coreboot-gerrit December 2023

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: vendorcode/amd/opensil: Add initial setup and API calls
by Varshit Pandya (Code Review) 05 Dec '23

05 Dec '23

Attention is currently required from: Arthur Heymans, Felix Held. Varshit Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76515?usp=email ) Change subject: vendorcode/amd/opensil: Add initial setup and API calls ...................................................................... Patch Set 7: (2 comments) File src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h: https://review.coreboot.org/c/coreboot/+/76515/comment/f7d95965_eae99a81 : PS6, Line 7: > might be good to do the whitespace changes in a separate patch. […] Done File src/vendorcode/amd/opensil/genoa_poc/ramstage.c: https://review.coreboot.org/c/coreboot/+/76515/comment/0fe020cb_857ae490 : PS6, Line 86: BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, opensil_entry, (void *)SIL_TP1); > we should probably look into removing the BOOT_STATE_INIT_ENTRY in this file and have the few calls […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/76515?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4833a5a86034a13e6be102a6b68c3bb54108bc9a Gerrit-Change-Number: 76515 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 05 Dec 2023 15:04:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: commonlib/bsd: Use tabs instead of whitespaces
by Varshit Pandya (Code Review) 05 Dec '23

05 Dec '23

Attention is currently required from: Arthur Heymans. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/79400?usp=email to review the following change. Change subject: commonlib/bsd: Use tabs instead of whitespaces ...................................................................... commonlib/bsd: Use tabs instead of whitespaces Change-Id: I05e7ba10e499ea1e824bdd6c87df05fc5a0864f8 Signed-off-by: Varshit Pandya <pandyavarshit(a)gmail.com> Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/79400/1 diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h index ff70152..724b592 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h @@ -4,7 +4,7 @@ #define _CBMEM_ID_H_ #define CBMEM_ID_ACPI 0x41435049 -#define CBMEM_ID_ACPI_BERT 0x42455254 +#define CBMEM_ID_ACPI_BERT 0x42455254 #define CBMEM_ID_ACPI_CNVS 0x434e5653 #define CBMEM_ID_ACPI_GNVS 0x474e5653 #define CBMEM_ID_ACPI_HEST 0x48455354 @@ -56,7 +56,7 @@ #define CBMEM_ID_ROMSTAGE_INFO 0x47545352 #define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4 #define CBMEM_ID_ROOT 0xff4007ff -#define CBMEM_ID_SMBIOS 0x534d4254 +#define CBMEM_ID_SMBIOS 0x534d4254 #define CBMEM_ID_SMM_SAVE_SPACE 0x07e9acee #define CBMEM_ID_STAGEx_META 0x57a9e000 #define CBMEM_ID_STAGEx_CACHE 0x57a9e100 @@ -167,7 +167,7 @@ { CBMEM_ID_FSP_LOGO, "FSP LOGO "}, \ { CBMEM_ID_SMM_COMBUFFER, "SMM COMBUFFER"}, \ { CBMEM_ID_TYPE_C_INFO, "TYPE_C INFO"},\ - { CBMEM_ID_MEM_CHIP_INFO, "MEM CHIP INFO"},\ + { CBMEM_ID_MEM_CHIP_INFO, "MEM CHIP INFO"},\ { CBMEM_ID_AMD_STB, "AMD STB"},\ { CBMEM_ID_AMD_MP2, "AMD MP2 BUFFER"},\ { CBMEM_ID_CSE_INFO, "CSE SPECIFIC INFO"},\ -- To view, visit https://review.coreboot.org/c/coreboot/+/79400?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I05e7ba10e499ea1e824bdd6c87df05fc5a0864f8 Gerrit-Change-Number: 79400 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: vendorcode/amd/opensil: Add initial setup and API calls
by Varshit Pandya (Code Review) 05 Dec '23

05 Dec '23

Attention is currently required from: Arthur Heymans, Martin L Roth. Varshit Pandya has uploaded a new patch set (#7) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/76515?usp=email ) The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: vendorcode/amd/opensil: Add initial setup and API calls ...................................................................... vendorcode/amd/opensil: Add initial setup and API calls - First a console is set up for opensil. - After that a region in CBMEM is reserved and passed to opensil which will use it as a buffer for input/output information. - Finally opensil is called and the return value handled. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I4833a5a86034a13e6be102a6b68c3bb54108bc9a --- M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h M src/vendorcode/amd/opensil/genoa_poc/Makefile.inc A src/vendorcode/amd/opensil/genoa_poc/ramstage.c 3 files changed, 92 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/76515/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/76515?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4833a5a86034a13e6be102a6b68c3bb54108bc9a Gerrit-Change-Number: 76515 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: acpi/acpi_gic: Add GIC ITS subtable
by Angel Pons (Code Review) 05 Dec '23

05 Dec '23

Attention is currently required from: Angel Pons, Arthur Heymans, Cliff Huang, Lance Zhao, Lean Sheng Tan, Maximilian Brune, Naresh Solanki, Nico Huber, Patrick Rudolph, Paul Menzel, Tim Wawrzynczak. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78115?usp=email ) Change subject: acpi/acpi_gic: Add GIC ITS subtable ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78115?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1bcb3ad24de64cbba8aeef7ba7254d3157e0dc43 Gerrit-Change-Number: 78115 Gerrit-PatchSet: 8 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Comment-Date: Tue, 05 Dec 2023 14:38:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/rex: Simplify power limit configuration usage
by Matt DeVillier (Code Review) 05 Dec '23

05 Dec '23

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79331?usp=email ) Change subject: mb/google/rex: Simplify power limit configuration usage ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: > > looks like u landed the patches out of order […] what was the previous patch that was missed? it didn't show in the relation chain -- To view, visit https://review.coreboot.org/c/coreboot/+/79331?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I872e5cb59d7b2789ef517d4a090189785db46b85 Gerrit-Change-Number: 79331 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 05 Dec 2023 14:27:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/intel/mtlrvp: add 512KB SI_EC FMAP region
by Paul Menzel (Code Review) 05 Dec '23

05 Dec '23

Attention is currently required from: Balaji Manigandan, Deepti Deshatty, Kapil Porwal, Krishna P Bhat D, Subrata Banik. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79209?usp=email ) Change subject: mb/intel/mtlrvp: add 512KB SI_EC FMAP region ...................................................................... Patch Set 7: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79209/comment/c3416b59_d8dd9578 : PS7, Line 19: TEST=build "emerge-rex coreboot chromeos-bootimage" is successful “and the changes are verified” sounds like you even runtime tested this. Maybe show the log line, stating the EC1723 loaded the firmware. (Feel free to ignore the comment, but keep it mind for next time.) -- To view, visit https://review.coreboot.org/c/coreboot/+/79209?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I788dbeaad05e5d6904fb2c7c681a0bf653dc7d84 Gerrit-Change-Number: 79209 Gerrit-PatchSet: 7 Gerrit-Owner: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Deepti Deshatty <deepti.deshatty(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Comment-Date: Tue, 05 Dec 2023 14:20:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: [test][Do not merge] Revert "arch/x86: Reduce max phys address size f...
by Ronak Kanabar (Code Review) 05 Dec '23

05 Dec '23

Ronak Kanabar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79399?usp=email ) Change subject: [test][Do not merge] Revert "arch/x86: Reduce max phys address size for Intel TME capable SoCs" ...................................................................... [test][Do not merge] Revert "arch/x86: Reduce max phys address size for Intel TME capable SoCs" This reverts commit 1eff77bc59b77735872e675a8df4f059245e4be7. Change-Id: If4249b65f4294b38b0721d1a3ba577e87766f547 --- M src/arch/x86/cpu_common.c M src/arch/x86/include/arch/cpu.h M src/cpu/intel/common/Makefile.inc M src/cpu/intel/common/common_init.c M src/include/cpu/intel/msr.h 5 files changed, 2 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/79399/1 diff --git a/src/arch/x86/cpu_common.c b/src/arch/x86/cpu_common.c index 0242dce..ebd13c9 100644 --- a/src/arch/x86/cpu_common.c +++ b/src/arch/x86/cpu_common.c @@ -49,11 +49,8 @@ if (!(cpu_have_cpuid())) return 32; - if (cpu_cpuid_extended_level() >= 0x80000008) { - int size = cpuid_eax(0x80000008) & 0xff; - size -= get_reserved_phys_addr_bits(); - return size; - } + if (cpu_cpuid_extended_level() >= 0x80000008) + return cpuid_eax(0x80000008) & 0xff; if (cpuid_edx(1) & (CPUID_FEATURE_PAE | CPUID_FEATURE_PSE36)) return 36; diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 0c4decf..aca0d46 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -329,15 +329,4 @@ */ bool fill_cpu_cache_info(uint8_t level, struct cpu_cache_info *info); -#if CONFIG(RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT) -unsigned int get_reserved_phys_addr_bits(void); -#else -/* Default implementation */ -static inline unsigned int get_reserved_phys_addr_bits(void) -{ - /* Default implementation */ - return 0; -} -#endif - #endif /* ARCH_CPU_H */ diff --git a/src/cpu/intel/common/Makefile.inc b/src/cpu/intel/common/Makefile.inc index 8b247ab..c4ac57e 100644 --- a/src/cpu/intel/common/Makefile.inc +++ b/src/cpu/intel/common/Makefile.inc @@ -1,8 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only -bootblock-$(CONFIG_CPU_INTEL_COMMON) += common_init.c romstage-$(CONFIG_CPU_INTEL_COMMON) += common_init.c -postcar-$(CONFIG_CPU_INTEL_COMMON) += common_init.c ramstage-$(CONFIG_CPU_INTEL_COMMON) += common_init.c ramstage-$(CONFIG_CPU_INTEL_COMMON) += hyperthreading.c ramstage-$(CONFIG_CPU_INTEL_COMMON_VOLTAGE) += voltage.c diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c index 83a21e0..f8608ae 100644 --- a/src/cpu/intel/common/common_init.c +++ b/src/cpu/intel/common/common_init.c @@ -238,31 +238,3 @@ cpuid_regs = cpuid_ext(CPUID_STRUCT_EXTENDED_FEATURE_FLAGS, 0x0); return (cpuid_regs.ecx & CPUID_EXT_FEATURE_TME_SUPPORTED); } - -/* - * Get number of address bits used by Total Memory Encryption (TME) - * - * Returns TME_ACTIVATE[MK_TME_KEYID_BITS] (MSR 0x982 Bits[32-35]). - * - * NOTE: This function should be called after MK-TME features has been - * configured in the MSRs according to the capabilities and platform - * configuration. For instance, after FSP-M. - */ -static unsigned int get_tme_keyid_bits(void) -{ - msr_t msr; - - msr = rdmsr(MSR_TME_ACTIVATE); - return msr.hi & TME_ACTIVATE_HI_KEYID_BITS_MASK; -} - -unsigned int get_reserved_phys_addr_bits(void) -{ - if (CONFIG_CPU_INTEL_COMMON_RESERVED_PHYS_ADDR_BITS) - return CONFIG_CPU_INTEL_COMMON_RESERVED_PHYS_ADDR_BITS; - - if (!is_tme_supported()) - return 0; - - return get_tme_keyid_bits(); -} diff --git a/src/include/cpu/intel/msr.h b/src/include/cpu/intel/msr.h index 75c12a8..8efe4e2 100644 --- a/src/include/cpu/intel/msr.h +++ b/src/include/cpu/intel/msr.h @@ -33,7 +33,4 @@ #define MSR_PKG_C10_RESIDENCY 0x632 -#define MSR_TME_ACTIVATE 0x982 -#define TME_ACTIVATE_HI_KEYID_BITS_MASK 0xf - #endif /* CPU_INTEL_MSR_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/79399?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If4249b65f4294b38b0721d1a3ba577e87766f547 Gerrit-Change-Number: 79399 Gerrit-PatchSet: 1 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: acpi/acpi_gic: Add GIC ITS subtable
by Naresh Solanki (Code Review) 05 Dec '23

05 Dec '23

Attention is currently required from: Angel Pons, Angel Pons, Arthur Heymans, Cliff Huang, Lance Zhao, Lean Sheng Tan, Maximilian Brune, Nico Huber, Patrick Rudolph, Paul Menzel, Tim Wawrzynczak. Naresh Solanki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78115?usp=email ) Change subject: acpi/acpi_gic: Add GIC ITS subtable ...................................................................... Patch Set 7: (1 comment) File src/acpi/acpi_gic.c: https://review.coreboot.org/c/coreboot/+/78115/comment/b46a9414_684b11ef : PS7, Line 100: sizeof(acpi_madt_gic_its_t) > Sorry, forgot to mark this one too. […] NP. Will restore to patchset 6. -- To view, visit https://review.coreboot.org/c/coreboot/+/78115?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1bcb3ad24de64cbba8aeef7ba7254d3157e0dc43 Gerrit-Change-Number: 78115 Gerrit-PatchSet: 7 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Comment-Date: Tue, 05 Dec 2023 12:10:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/nissa/var/quandiso: Update P-sensor tuning
by Sumeet R Pawnikar (Code Review) 05 Dec '23

05 Dec '23

Attention is currently required from: Eric Lai, Nick Vaccaro, Robert Chen, Subrata Banik. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79247?usp=email ) Change subject: mb/google/nissa/var/quandiso: Update P-sensor tuning ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79247?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7c687677a797415d80be4c420484d3346a8455f6 Gerrit-Change-Number: 79247 Gerrit-PatchSet: 7 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 05 Dec 2023 11:41:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: acpi/acpi_gic: Add GIC ITS subtable
by Angel Pons (Code Review) 05 Dec '23

05 Dec '23

Attention is currently required from: Angel Pons, Arthur Heymans, Cliff Huang, Lance Zhao, Lean Sheng Tan, Maximilian Brune, Naresh Solanki, Nico Huber, Patrick Rudolph, Paul Menzel, Tim Wawrzynczak. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78115?usp=email ) Change subject: acpi/acpi_gic: Add GIC ITS subtable ...................................................................... Patch Set 7: Code-Review+1 (1 comment) File src/acpi/acpi_gic.c: https://review.coreboot.org/c/coreboot/+/78115/comment/6f388977_ee88be90 : PS7, Line 100: sizeof(acpi_madt_gic_its_t) Sorry, forgot to mark this one too. But I've just noticed that the rest of the file uses `sizeof(acpi_madt_gic_its_t)`, so maybe let's keep it as on patchset 6. Apologies for the noise. -- To view, visit https://review.coreboot.org/c/coreboot/+/78115?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1bcb3ad24de64cbba8aeef7ba7254d3157e0dc43 Gerrit-Change-Number: 78115 Gerrit-PatchSet: 7 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Comment-Date: Tue, 05 Dec 2023 11:08:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit December 2023