coreboot-gerrit December 2023

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[M] Change in coreboot[main]: vendorcode/amd/opensil: Add initial setup and API calls
by Felix Held (Code Review) 05 Dec '23

05 Dec '23

Attention is currently required from: Arthur Heymans, Varshit Pandya. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76515?usp=email ) Change subject: vendorcode/amd/opensil: Add initial setup and API calls ...................................................................... Patch Set 8: Code-Review+2 (2 comments) File src/vendorcode/amd/opensil/genoa_poc/ramstage.c: https://review.coreboot.org/c/coreboot/+/76515/comment/fa7af880_cf0d34fa : PS7, Line 14: error_string > might be good to rename this struct to avoid confusion. […] Done https://review.coreboot.org/c/coreboot/+/76515/comment/69ba4cb6_e6e3ba5f : PS7, Line 86: /* TODO Find a better place for BOOT_STATE_INIT_ENTRY */ > maybe reword this to something like: […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/76515?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4833a5a86034a13e6be102a6b68c3bb54108bc9a Gerrit-Change-Number: 76515 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 05 Dec 2023 15:46:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: vendorcode/amd/opensil: Add initial setup and API calls
by Varshit Pandya (Code Review) 05 Dec '23

05 Dec '23

Attention is currently required from: Arthur Heymans, Varshit Pandya. Varshit Pandya has uploaded a new patch set (#8) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/76515?usp=email ) The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: vendorcode/amd/opensil: Add initial setup and API calls ...................................................................... vendorcode/amd/opensil: Add initial setup and API calls - First a console is set up for opensil. - After that a region in CBMEM is reserved and passed to opensil which will use it as a buffer for input/output information. - Finally opensil is called and the return value handled. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I4833a5a86034a13e6be102a6b68c3bb54108bc9a --- M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h M src/vendorcode/amd/opensil/genoa_poc/Makefile.inc A src/vendorcode/amd/opensil/genoa_poc/ramstage.c 3 files changed, 93 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/76515/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/76515?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4833a5a86034a13e6be102a6b68c3bb54108bc9a Gerrit-Change-Number: 76515 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: sb/intel/bd82x6x: assign PCH XHCI controller ops in chipset devicetree
by Patrick Rudolph (Code Review) 05 Dec '23

05 Dec '23

Attention is currently required from: Felix Held. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79170?usp=email ) Change subject: sb/intel/bd82x6x: assign PCH XHCI controller ops in chipset devicetree ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79170?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8685bec734415346a53330c9bd1aa82986995f1a Gerrit-Change-Number: 79170 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 05 Dec 2023 15:19:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: sb/intel/bd82x6x: assign PCH PCI bridge ops in chipset devicetree
by Patrick Rudolph (Code Review) 05 Dec '23

05 Dec '23

Attention is currently required from: Felix Held. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79169?usp=email ) Change subject: sb/intel/bd82x6x: assign PCH PCI bridge ops in chipset devicetree ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79169?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic9ca925a12e64c9a5b3bf295653bf032572ff29a Gerrit-Change-Number: 79169 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 05 Dec 2023 15:19:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: sb/intel/bd82x6x: assign PCH SMBus controller ops in chipset devicetree
by Patrick Rudolph (Code Review) 05 Dec '23

05 Dec '23

Attention is currently required from: Felix Held. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79168?usp=email ) Change subject: sb/intel/bd82x6x: assign PCH SMBus controller ops in chipset devicetree ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79168?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3d3745ba5aefa30efbe705155d216aa7eadd26a7 Gerrit-Change-Number: 79168 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 05 Dec 2023 15:19:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: vendorcode/amd/opensil: Add initial setup and API calls
by Felix Held (Code Review) 05 Dec '23

05 Dec '23

Attention is currently required from: Arthur Heymans, Varshit Pandya. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76515?usp=email ) Change subject: vendorcode/amd/opensil: Add initial setup and API calls ...................................................................... Patch Set 7: (2 comments) File src/vendorcode/amd/opensil/genoa_poc/ramstage.c: https://review.coreboot.org/c/coreboot/+/76515/comment/84baa037_12583d71 : PS7, Line 14: error_string might be good to rename this struct to avoid confusion. error_string_entry maybe? or drop the struct name altogether? https://review.coreboot.org/c/coreboot/+/76515/comment/e0b5fb60_46d30299 : PS7, Line 86: /* TODO Find a better place for BOOT_STATE_INIT_ENTRY */ maybe reword this to something like: TODO: look into calling these functions from some SoC device operations instead of using BOOT_STATE_INIT_ENTRY -- To view, visit https://review.coreboot.org/c/coreboot/+/76515?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4833a5a86034a13e6be102a6b68c3bb54108bc9a Gerrit-Change-Number: 76515 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 05 Dec 2023 15:14:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/nissa/var/quandiso: Update P-sensor tuning
by Eric Lai (Code Review) 05 Dec '23

05 Dec '23

Attention is currently required from: Nick Vaccaro, Robert Chen, Subrata Banik. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79247?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/nissa/var/quandiso: Update P-sensor tuning ...................................................................... Patch Set 7: (1 comment) File src/mainboard/google/brya/variants/quandiso/gpio.c: https://review.coreboot.org/c/coreboot/+/79247/comment/4ccc5c5e_7995f11d : PS7, Line 19: /* B5 : I2C2_SDA ==> I2C_P_SENSOR_SDA */ please also describe the gpio change in comment. -- To view, visit https://review.coreboot.org/c/coreboot/+/79247?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7c687677a797415d80be4c420484d3346a8455f6 Gerrit-Change-Number: 79247 Gerrit-PatchSet: 7 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 05 Dec 2023 15:09:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/rex: Simplify power limit configuration usage
by Subrata Banik (Code Review) 05 Dec '23

05 Dec '23

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79331?usp=email ) Change subject: mb/google/rex: Simplify power limit configuration usage ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: > what was the previous patch that was missed? it didn't show in the relation chain yes, :) no worries, i have landed that almosst immediately -- To view, visit https://review.coreboot.org/c/coreboot/+/79331?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I872e5cb59d7b2789ef517d4a090189785db46b85 Gerrit-Change-Number: 79331 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 05 Dec 2023 15:08:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: commonlib/bsd: Use tabs instead of whitespaces
by Felix Held (Code Review) 05 Dec '23

05 Dec '23

Attention is currently required from: Arthur Heymans, Varshit Pandya. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79400?usp=email ) Change subject: commonlib/bsd: Use tabs instead of whitespaces ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79400?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I05e7ba10e499ea1e824bdd6c87df05fc5a0864f8 Gerrit-Change-Number: 79400 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 05 Dec 2023 15:07:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: sb/intel/bd82x6x: assign PCH LPC bridge ops in chipset devicetree
by Felix Held (Code Review) 05 Dec '23

05 Dec '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79167?usp=email ) Change subject: sb/intel/bd82x6x: assign PCH LPC bridge ops in chipset devicetree ...................................................................... sb/intel/bd82x6x: assign PCH LPC bridge ops in chipset devicetree Since the LPC bridge in the PCH is always on the same device function, the device operations can be statically assigned in the devicetree and there's no need to bind the LPC bridge device operations to the PCI device during runtime via a list of PCI IDs. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I366226be4aba75b98e45e4832bfe129fac14dbfa Reviewed-on: https://review.coreboot.org/c/coreboot/+/79167 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/northbridge/intel/sandybridge/chipset.cb M src/southbridge/intel/bd82x6x/lpc.c 2 files changed, 2 insertions(+), 25 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Patrick Rudolph: Looks good to me, approved diff --git a/src/northbridge/intel/sandybridge/chipset.cb b/src/northbridge/intel/sandybridge/chipset.cb index a08b1bd..83680c1 100644 --- a/src/northbridge/intel/sandybridge/chipset.cb +++ b/src/northbridge/intel/sandybridge/chipset.cb @@ -37,7 +37,7 @@ device pci 1c.7 alias pcie_rp8 off ops bd82x6x_pcie_rp_ops end # PCIe Port #8 device pci 1d.0 alias ehci1 off end # USB2 EHCI #1 device pci 1e.0 alias pci_bridge off end # PCI bridge - device pci 1f.0 alias lpc on end # LPC bridge + device pci 1f.0 alias lpc on ops bd82x6x_lpc_bridge_ops end device pci 1f.2 alias sata1 off end # SATA Controller 1 device pci 1f.3 alias smbus on end # SMBus device pci 1f.5 alias sata2 off end # SATA Controller 2 diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 0cf7b9c..5d1a7bf 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -658,7 +658,7 @@ memcpy(spi_config, &config->spi, sizeof(*spi_config)); } -static struct device_operations device_ops = { +struct device_operations bd82x6x_lpc_bridge_ops = { .read_resources = pch_lpc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, @@ -671,26 +671,3 @@ .scan_bus = scan_static_bus, .ops_pci = &pci_dev_ops_pci, }; - -/* IDs for LPC device of Intel 6 Series Chipset, Intel 7 Series Chipset, and - * Intel C200 Series Chipset - */ - -static const unsigned short pci_device_ids[] = { - 0x1c40, 0x1c41, 0x1c42, 0x1c43, 0x1c44, 0x1c45, 0x1c46, 0x1c47, 0x1c48, - 0x1c49, 0x1c4a, 0x1c4b, 0x1c4c, 0x1c4d, 0x1c4e, 0x1c4f, 0x1c50, 0x1c51, - 0x1c52, 0x1c53, 0x1c54, 0x1c55, 0x1c56, 0x1c57, 0x1c58, 0x1c59, 0x1c5a, - 0x1c5b, 0x1c5c, 0x1c5d, 0x1c5e, 0x1c5f, - - 0x1e41, 0x1e42, 0x1e43, 0x1e44, 0x1e45, 0x1e46, 0x1e47, 0x1e48, 0x1e49, - 0x1e4a, 0x1e4b, 0x1e4c, 0x1e4d, 0x1e4e, 0x1e4f, 0x1e50, 0x1e51, 0x1e52, - 0x1e53, 0x1e54, 0x1e55, 0x1e56, 0x1e57, 0x1e58, 0x1e59, 0x1e5a, 0x1e5b, - 0x1e5c, 0x1e5d, 0x1e5e, 0x1e5f, - - 0 }; - -static const struct pci_driver pch_lpc __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VID_INTEL, - .devices = pci_device_ids, -}; -- To view, visit https://review.coreboot.org/c/coreboot/+/79167?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I366226be4aba75b98e45e4832bfe129fac14dbfa Gerrit-Change-Number: 79167 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit December 2023