coreboot-gerrit December 2023

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[XS] Change in coreboot[main]: acpi: add missing device/device.h include
by Felix Held (Code Review) 05 Dec '23

05 Dec '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79401?usp=email ) Change subject: acpi: add missing device/device.h include ...................................................................... acpi: add missing device/device.h include The device/device.h provides the definition for struct device used in those files, so include this header file to make sure that it's not only included indirectly via some other header file. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I6ff7cdbf0f53ada92adb53cf268e5feee9df4629 --- M src/acpi/acpi.c M src/acpi/acpi_apic.c M src/acpi/acpi_gic.c M src/acpi/acpi_hpet.c M src/acpi/acpigen_usb.c 5 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/79401/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index c4d55ab..35464b8 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -21,6 +21,7 @@ #include <commonlib/helpers.h> #include <console/console.h> #include <cpu/cpu.h> +#include <device/device.h> #include <device/mmio.h> #include <device/pci.h> #include <drivers/uart/pl011.h> diff --git a/src/acpi/acpi_apic.c b/src/acpi/acpi_apic.c index f952d0a..d6937fc 100644 --- a/src/acpi/acpi_apic.c +++ b/src/acpi/acpi_apic.c @@ -5,6 +5,7 @@ #include <arch/smp/mpspec.h> #include <commonlib/sort.h> #include <cpu/cpu.h> +#include <device/device.h> static int acpi_create_madt_lapic(acpi_madt_lapic_t *lapic, u8 cpu, u8 apic) { diff --git a/src/acpi/acpi_gic.c b/src/acpi/acpi_gic.c index e9ae370c..e259ea1 100644 --- a/src/acpi/acpi_gic.c +++ b/src/acpi/acpi_gic.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <device/device.h> static int acpi_create_madt_one_gicc_v3(acpi_madt_gicc_t *gicc, u32 acpi_uid, u32 pi_gsiv, uint32_t vgic_mi, uint64_t mpidr) diff --git a/src/acpi/acpi_hpet.c b/src/acpi/acpi_hpet.c index 9f91829..fbf8529 100644 --- a/src/acpi/acpi_hpet.c +++ b/src/acpi/acpi_hpet.c @@ -3,6 +3,7 @@ #include <acpi/acpi.h> #include <arch/hpet.h> #include <console/console.h> +#include <device/device.h> #include <device/mmio.h> #include <version.h> diff --git a/src/acpi/acpigen_usb.c b/src/acpi/acpigen_usb.c index e71e6da..221a215 100644 --- a/src/acpi/acpigen_usb.c +++ b/src/acpi/acpigen_usb.c @@ -4,6 +4,7 @@ #include <acpi/acpi_pld.h> #include <acpi/acpigen.h> #include <acpi/acpigen_usb.h> +#include <device/device.h> static const char *power_role_to_str(enum usb_typec_power_role power_role) { -- To view, visit https://review.coreboot.org/c/coreboot/+/79401?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6ff7cdbf0f53ada92adb53cf268e5feee9df4629 Gerrit-Change-Number: 79401 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[XL] Change in coreboot[main]: payloads: Add uefistub payload
by Simon Glass (Code Review) 05 Dec '23

05 Dec '23

Attention is currently required from: Benjamin Doron, Martin L Roth, Maximilian Brune, Patrick Rudolph. Simon Glass has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78913?usp=email ) Change subject: payloads: Add uefistub payload ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: > > Why do we need to pull pieces out of U-Boot to achieve this? It doesn't seem a very friendly appro […] Hi Maximillian, Re solution 2, let's work together on that, instead of this effort! For 64-bit SMBIOS (I suppose the SMBIOS3 header) there is a patch[1] but it needs a bit of work, or perhaps that has already been done. In any case, I can help, or Heinrich / others on the ML. For ACPI, can you share your working code? The ACPI code is now fairly generic so enabling it on ARM should not be difficult. Of course any new thing has challenges. We have enough forking going on in private projects. I would really like to see more collaboration between coreboot and U-Boot. I did do some fiddling on U-Boot as a library a while back. It is a big effort though...so using the existing payload seems a lot easier. [1] https://patchwork.ozlabs.org/project/uboot/patch/20231008213646.622002-4-sj… -- To view, visit https://review.coreboot.org/c/coreboot/+/78913?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4093378e89c3cb43fb0846666de80a7da36b03f1 Gerrit-Change-Number: 78913 Gerrit-PatchSet: 4 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Simon Glass <sjg(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Tue, 05 Dec 2023 18:58:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Comment-In-Reply-To: Simon Glass <sjg(a)chromium.org> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: nb/amd/pi/00730F01/chipset.cb: don't call dummy function host bridge
by Matt DeVillier (Code Review) 05 Dec '23

05 Dec '23

Attention is currently required from: Felix Held. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79397?usp=email ) Change subject: nb/amd/pi/00730F01/chipset.cb: don't call dummy function host bridge ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79397?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6069205bd2e1cb0f75025e9f330afc50462e742a Gerrit-Change-Number: 79397 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 05 Dec 2023 18:50:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/amd/*/chipset.cb: don't call dummy device functions host bridges
by Matt DeVillier (Code Review) 05 Dec '23

05 Dec '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Martin L Roth, Nico Huber, Varshit Pandya. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79396?usp=email ) Change subject: soc/amd/*/chipset.cb: don't call dummy device functions host bridges ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79396?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibddfdf558d84bc44434d718b86f41bd06044b22a Gerrit-Change-Number: 79396 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 05 Dec 2023 18:50:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/brox: Fix memory config
by Shelley Chen (Code Review) 05 Dec '23

05 Dec '23

Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79355?usp=email ) Change subject: mb/google/brox: Fix memory config ...................................................................... Patch Set 7: (1 comment) File src/mainboard/google/brox/variants/baseboard/brox/memory.c: https://review.coreboot.org/c/coreboot/+/79355/comment/beff2e1f_a813c699 : PS7, Line 13: .lpx_dq_map = { : .ddr0 = { : .dq0 = { 4, 7, 5, 6, 0, 1, 2, 3, }, : .dq1 = { 8, 11, 9, 10, 13, 14, 15, 12, }, : }, : .ddr1 = { : .dq0 = { 1, 2, 3, 0, 6, 4, 7, 5, }, : .dq1 = { 13, 15, 12, 14, 8, 11, 9, 10, }, : }, : .ddr2 = { : .dq0 = { 0, 3, 2, 1, 6, 5, 7, 4, }, : .dq1 = { 14, 12, 15, 13, 8, 10, 9, 11, }, : }, : .ddr3 = { : .dq0 = { 5, 7, 4, 6, 2, 0, 1, 3, }, : .dq1 = { 10, 9, 11, 8, 12, 15, 13, 14, }, : }, : .ddr4 = { : .dq0 = { 4, 6, 5, 7, 3, 2, 1, 0, }, : .dq1 = { 8, 11, 9, 10, 14, 13, 15, 12, }, : }, : .ddr5 = { : .dq0 = { 2, 1, 3, 0, 6, 4, 7, 5, }, : .dq1 = { 13, 15, 12, 14, 8, 11, 9, 10, }, : }, : .ddr6 = { : .dq0 = { 14, 12, 15, 13, 8, 11, 10, 9, }, : .dq1 = { 1, 2, 3, 0, 5, 6, 7, 4, }, : }, : .ddr7 = { : .dq0 = { 3, 6, 2, 7, 5, 0, 1, 4, }, : .dq1 = { 9, 8, 14, 15, 10, 12, 13, 11, }, : }, : }, : : /* DQS CPU<>DRAM map */ : .lpx_dqs_map = { : .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, : .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, : .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, : .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, : .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, : .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, : .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, : .ddr7 = { .dqs0 = 0, .dqs1 = 1 } : }, : : .lp5x_config = { : .ccc_config = 0x99, : }, > Where did you get these values from? Hi Paul, as mentioned in the comments this was from the brox schematics and defines how the Soc connects to the DRAM. Unfortunately, the schematics are not open right now, but the way that these connections are defined are done exactly the same way as other existing Intel boards. -- To view, visit https://review.coreboot.org/c/coreboot/+/79355?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I17615cda7df10e73e49fb49f736728787ef7625d Gerrit-Change-Number: 79355 Gerrit-PatchSet: 7 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 05 Dec 2023 18:39:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: acpi/acpi: make sure that table_ptr is non-NULL in acpidump_print
by Martin L Roth (Code Review) 05 Dec '23

05 Dec '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79393?usp=email ) Change subject: acpi/acpi: make sure that table_ptr is non-NULL in acpidump_print ...................................................................... acpi/acpi: make sure that table_ptr is non-NULL in acpidump_print While acpidump_print shouldn't be called with a NULL pointer as table_ptr argument, better add a check to not end up dereferencing the NULL pointer. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ic3cc103c8a47fb8c2fe4262236ea47013af27c4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/79393 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland(a)gmail.com> --- M src/acpi/acpi.c 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: Tim Wawrzynczak: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index e40d4ac..c4d55ab 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -1367,6 +1367,8 @@ static void acpidump_print(void *table_ptr) { + if (table_ptr == NULL) + return; const acpi_header_t *header = (acpi_header_t *)table_ptr; const size_t table_size = header->length; printk(BIOS_SPEW, "%.4s @ 0x0000000000000000\n", header->signature); -- To view, visit https://review.coreboot.org/c/coreboot/+/79393?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic3cc103c8a47fb8c2fe4262236ea47013af27c4f Gerrit-Change-Number: 79393 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: soc/amd/common/pci: Add weak impl. of get_pci_routing_table()
by Martin L Roth (Code Review) 05 Dec '23

05 Dec '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79018?usp=email ) Change subject: soc/amd/common/pci: Add weak impl. of get_pci_routing_table() ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79018/comment/9ec53a66_5f047d34 : PS1, Line 11: and make use of other functions provided therein. Is this just a temporary change that's going to be removed? Would it be better just to implement an empty function directly in Genoa with the understanding that it needs to be filled in at some point? -- To view, visit https://review.coreboot.org/c/coreboot/+/79018?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I873a528f02018bf5c6975bbcee8fbc4b123a06f7 Gerrit-Change-Number: 79018 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 05 Dec 2023 18:35:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/amd/common/acpi: Add weak CPPC min/nomimal functions
by Martin L Roth (Code Review) 05 Dec '23

05 Dec '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Nico Huber. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79017?usp=email ) Change subject: soc/amd/common/acpi: Add weak CPPC min/nomimal functions ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79017/comment/33e0697b_c072e780 : PS1, Line 11: allow SoCs not using FSP to use the CPPC common code as well. > Having alternative implementations doesn't necessarily require weak […] Agreed. How do the non-FSP platforms get the values, or do they not need to? -- To view, visit https://review.coreboot.org/c/coreboot/+/79017?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3cea9b0a8e11aff1949fedbbecba575b351c1706 Gerrit-Change-Number: 79017 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 05 Dec 2023 18:33:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: vc/amd/psp: Remove unknown section flags
by Martin L Roth (Code Review) 05 Dec '23

05 Dec '23

Attention is currently required from: Arthur Heymans, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Zebreus. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79366?usp=email ) Change subject: vc/amd/psp: Remove unknown section flags ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: This needs to be tested before it can be merged. Unfortunately, I don't remember what this was supposed to do either, since this code was written a number of years ago. Hopefully we can just compile with and without the flag and see whether or not anything changes. -- To view, visit https://review.coreboot.org/c/coreboot/+/79366?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie3735b72349b0cfdd27364a39bcdda390af7bfa5 Gerrit-Change-Number: 79366 Gerrit-PatchSet: 2 Gerrit-Owner: Zebreus <lennarteichhorn(a)googlemail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zebreus <lennarteichhorn(a)googlemail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 05 Dec 2023 17:18:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: [test][Do not merge] Revert "arch/x86: Reduce max phys address size f...
by Ronak Kanabar (Code Review) 05 Dec '23

05 Dec '23

Attention is currently required from: Jérémy Compostella. Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79399?usp=email ) Change subject: [test][Do not merge] Revert "arch/x86: Reduce max phys address size for Intel TME capable SoCs" ...................................................................... Patch Set 1: Code-Review-1 (1 comment) Patchset: PS1: > Investigation in progress. just a test patch so we can use it in build tools -- To view, visit https://review.coreboot.org/c/coreboot/+/79399?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If4249b65f4294b38b0721d1a3ba577e87766f547 Gerrit-Change-Number: 79399 Gerrit-PatchSet: 1 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Tue, 05 Dec 2023 16:34:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: comment

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coreboot-gerrit December 2023