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Change subject: mb/google/nissa/var/quandiso: Update P-sensor tuning
......................................................................
Patch Set 8: Code-Review+2
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Change subject: mb/google/nissa/var/quandiso: Update P-sensor tuning
......................................................................
Patch Set 8:
(1 comment)
File src/mainboard/google/brya/variants/quandiso/gpio.c:
https://review.coreboot.org/c/coreboot/+/79247/comment/3ab9680e_f31887a9 :
PS7, Line 19: /* B5 : I2C2_SDA ==> I2C_P_SENSOR_SDA */
> please also describe the gpio change in comment.
Done
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Hello Eric Lai, Nick Vaccaro, Subrata Banik, Sumeet R Pawnikar, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#8).
Change subject: mb/google/nissa/var/quandiso: Update P-sensor tuning
......................................................................
mb/google/nissa/var/quandiso: Update P-sensor tuning
Update proximity sensor tuning value copied from kracko.
Remove gpio override to leverage from nissa baseboard:
- GPP_B5 ==> SOC_I2C_SUB_SDA
- GPP_B6 ==> SOC_I2C_SUB_SCL
BUG=b:310050220
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I7c687677a797415d80be4c420484d3346a8455f6
Signed-off-by: Robert Chen <robert.chen(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/variants/quandiso/gpio.c
M src/mainboard/google/brya/variants/quandiso/overridetree.cb
3 files changed, 16 insertions(+), 48 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/79247/8
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Change subject: util/docker/fedora: Add Dockerfile.base
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS5:
> Needs this so that it's actually able to pass what-jenkins-does https://chromium-review. […]
Updating submodule pointer CB:79402
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Change subject: 3rdparty/intel-microcode: Update submodule to upstream main
......................................................................
3rdparty/intel-microcode: Update submodule to upstream main
Updating from commit id 6788bb0:
2023-08-08 12:04:21 -0600 - (microcode-20230808 Release)
to commit id ece0d29:
2023-11-14 10:19:09 -0600 - (microcode-20231114 Release)
This brings in 1 new commits:
ece0d29 microcode-20231114 Release
Change-Id: I1d65318015803d5ca11dcf52e4011f49cf3129a1
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M 3rdparty/intel-microcode
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/79403/1
diff --git a/3rdparty/intel-microcode b/3rdparty/intel-microcode
index 6788bb0..ece0d29 160000
--- a/3rdparty/intel-microcode
+++ b/3rdparty/intel-microcode
@@ -1 +1 @@
-Subproject commit 6788bb07eb5f9e9b83c31ea1364150fe898f450a
+Subproject commit ece0d294a29a1375397941a4e6f2f7217910bc89
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Change subject: 3rdparty/vboot: Update submodule to upstream main
......................................................................
3rdparty/vboot: Update submodule to upstream main
Updating from commit id ba7fd22d:
2023-11-29 01:50:20 +0000 - (Makefile: Always link libdl)
to commit id db533497:
2023-12-05 20:09:44 +0000 - (host/lib/pkcs11: Remove superfluous 'nss' directory from include paths)
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3307f1a7 tlcl: Add `TlclEvictControl()` support
0bd01137 tlcl: Remove the redundant bytes in TlclReadPublic
9afdf0f2 sign_official_build.sh: stop messing with +x
Change-Id: Ib2ded699605dfa4032f4687e1e336297c0af1372
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M 3rdparty/vboot
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/79402/1
diff --git a/3rdparty/vboot b/3rdparty/vboot
index ba7fd22..db53349 160000
--- a/3rdparty/vboot
+++ b/3rdparty/vboot
@@ -1 +1 @@
-Subproject commit ba7fd22d3dd659b3ab42ad66f22169a6ce0f4dfe
+Subproject commit db53349726e2948e07452fea5680381861928f66
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Change subject: acpi: add missing device/device.h include
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/intel/xeon_sp: Redesign resource allocation
......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/xeon_sp/chip_common.c:
https://review.coreboot.org/c/coreboot/+/78327/comment/3844ae65_88e47b55 :
PS4, Line 112: .scan_bus = non_iio_pci_domain_scan_bus,
> yeah ... integrated_iio_stack_... is a good idea. […]
Hi Nico, Arthur,
For these integrated iio stacks, suggestions coming from intel silicon team is ioat stacks (IO accelerator stack), a.k.a. iio_pci_domain_xxx v.s. iio_ioat_domain_xxx. Your opinion?
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Change subject: mb/google/brox: Update configuration for USB ports
......................................................................
Patch Set 4:
(9 comments)
This change is ready for review.
Commit Message:
https://review.coreboot.org/c/coreboot/+/79391/comment/7e627dbd_53853fd4 :
PS1, Line 9: and TCP
> Also mention in the summary?
Done
https://review.coreboot.org/c/coreboot/+/79391/comment/0d10f6ff_4f46dc21 :
PS1, Line 9: Update brox USB2/3 and TCP ports based on schematics.
> Please mention the version.
Done
File src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/79391/comment/cfa11864_f3d67ecd :
PS1, Line 31: OC_SKIP
> OC2 here as well?
Done
https://review.coreboot.org/c/coreboot/+/79391/comment/0d0ebda0_2217013a :
PS1, Line 33: OC_SKIP
> Is this supposed to be OC1? I see that in the schematics USB_OC1_L is attached to USB_A0_OC_ODL.
Done
https://review.coreboot.org/c/coreboot/+/79391/comment/97352bc1_3b246232 :
PS1, Line 36: DCI
> Is this Type A port A0? Also should it be OC1 like previous comment above?
Done
File src/mainboard/google/brox/variants/brox/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/79391/comment/d6d50bfc_a44124a5 :
PS1, Line 3: device ref pch_espi on
: chip ec/google/chromeec
: use conn0 as mux_conn[0]
: use conn1 as mux_conn[1]
: device pnp 0c09.0 on end
: end
: end
> Mention that in the commit message?
Done
https://review.coreboot.org/c/coreboot/+/79391/comment/afae5803_c770037f :
PS1, Line 81: end
> Missing port A0 config
Done
https://review.coreboot.org/c/coreboot/+/79391/comment/7b677777_6a48eac3 :
PS1, Line 84: register "type" = "UPC_TYPE_INTERNAL"
> has_power_resource = 1?
Done
https://review.coreboot.org/c/coreboot/+/79391/comment/1b08c45e_637a52ce :
PS1, Line 87: end
> Similarly missing USB3 config for port A0.
Done
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Change subject: soc/intel/common,mtl: Refactor BERT generation flow for crashlog
......................................................................
Patch Set 6: Code-Review-1
(1 comment)
Patchset:
PS6:
we are discussing some brokenness due to resource allocator, kindly wait to merge this CL.
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