coreboot-gerrit October 2023

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: vc/intel/fsp/mtl: Export pre-memory graphics FSP-M UPDs
by Subrata Banik (Code Review) 30 Oct '23

30 Oct '23

Attention is currently required from: Jérémy Compostella. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78654?usp=email ) Change subject: vc/intel/fsp/mtl: Export pre-memory graphics FSP-M UPDs ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: as mentioned earlier, please file a bug to capture all newly added UPD into FSP partial header. We need to first land the FSP code changes internally. -- To view, visit https://review.coreboot.org/c/coreboot/+/78654?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iff4467720541efbdedace12431cd1f6f66fca8e7 Gerrit-Change-Number: 78654 Gerrit-PatchSet: 3 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Mon, 30 Oct 2023 17:53:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[main]: acpi: Add PPTT support
by David Milosevic (Code Review) 30 Oct '23

30 Oct '23

Attention is currently required from: Arthur Heymans, Cliff Huang, Lance Zhao, Maximilian Brune, Patrick Rudolph, Tim Wawrzynczak. Hello Arthur Heymans, Cliff Huang, Lance Zhao, Maximilian Brune, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78071?usp=email to look at the new patch set (#8). Change subject: acpi: Add PPTT support ...................................................................... acpi: Add PPTT support This patch adds code to generate Processor Properties Topology Tables (PPTT) compliant to the ACPI 6.4 specification. - The 'acpi_get_pptt_topology' hook is mandatory once ACPI_PPTT is selected. Its purpose is to return a pointer to a topology tree, which describes the relationship between CPUs and caches. The hook can be provided by, for example, mainboard code. - The optional hook 'acpi_cleanup_pptt_topology' can be implemented to cleanup remainders of 'acpi_get_pptt_topology'. For example, one might use dynamic memory allocations in order to setup the topology tree. The hook can then be used to free that memory. Background: We are currently working on a mainboard which requires a valid PPTT table. Patch was tested for that mainboard. Change-Id: Ia119e1ba15756704668116bdbc655190ec94ff10 Signed-off-by: David Milosevic <David.Milosevic(a)9elements.com> --- M src/acpi/Kconfig M src/acpi/Makefile.inc M src/acpi/acpi.c A src/acpi/acpi_pptt.c M src/include/acpi/acpi.h 5 files changed, 287 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/78071/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/78071?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia119e1ba15756704668116bdbc655190ec94ff10 Gerrit-Change-Number: 78071 Gerrit-PatchSet: 8 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: soc/intel/cse: Add API to check if CSE Firmware update is required
by Subrata Banik (Code Review) 30 Oct '23

30 Oct '23

Attention is currently required from: Anil Kumar K, Jérémy Compostella, Krishna P Bhat D, Paul Menzel. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78243?usp=email ) Change subject: soc/intel/cse: Add API to check if CSE Firmware update is required ...................................................................... Patch Set 14: (1 comment) Patchset: PS14: can you please capture the boot time w/o and w/ this CL. specifically at the caller of this function? -- To view, visit https://review.coreboot.org/c/coreboot/+/78243?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If5fae95786d28d586566881bc4436812754636ae Gerrit-Change-Number: 78243 Gerrit-PatchSet: 14 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Mon, 30 Oct 2023 17:52:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[main]: acpi: Add PPTT support
by David Milosevic (Code Review) 30 Oct '23

30 Oct '23

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[L] Change in coreboot[main]: acpi: Add PPTT support
by David Milosevic (Code Review) 30 Oct '23

30 Oct '23

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[M] Change in coreboot[main]: soc/intel/cannonlake: Implement SoC sleep state array
by Martin L Roth (Code Review) 30 Oct '23

30 Oct '23

Attention is currently required from: Matt DeVillier, Nick Vaccaro, Subrata Banik. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78522?usp=email ) Change subject: soc/intel/cannonlake: Implement SoC sleep state array ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78522?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib2c733c04e29f0f9e7e2e6dbf36c2a7618fdc23f Gerrit-Change-Number: 78522 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 30 Oct 2023 17:45:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/tigerlake: Implement SoC sleep state array
by Martin L Roth (Code Review) 30 Oct '23

30 Oct '23

Attention is currently required from: Matt DeVillier, Nick Vaccaro, Paul Menzel, Subrata Banik. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78521?usp=email ) Change subject: soc/intel/tigerlake: Implement SoC sleep state array ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78521?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I34999891ea0d386328698109b6315d481de7c43a Gerrit-Change-Number: 78521 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 30 Oct 2023 17:44:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/hatch: Change WiFi device type from PCI to generic
by Martin L Roth (Code Review) 30 Oct '23

30 Oct '23

Attention is currently required from: Matt DeVillier, Nick Vaccaro, Subrata Banik. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78543?usp=email ) Change subject: mb/google/hatch: Change WiFi device type from PCI to generic ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78543?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieab0722a81f0952bb5b6df8e60c4d684ff455418 Gerrit-Change-Number: 78543 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 30 Oct 2023 17:43:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[main]: acpi: Add PPTT support
by David Milosevic (Code Review) 30 Oct '23

30 Oct '23

Attention is currently required from: Arthur Heymans, Cliff Huang, Lance Zhao, Maximilian Brune, Patrick Rudolph, Tim Wawrzynczak. David Milosevic has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78071?usp=email ) Change subject: acpi: Add PPTT support ...................................................................... Patch Set 7: (6 comments) File src/acpi/acpi_pptt.c: https://review.coreboot.org/c/coreboot/+/78071/comment/a7aa4bad_560cc43d : PS6, Line 6: #define node_to_idx(n, pptt_start) ((uintptr_t)(n) - (uintptr_t)(pptt_start)) : #define idx_to_cpu(i, pptt_start) ((acpi_pptt_cpu_node_t *)((uint32_t)(i) + (uintptr_t)(pptt_start))) : > These macros are unreadable and require you to read the ACPI spec to read the code. […] Done https://review.coreboot.org/c/coreboot/+/78071/comment/b4deed27_09afb0cd : PS6, Line 9: static u32 unique_cache_id = 1; > Why global and not inside the function? Done https://review.coreboot.org/c/coreboot/+/78071/comment/7e9b0ed8_570da563 : PS6, Line 66: > drop newline Is that really necessary? I mean, Jenkins does not complain and it really is only a matter of preference. https://review.coreboot.org/c/coreboot/+/78071/comment/48ccaf9a_c41f2f5a : PS6, Line 74: static void pptt_cpu_push_resource(const u32 cpu_idx, const u32 where, const u32 resource_idx, const acpi_pptt_t *pptt) : { : acpi_pptt_cpu_node_t *cpu_node = idx_to_cpu(cpu_idx, pptt); : : if (where < cpu_node->n_resources) : cpu_node->resources[where] = resource_idx; > Inline this function and get rid of the if check. It should never not hit. […] Done https://review.coreboot.org/c/coreboot/+/78071/comment/51cc006d_14bf5ac4 : PS6, Line 102: root > That's a poor name. There should be only one root. […] It is the root of a (sub)-tree. How does renaming it to "entry" fixes this? Should not there be only one "entry"? https://review.coreboot.org/c/coreboot/+/78071/comment/b0f17cbc_a3b904d9 : PS6, Line 113: for (struct pptt_cpu_resources *it = root->resources; it != NULL; it = it->next) : pptt_cpu_push_resource(cpu_idx, r_idx++, new_pptt_cache(current, it->cache, pptt), pptt); > This has the same loop as count_resources. […] The position (current) of the new cache entry (new_pptt_cache) depends on the number of resources we have, so the first time I am iterating to determine the size to alloc for the CPU node. Then in the second loop, I generate the cache nodes. -- To view, visit https://review.coreboot.org/c/coreboot/+/78071?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia119e1ba15756704668116bdbc655190ec94ff10 Gerrit-Change-Number: 78071 Gerrit-PatchSet: 7 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 30 Oct 2023 17:32:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/cmn/gfx: Fix GFX modeset issue with dual-display
by Nick Vaccaro (Code Review) 30 Oct '23

30 Oct '23

Attention is currently required from: Kapil Porwal, Nick Vaccaro, Subrata Banik. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78691?usp=email ) Change subject: soc/intel/cmn/gfx: Fix GFX modeset issue with dual-display ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78691?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie2a3b9f1212a9dcab2b7305078fe22ee35e7423c Gerrit-Change-Number: 78691 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paz Zcharya <pazz(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 30 Oct 2023 17:28:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit October 2023