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Change subject: mb/gigabyte/ga-h77m-d3h: Add Sandy/Ivy Bridge board GA-H77M-D3H
......................................................................
Patch Set 6:
(1 comment)
File 3rdparty/amd_blobs:
PS6:
I guess this is not intended
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Change subject: soc/amd/common/psp: Remove unnecessary prompts from Kconfig
......................................................................
Patch Set 1: Code-Review+2
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Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78819?usp=email )
Change subject: arch/x86/memcpy: Change unrecognized instruction movsd to movsq
......................................................................
arch/x86/memcpy: Change unrecognized instruction movsd to movsq
When doing a 64-bit compile, I noticed a warning saying that movsd was
not recognized, and that movsl was being used instead. I think that's
an incorrect replacement, and that movsq should be used instead.
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Change-Id: Ib3f55f50da74a9c24d2fdd0fa45bd0019b2fdc0a
---
M src/arch/x86/memcpy.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/78819/1
diff --git a/src/arch/x86/memcpy.c b/src/arch/x86/memcpy.c
index 93002cd..478f610 100644
--- a/src/arch/x86/memcpy.c
+++ b/src/arch/x86/memcpy.c
@@ -16,7 +16,7 @@
asm volatile(
#if ENV_X86_64
- "rep ; movsd\n\t"
+ "rep ; movsq\n\t"
"mov %4,%%rcx\n\t"
#else
"rep ; movsl\n\t"
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Change subject: soc/amd/common/psp: Remove unnecessary prompts from Kconfig
......................................................................
soc/amd/common/psp: Remove unnecessary prompts from Kconfig
I think this was probably a cut & paste error. We don't want prompts
for the "default" Kconfig options. Those should be set by the platform,
not the end user. These prompts didn't make sense where they were in the
Kconfig menus either.
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Change-Id: Idcd2ba84591d31a9a25bcc6cae3ec163939d7836
---
M src/soc/amd/common/block/psp/Kconfig
1 file changed, 7 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/78818/1
diff --git a/src/soc/amd/common/block/psp/Kconfig b/src/soc/amd/common/block/psp/Kconfig
index d86ad7c..47e3fc4 100644
--- a/src/soc/amd/common/block/psp/Kconfig
+++ b/src/soc/amd/common/block/psp/Kconfig
@@ -94,25 +94,25 @@
Select this config to indicate SoC includes Hardware Security Processor(HSP).
config AMD_FWM_POSITION_20000_DEFAULT
- bool "0x20000"
+ bool
config AMD_FWM_POSITION_420000_DEFAULT
- bool "0x420000"
+ bool
config AMD_FWM_POSITION_820000_DEFAULT
- bool "0x820000"
+ bool
config AMD_FWM_POSITION_C20000_DEFAULT
- bool "0xC20000"
+ bool
config AMD_FWM_POSITION_E20000_DEFAULT
- bool "0xE20000"
+ bool
config AMD_FWM_POSITION_F20000_DEFAULT
- bool "0xF20000"
+ bool
config AMD_FWM_POSITION_FA0000_DEFAULT
- bool "0xFA0000"
+ bool
choice AMD_FWM_POSITION_CHOICE
prompt "AMD FW position"
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#6).
The following approvals got outdated and were removed:
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Change subject: mb/gigabyte/ga-h77m-d3h: Add Sandy/Ivy Bridge board GA-H77M-D3H
......................................................................
mb/gigabyte/ga-h77m-d3h: Add Sandy/Ivy Bridge board GA-H77M-D3H
This board is based off ga-b75m-d3h, which uses the same SuperIO chip.
It doesn't have the ASMedia SATA3 controller, the H77 chipset comes with
2 SATA3 ports next to the 4 SATA2 ports.
Flashing notes:
These boards come with dual-BIOS feature. This is set of two
unremovable what appears to be identical chips marked M_BIOS and
B_BIOS. Flash the B_BIOS chip, and boot the system. Ensure you have
a payload and setup ready to boot a Linux system with iomem=relaxed or
similar. Immediately use flashrom -p internal to flash the same
firmware again. If you skip this step your next boot will show weird
exception traces in either coreboot or your payload. Flashing from
there via the chip is very difficult (you have to try many times in
order to get a booting run), which can all be remedied by doing a
flash from internal. I suppose the dual-BIOS feature is somewhat in
the way here.
Tested with:
- CPU Core i7-3770S
- RAM single bank 4GB CL11, two banks 4+4GB CL11
- OS Gentoo Linux LiveUSB, KDE desktop (Linux 5.15.72)
Working:
- GRUB2 payload
- Intel ME stripped
- Integrated graphics with libgfxinit
- (boot from) SATA2, SATA3 ports
- Rear and mainboard connector USB ports, supporting boot
- Atheros GbE NIC
- 2.0 channel audio via lineout jack output
- ACPI (power button triggers OS events)
- S3 suspend/resume
Signed-off-by: Fabian Groffen <grobian(a)gentoo.org>
Change-Id: Icb3e74326a0a7aaf770d1917a2a0931feadd7eab
---
M 3rdparty/amd_blobs
A src/mainboard/gigabyte/ga-h77m-d3h/Kconfig
A src/mainboard/gigabyte/ga-h77m-d3h/Kconfig.name
A src/mainboard/gigabyte/ga-h77m-d3h/Makefile.inc
A src/mainboard/gigabyte/ga-h77m-d3h/acpi/ec.asl
A src/mainboard/gigabyte/ga-h77m-d3h/acpi/mainboard.asl
A src/mainboard/gigabyte/ga-h77m-d3h/acpi/pci.asl
A src/mainboard/gigabyte/ga-h77m-d3h/acpi/platform.asl
A src/mainboard/gigabyte/ga-h77m-d3h/acpi/superio.asl
A src/mainboard/gigabyte/ga-h77m-d3h/acpi/thermal.asl
A src/mainboard/gigabyte/ga-h77m-d3h/acpi_tables.c
A src/mainboard/gigabyte/ga-h77m-d3h/board_info.txt
A src/mainboard/gigabyte/ga-h77m-d3h/cmos.default
A src/mainboard/gigabyte/ga-h77m-d3h/cmos.layout
A src/mainboard/gigabyte/ga-h77m-d3h/data.vbt
A src/mainboard/gigabyte/ga-h77m-d3h/devicetree.cb
A src/mainboard/gigabyte/ga-h77m-d3h/dsdt.asl
A src/mainboard/gigabyte/ga-h77m-d3h/early_init.c
A src/mainboard/gigabyte/ga-h77m-d3h/gma-mainboard.ads
A src/mainboard/gigabyte/ga-h77m-d3h/gpio.c
A src/mainboard/gigabyte/ga-h77m-d3h/hda_verb.c
A src/mainboard/gigabyte/ga-h77m-d3h/thermal.h
22 files changed, 682 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/77046/6
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Change subject: payloads/edk2: Remove the warning about edk2/master not working
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
Is this just the commit that happened to be tested? This is just printed for debugging, I can't really see how it would break the boot (unless there's an invalid MTRR number requested, and the CPU misbehaves. Maybe AMD implements MTRRs differently). Besides, it's inside DEBUG_CODE_BEGIN() and DEBUG_CODE_END(), so (per upstream's UefiPayloadPkg.dsc) the preprocessor strips it out for the 'CBMEM console + RELEASE' build.
Aside, we should probably stop changing behaviour between DEBUG/RELEASE, it creates so much confusion about how "this ASSERT is only breaking/a problem for DEBUG builds"
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