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Change subject: soc/intel/xeon_sp/Kconfig: select configs for skx/cpx
......................................................................
Patch Set 1:
(2 comments)
File src/soc/intel/xeon_sp/Kconfig:
https://review.coreboot.org/c/coreboot/+/71140/comment/08ecea12_73fdf630
PS1, Line 13: PLATFORM_USES_FSP2_0
this is also duplicated
https://review.coreboot.org/c/coreboot/+/71140/comment/571a76fc_88e6bccc
PS1, Line 24: PLATFORM_USES_FSP2_2
this is also duplicated
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Change subject: soc/intel/xeon_sp/Kconfig: select configs for skx/cpx
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/xeon_sp/Kconfig:
https://review.coreboot.org/c/coreboot/+/71140/comment/d60856f4_d72b4b4c
PS1, Line 26: CPU_INTEL_COMMON_SMM
this is already selected here src/cpu/intel/common/Kconfig:
config CPU_INTEL_COMMON_SMM
bool
default y if CPU_INTEL_COMMON
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Change subject: soc/intel/xeon_sp/Kconfig: select configs for skx/cpx
......................................................................
Patch Set 1:
(2 comments)
File src/soc/intel/xeon_sp/Kconfig:
https://review.coreboot.org/c/coreboot/+/71140/comment/289782d1_d81eb4db
PS1, Line 28: HAVE_SMI_HANDLER
line #46
https://review.coreboot.org/c/coreboot/+/71140/comment/26872797_c3f1de25
PS1, Line 29: NO_FSP_TEMP_RAM_EXIT
line #49
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Change subject: soc/intel/xeon_sp/Kconfig: select configs for skx/cpx
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/xeon_sp/Kconfig:
https://review.coreboot.org/c/coreboot/+/71140/comment/b14f70cd_ca15d45e
PS1, Line 27: SOC_INTEL_COMMON_BLOCK_SMM
see line #62
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Change subject: soc/intel/xeon_sp/Kconfig: select configs for skx/cpx
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Patch Set 1: Code-Review+2
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Change subject: soc/intel/xeon_sp: lock MSR_PPIN_CTL at BS_PAYLOAD_LOAD
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Patch Set 1: Code-Review+1
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Change subject: soc/intel/xeon_sp: select SCO_INTEL_COMMON_BLOCK_TCO
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Patch Set 1: Code-Review+2
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Change subject: soc/intel/xeon_sp: Improve final MTRR solution
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Patch Set 3: Code-Review+2
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