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Change subject: mb/google/brya/var/gladios: Add ACPI DmaProperty for RTL8168 ethernet
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/71699/comment/629ff79d_b5782e2f
PS1, Line 7: mb/google/brya/var/gladios: Add ACPI DmaProperty for gladios
> Add ACPI DmaProperty for RTL8168 ethernet
Done
https://review.coreboot.org/c/coreboot/+/71699/comment/1837d43d_4d2abf27
PS1, Line 12: TEST=emerge-brask coreboot.
> please also check SSDT
Done
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Hello Kevin Chiu, Tarun Tuli,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/71699
to look at the new patch set (#3).
Change subject: mb/google/brya/var/gladios: Add ACPI DmaProperty for RTL8168 ethernet
......................................................................
mb/google/brya/var/gladios: Add ACPI DmaProperty for RTL8168 ethernet
Add ACPI DmaProperty for gladios.
BUG=b:239513596
TEST=Verified SSDT on gladios unit.
Before:
Scope (\_SB.PCI0.RP01)
{
Device (RLTK)
{
Name (_HID, "R8168") // _HID: Hardware ID
Name (_UID, 0xD0E889DD) // _UID: Unique ID
Name (_DDN, "Realtek r8168") // _DDN: DOS Device Name
Name (_ADR, 0x00000000) // _ADR: Address
Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
{
0x07,
0x03
})
}
}
After:
Scope (\_SB.PCI0.RP01)
{
Device (RLTK)
{
Name (_HID, "R8168") // _HID: Hardware ID
Name (_UID, 0xD0E889DD) // _UID: Unique ID
Name (_DDN, "Realtek r8168") // _DDN: DOS Device Name
Name (_ADR, 0x00000000) // _ADR: Address
Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
{
0x07,
0x03
})
Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
{
ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"),
Package (0x01)
{
Package (0x02)
{
"DmaProperty",
One
}
}
})
}
}
Change-Id: I1c4f6ff7b3eda114f4f365a963c089fe584d8aee
Signed-off-by: Robert Chen <robert.chen(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/gladios/overridetree.cb
1 file changed, 62 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/71699/3
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Hello Kevin Chiu, Tarun Tuli,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/71699
to look at the new patch set (#2).
Change subject: mb/google/brya/var/gladios: Add ACPI DmaProperty for RTL8168 ethernet
......................................................................
mb/google/brya/var/gladios: Add ACPI DmaProperty for RTL8168 ethernet
Add ACPI DmaProperty for gladios.
BUG=b:239513596
TEST=Verified SSDT on gladios.
Before:
Scope (\_SB.PCI0.RP01)
{
Device (RLTK)
{
Name (_HID, "R8168") // _HID: Hardware ID
Name (_UID, 0xD0E889DD) // _UID: Unique ID
Name (_DDN, "Realtek r8168") // _DDN: DOS Device Name
Name (_ADR, 0x00000000) // _ADR: Address
Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
{
0x07,
0x03
})
}
}
After:
Scope (\_SB.PCI0.RP01)
{
Device (RLTK)
{
Name (_HID, "R8168") // _HID: Hardware ID
Name (_UID, 0xD0E889DD) // _UID: Unique ID
Name (_DDN, "Realtek r8168") // _DDN: DOS Device Name
Name (_ADR, 0x00000000) // _ADR: Address
Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
{
0x07,
0x03
})
Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
{
ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"),
Package (0x01)
{
Package (0x02)
{
"DmaProperty",
One
}
}
})
}
}
Change-Id: I1c4f6ff7b3eda114f4f365a963c089fe584d8aee
Signed-off-by: Robert Chen <robert.chen(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/gladios/overridetree.cb
1 file changed, 62 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/71699/2
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Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71628 )
Change subject: mb/google/brya/var/kano: Set the ov2740 to 0 and the hi556 to 1 for SSFC
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/brya/variants/kano/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/71628/comment/b781b62f_70778936
PS1, Line 20: option UFC_MIPI_OVTI2740 0
> You can use ec command (ectool cbi get 8) to get the SSFC data to know whether or not to use SSFC. […]
I still don't understand why UFC_MIPI_HI556 can't just be value 3 in the UFC field, and why the SSFC fields can't just be used to extend the UFC field if more bits are needed. It seems very odd that we'd need a completely new field here, with one of the options being the same as one of the options in the existing field.
I'm not objecting - but it seems strange that this is needed at all.
I think that being able to extend the existing fields using the SSFC is kind of the point of SSFC returning 0 instead of an error when it's not initialized.
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Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71592 )
Change subject: vc/google: Add and use POST_CODE_CLEAR definition
......................................................................
vc/google: Add and use POST_CODE_CLEAR definition
The CR50 code clears the post code value. Add this as a #define.
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Change-Id: If3b73a3159ac8ac9ab08c6ff705b0ca289ab453c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71592
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy(a)google.com>
Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
---
M src/commonlib/include/commonlib/console/post_codes.h
M src/vendorcode/google/chromeos/cr50_enable_update.c
2 files changed, 24 insertions(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Jon Murphy: Looks good to me, approved
Eric Lai: Looks good to me, approved
diff --git a/src/commonlib/include/commonlib/console/post_codes.h b/src/commonlib/include/commonlib/console/post_codes.h
index d838815..ef296bd 100644
--- a/src/commonlib/include/commonlib/console/post_codes.h
+++ b/src/commonlib/include/commonlib/console/post_codes.h
@@ -28,6 +28,12 @@
#define POST_CODES_H
/**
+ * \brief Not an actual post-code - used to clear port80h
+ *
+ */
+#define POST_CODE_CLEAR 0x00
+
+/**
* \brief Entry into 'crt0.s'. reset code jumps to here
*
* First instruction that gets executed after the reset vector jumps.
diff --git a/src/vendorcode/google/chromeos/cr50_enable_update.c b/src/vendorcode/google/chromeos/cr50_enable_update.c
index 9ac33a5..6beea91 100644
--- a/src/vendorcode/google/chromeos/cr50_enable_update.c
+++ b/src/vendorcode/google/chromeos/cr50_enable_update.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootstate.h>
+#include <commonlib/console/post_codes.h>
#include <console/console.h>
#include <ec/google/chromeec/ec.h>
#include <elog.h>
@@ -133,7 +134,7 @@
mainboard_prepare_cr50_reset();
/* clear current post code avoid chatty eventlog on subsequent boot*/
- post_code(0);
+ post_code(POST_CODE_CLEAR);
/*
* Older Cr50 firmware doesn't support the timeout parameter for the
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Change subject: mb/google/brya/var/gladios: Add ACPI DmaProperty for gladios
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/71699/comment/57e47deb_0e338f2d
PS1, Line 7: mb/google/brya/var/gladios: Add ACPI DmaProperty for gladios
Add ACPI DmaProperty for RTL8168 ethernet
https://review.coreboot.org/c/coreboot/+/71699/comment/e080e92f_8b8c0255
PS1, Line 12: TEST=emerge-brask coreboot.
please also check SSDT
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Change subject: mb/google/brya/var/gladios: Update RTL8168 LAN LED config
......................................................................
Patch Set 6: Code-Review+2
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