coreboot-gerrit January 2023

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[M] Change in coreboot[master]: Kconfig: Add option to compress ramstage with LZ4
by Martin L Roth (Code Review) 08 Jan '23

08 Jan '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71673 ) Change subject: Kconfig: Add option to compress ramstage with LZ4 ...................................................................... Kconfig: Add option to compress ramstage with LZ4 When ramstage is loaded asynchronously, as on the skyrim boards, the faster decompression of LZ4 allows for faster boot times than the tighter compression of LZMA. To make this change, the name of the existing ramstage_compression option needs to be updated. BUG=b:264409477 TEST=Boot skyrim, look at boot speed Signed-off-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Change-Id: I27dd1a8def024e0efd466cef9ffd9ca71717486a Reviewed-on: https://review.coreboot.org/c/coreboot/+/71673 Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M Makefile.inc M src/Kconfig M src/lib/Makefile.inc M src/lib/cbfs.c 4 files changed, 59 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Fred Reitberger: Looks good to me, approved diff --git a/Makefile.inc b/Makefile.inc index 5cd13ba..2b5d742 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -372,9 +372,12 @@ ####################################################################### # a variety of flags for our build CBFS_COMPRESS_FLAG:=none -ifeq ($(CONFIG_COMPRESS_RAMSTAGE),y) +ifeq ($(CONFIG_COMPRESS_RAMSTAGE_LZMA),y) CBFS_COMPRESS_FLAG:=LZMA endif +ifeq ($(CONFIG_COMPRESS_RAMSTAGE_LZ4),y) +CBFS_COMPRESS_FLAG:=LZ4 +endif CBFS_PAYLOAD_COMPRESS_FLAG:=none ifeq ($(CONFIG_COMPRESSED_PAYLOAD_LZMA),y) diff --git a/src/Kconfig b/src/Kconfig index f68553c..8246a17 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -170,12 +170,36 @@ every boot. Use this if you want the NVRAM configuration to never be modified from its default values. -config COMPRESS_RAMSTAGE - bool "Compress ramstage with LZMA" - depends on HAVE_RAMSTAGE - # Default value set at the end of the file +config MB_COMPRESS_RAMSTAGE_LZ4 + bool help - Compress ramstage to save memory in the flash image. + Select this in a mainboard to use LZ4 compression by default + +choice + prompt "Ramstage compression" + depends on HAVE_RAMSTAGE && !UNCOMPRESSED_RAMSTAGE + default COMPRESS_RAMSTAGE_LZ4 if MB_COMPRESS_RAMSTAGE_LZ4 + default COMPRESS_RAMSTAGE_LZMA + +config COMPRESS_RAMSTAGE_LZMA + bool "Compress ramstage with LZMA" + help + Compress ramstage with LZMA to save memory in the flash image. + +config COMPRESS_RAMSTAGE_LZ4 + bool "Compress ramstage with LZ4" + help + LZ4 doesn't give as good compression as LZMA, but decompresses much + faster. For large binaries such as ramstage, it's typically best to + use LZMA, but there can be cases where the faster decompression of + LZ4 can lead to a faster boot time. Testing on each individual board + is typically going to be needed due to the large number of factors + that can influence the decision. Binary size, CPU speed, ROM read + speed, cache, and other factors all play a part. + + If you're not sure, stick with LZMA. + +endchoice config COMPRESS_PRERAM_STAGES bool "Compress romstage and verstage with LZ4" @@ -1379,9 +1403,6 @@ # Set default values for symbols created before mainboards. This allows the # option to be displayed in the general menu, but the default to be loaded in # the mainboard if desired. -config COMPRESS_RAMSTAGE - default y if !UNCOMPRESSED_RAMSTAGE - config COMPRESS_PRERAM_STAGES depends on (HAVE_ROMSTAGE || HAVE_VERSTAGE) && NO_XIP_EARLY_STAGES default y diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index dcba0c6..030959c 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -95,7 +95,7 @@ romstage-y += fmap.c romstage-y += delay.c romstage-y += cbfs.c -romstage-$(CONFIG_COMPRESS_RAMSTAGE) += lzma.c lzmadecode.c +romstage-$(CONFIG_COMPRESS_RAMSTAGE_LZMA) += lzma.c lzmadecode.c romstage-y += libgcc.c romstage-y += memrange.c romstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c @@ -294,7 +294,7 @@ postcar-y += gcc.c postcar-y += halt.c postcar-y += libgcc.c -postcar-$(CONFIG_COMPRESS_RAMSTAGE) += lzma.c lzmadecode.c +postcar-$(CONFIG_COMPRESS_RAMSTAGE_LZMA) += lzma.c lzmadecode.c postcar-y += memchr.c postcar-y += memcmp.c postcar-y += prog_loaders.c diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index d2829d1..0b2d66b 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -142,7 +142,7 @@ return false; if (ENV_ROMSTAGE && CONFIG(POSTCAR_STAGE)) return false; - if ((ENV_ROMSTAGE || ENV_POSTCAR) && !CONFIG(COMPRESS_RAMSTAGE)) + if ((ENV_ROMSTAGE || ENV_POSTCAR) && !CONFIG(COMPRESS_RAMSTAGE_LZMA)) return false; if (ENV_SMM) return false; -- To view, visit https://review.coreboot.org/c/coreboot/+/71673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27dd1a8def024e0efd466cef9ffd9ca71717486a Gerrit-Change-Number: 71673 Gerrit-PatchSet: 5 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/dedede: Create dibbi variant
by Martin L Roth (Code Review) 08 Jan '23

08 Jan '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71709 ) Change subject: mb/google/dedede: Create dibbi variant ...................................................................... mb/google/dedede: Create dibbi variant Create the dibbi variant of the waddledee reference board by copying the template files to a new directory. BUG=b:260934018 BRANCH=dedede TEST=util/abuild/abuild -p none -t google/dedede -x -a includes GOOGLE_DIBBI Change-Id: I3b8d4e7f8a53323f56567cbbc03bab7f8804f286 Signed-off-by: Liam Flaherty <liamflaherty(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71709 Reviewed-by: Adam Mills <adamjmills(a)google.com> Reviewed-by: Sam McNally <sammc(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/Kconfig.name A src/mainboard/google/dedede/variants/dibbi/include/variant/ec.h A src/mainboard/google/dedede/variants/dibbi/include/variant/gpio.h A src/mainboard/google/dedede/variants/dibbi/memory/Makefile.inc A src/mainboard/google/dedede/variants/dibbi/memory/dram_id.generated.txt A src/mainboard/google/dedede/variants/dibbi/memory/mem_parts_used.txt A src/mainboard/google/dedede/variants/dibbi/overridetree.cb 8 files changed, 103 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Sam McNally: Looks good to me, approved Adam Mills: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 8901da3..ca72da1 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -88,6 +88,7 @@ config MAINBOARD_PART_NUMBER default "Boten" if BOARD_GOOGLE_BOTEN + default "Dibbi" if BOARD_GOOGLE_DIBBI default "Dedede" if BOARD_GOOGLE_DEDEDE default "Drawcia" if BOARD_GOOGLE_DRAWCIA default "Madoo" if BOARD_GOOGLE_MADOO @@ -127,6 +128,7 @@ config VARIANT_DIR default "boten" if BOARD_GOOGLE_BOTEN + default "dibbi" if BOARD_GOOGLE_DIBBI default "dedede" if BOARD_GOOGLE_DEDEDE default "drawcia" if BOARD_GOOGLE_DRAWCIA default "madoo" if BOARD_GOOGLE_MADOO diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 4f2fa04..eeed1aa 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -8,6 +8,10 @@ select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR +config BOARD_GOOGLE_DIBBI + bool "-> Dibbi" + select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 + config BOARD_GOOGLE_DEDEDE bool "-> Dedede" select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 diff --git a/src/mainboard/google/dedede/variants/dibbi/include/variant/ec.h b/src/mainboard/google/dedede/variants/dibbi/include/variant/ec.h new file mode 100644 index 0000000..08870e0 --- /dev/null +++ b/src/mainboard/google/dedede/variants/dibbi/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/dedede/variants/dibbi/include/variant/gpio.h b/src/mainboard/google/dedede/variants/dibbi/include/variant/gpio.h new file mode 100644 index 0000000..9078664 --- /dev/null +++ b/src/mainboard/google/dedede/variants/dibbi/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/dedede/variants/dibbi/memory/Makefile.inc b/src/mainboard/google/dedede/variants/dibbi/memory/Makefile.inc new file mode 100644 index 0000000..eace2e4 --- /dev/null +++ b/src/mainboard/google/dedede/variants/dibbi/memory/Makefile.inc @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder diff --git a/src/mainboard/google/dedede/variants/dibbi/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/dibbi/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/dedede/variants/dibbi/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/dedede/variants/dibbi/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/dibbi/memory/mem_parts_used.txt new file mode 100644 index 0000000..9621137 --- /dev/null +++ b/src/mainboard/google/dedede/variants/dibbi/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/dedede/variants/dibbi/overridetree.cb b/src/mainboard/google/dedede/variants/dibbi/overridetree.cb new file mode 100644 index 0000000..404024b --- /dev/null +++ b/src/mainboard/google/dedede/variants/dibbi/overridetree.cb @@ -0,0 +1,42 @@ +chip soc/intel/jasperlake + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Trackpad | + #| I2C1 | Digitizer | + #| I2C2 | Touchscreen | + #| I2C3 | Camera | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + }" + + device domain 0 on + device pci 15.0 on end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/71709 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b8d4e7f8a53323f56567cbbc03bab7f8804f286 Gerrit-Change-Number: 71709 Gerrit-PatchSet: 3 Gerrit-Owner: Liam Flaherty <liamflaherty(a)chromium.org> Gerrit-Reviewer: Adam Mills <adamjmills(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/skyrim/var/markarth: Update RAM ID table
by Martin L Roth (Code Review) 08 Jan '23

08 Jan '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71619 ) Change subject: mb/google/skyrim/var/markarth: Update RAM ID table ...................................................................... mb/google/skyrim/var/markarth: Update RAM ID table Add new ram_id:0000 for Micron MT62F1G32D2DS-026 WT:B. Add new ram_id:0010 for Micron MT62F512M32D2DR-031 WT:B The RAM ID table has been assigned as: DRAM Part Name ID to assign K3KL8L80CM-MGCT 0 (0000) H58G56BK7BX068 0 (0000) MT62F1G32D2DS-026 WT:B 0 (0000) K3KL9L90CM-MGCT 1 (0001) H58G66BK7BX067 1 (0001) MT62F2G32D4DS-026 WT:B 1 (0001) MT62F512M32D2DR-031 WT:B 2 (0010) BUG=b:263296326, b:263216451 BRANCH=None TEST=FW_NAME=markarth emerge-skyrim coreboot Change-Id: I3a0d3edb813ef91bfdc68f7400be64fb679dfc04 Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71619 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> --- M src/mainboard/google/skyrim/variants/markarth/memory/Makefile.inc M src/mainboard/google/skyrim/variants/markarth/memory/dram_id.generated.txt M src/mainboard/google/skyrim/variants/markarth/memory/mem_parts_used.txt 3 files changed, 37 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Dtrain Hsu: Looks good to me, approved Ian Feng: Looks good to me, approved diff --git a/src/mainboard/google/skyrim/variants/markarth/memory/Makefile.inc b/src/mainboard/google/skyrim/variants/markarth/memory/Makefile.inc index 258a35b..6d0f0d0 100644 --- a/src/mainboard/google/skyrim/variants/markarth/memory/Makefile.inc +++ b/src/mainboard/google/skyrim/variants/markarth/memory/Makefile.inc @@ -4,5 +4,6 @@ # ./util/spd_tools/bin/part_id_gen MDN lp5 src/mainboard/google/skyrim/variants/markarth/memory src/mainboard/google/skyrim/variants/markarth/memory/mem_parts_used.txt SPD_SOURCES = -SPD_SOURCES += spd/lp5/set-1/spd-7.hex # ID = 0(0b0000) Parts = K3KL8L80CM-MGCT, H58G56BK7BX068 +SPD_SOURCES += spd/lp5/set-1/spd-7.hex # ID = 0(0b0000) Parts = K3KL8L80CM-MGCT, H58G56BK7BX068, MT62F1G32D2DS-026 WT:B SPD_SOURCES += spd/lp5/set-1/spd-8.hex # ID = 1(0b0001) Parts = K3KL9L90CM-MGCT, H58G66BK7BX067, MT62F2G32D4DS-026 WT:B +SPD_SOURCES += spd/lp5/set-1/spd-1.hex # ID = 2(0b0010) Parts = MT62F512M32D2DR-031 WT:B diff --git a/src/mainboard/google/skyrim/variants/markarth/memory/dram_id.generated.txt b/src/mainboard/google/skyrim/variants/markarth/memory/dram_id.generated.txt index c2ca506..8e3ef0e 100644 --- a/src/mainboard/google/skyrim/variants/markarth/memory/dram_id.generated.txt +++ b/src/mainboard/google/skyrim/variants/markarth/memory/dram_id.generated.txt @@ -6,6 +6,8 @@ DRAM Part Name ID to assign K3KL8L80CM-MGCT 0 (0000) H58G56BK7BX068 0 (0000) +MT62F1G32D2DS-026 WT:B 0 (0000) K3KL9L90CM-MGCT 1 (0001) H58G66BK7BX067 1 (0001) MT62F2G32D4DS-026 WT:B 1 (0001) +MT62F512M32D2DR-031 WT:B 2 (0010) diff --git a/src/mainboard/google/skyrim/variants/markarth/memory/mem_parts_used.txt b/src/mainboard/google/skyrim/variants/markarth/memory/mem_parts_used.txt index cded20f..0b3d319 100644 --- a/src/mainboard/google/skyrim/variants/markarth/memory/mem_parts_used.txt +++ b/src/mainboard/google/skyrim/variants/markarth/memory/mem_parts_used.txt @@ -3,3 +3,5 @@ K3KL9L90CM-MGCT, H58G66BK7BX067, MT62F2G32D4DS-026 WT:B, +MT62F1G32D2DS-026 WT:B, +MT62F512M32D2DR-031 WT:B, -- To view, visit https://review.coreboot.org/c/coreboot/+/71619 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a0d3edb813ef91bfdc68f7400be64fb679dfc04 Gerrit-Change-Number: 71619 Gerrit-PatchSet: 4 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chao Gui <chaogui(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: chris wang <Chris.Wang(a)amd.com> Gerrit-CC: AlanKY Lee <alanky_lee(a)compal.corp-partner.google.com> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/nissa: Enable eNEM
by Martin L Roth (Code Review) 08 Jan '23

08 Jan '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71707 ) Change subject: mb/google/nissa: Enable eNEM ...................................................................... mb/google/nissa: Enable eNEM Enable eNEM for all nissa variants. This is mostly done to be consistent with other recent Intel platforms. It's not strictly necessary since on nissa the LLC size is larger than the total code + data size used in CAR. There is no change in boot time. BUG=None TEST=Boot to OS on craask Change-Id: Iad48976e405403ab61c71d8f72e0616ea8b85ebd Signed-off-by: Reka Norman <rekanorman(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71707 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kangheui Won <khwon(a)chromium.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/brya/Kconfig 1 file changed, 23 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Kangheui Won: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index c171f85..b7a44c7 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -301,7 +301,7 @@ choice prompt "Cache as RAM (CAR) setup configuration to use" - default USE_ADL_NEM if BOARD_GOOGLE_PRIMUS4ES || BOARD_GOOGLE_GIMBLE4ES || BOARD_GOOGLE_REDRIX4ES || BOARD_GOOGLE_TAEKO4ES || BOARD_GOOGLE_ANAHERA4ES || BOARD_GOOGLE_TANIKS || BOARD_GOOGLE_NIVVIKS || BOARD_GOOGLE_NEREID || BOARD_GOOGLE_CRAASK || BOARD_GOOGLE_SKOLAS || BOARD_GOOGLE_SKOLAS4ES || BOARD_GOOGLE_JOXER || BOARD_GOOGLE_PUJJO || BOARD_GOOGLE_XIVU || BOARD_GOOGLE_YAVIKS || BOARD_GOOGLE_ZYDRON + default USE_ADL_NEM if BOARD_GOOGLE_PRIMUS4ES || BOARD_GOOGLE_GIMBLE4ES || BOARD_GOOGLE_REDRIX4ES || BOARD_GOOGLE_TAEKO4ES || BOARD_GOOGLE_ANAHERA4ES || BOARD_GOOGLE_TANIKS || BOARD_GOOGLE_SKOLAS || BOARD_GOOGLE_SKOLAS4ES || BOARD_GOOGLE_ZYDRON default USE_ADL_ENEM config USE_ADL_ENEM -- To view, visit https://review.coreboot.org/c/coreboot/+/71707 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad48976e405403ab61c71d8f72e0616ea8b85ebd Gerrit-Change-Number: 71707 Gerrit-PatchSet: 2 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/nissa: Enable eNEM
by Martin L Roth (Code Review) 08 Jan '23

08 Jan '23

Attention is currently required from: Tarun Tuli, Reka Norman. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71707 ) Change subject: mb/google/nissa: Enable eNEM ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/brya/Kconfig: https://review.coreboot.org/c/coreboot/+/71707/comment/e35669d3_61a47a7a PS1, Line 302: if BOARD_GOOGLE_PRIMUS4ES || BOARD_GOOGLE_GIMBLE4ES || BOARD_GOOGLE_REDRIX4ES || BOARD_GOOGLE_TAEKO4ES || BOARD_GOOGLE_ANAHERA4ES || BOARD_GOOGLE_TANIKS || BOARD_GOOGLE_SKOLAS || BOARD_GOOGLE_SKOLAS4ES || BOARD_GOOGLE_ZYDRON Could we maybe make a different config option "DEFALT_ADL_NEM" that is selected by these boards instead of just having a giant list of boards here? -- To view, visit https://review.coreboot.org/c/coreboot/+/71707 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad48976e405403ab61c71d8f72e0616ea8b85ebd Gerrit-Change-Number: 71707 Gerrit-PatchSet: 1 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Comment-Date: Sun, 08 Jan 2023 01:16:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/nissa/var/craask: remove SAR UNUSED fw_config
by Martin L Roth (Code Review) 08 Jan '23

08 Jan '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71690 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/nissa/var/craask: remove SAR UNUSED fw_config ...................................................................... mb/google/nissa/var/craask: remove SAR UNUSED fw_config This bit is dropped in factory. All skus can use table ID_0. BUG=b:251287101 TEST=build passed. Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Change-Id: I4298376899f881dd2265aef5a0bbc5bcc46728a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71690 Reviewed-by: Reka Norman <rekanorman(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/craask/overridetree.cb 1 file changed, 18 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Reka Norman: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/craask/overridetree.cb b/src/mainboard/google/brya/variants/craask/overridetree.cb index 19cf876..a0d709f 100644 --- a/src/mainboard/google/brya/variants/craask/overridetree.cb +++ b/src/mainboard/google/brya/variants/craask/overridetree.cb @@ -22,7 +22,6 @@ end field WIFI_SAR_ID 13 15 option ID_0 0 - option UNUSED 7 end field CODEC 32 33 option CODEC_ALC5682I_VS 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/71690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4298376899f881dd2265aef5a0bbc5bcc46728a1 Gerrit-Change-Number: 71690 Gerrit-PatchSet: 3 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/nissa/var/craask: remove SAR UNUSED fw_config
by Martin L Roth (Code Review) 08 Jan '23

08 Jan '23

Attention is currently required from: Tarun Tuli, Kangheui Won, Eric Lai. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71690 ) Change subject: mb/google/nissa/var/craask: remove SAR UNUSED fw_config ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/brya/variants/craask/overridetree.cb: https://review.coreboot.org/c/coreboot/+/71690/comment/c59a8a94_e25b3b01 PS2, Line 23: field WIFI_SAR_ID 13 15 : option ID_0 0 : end So get rid of the option and just hardcode it to option ID_0? The stuff that's going on with these fields makes no sense to me. Yeah, value 7 wasn't used, because you can't get a 7 with just 2 bits. Why was that even added? -- To view, visit https://review.coreboot.org/c/coreboot/+/71690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4298376899f881dd2265aef5a0bbc5bcc46728a1 Gerrit-Change-Number: 71690 Gerrit-PatchSet: 2 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Sun, 08 Jan 2023 01:14:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/var/kano: Set the ov2740 to 0 and the hi556 to 1 for SSFC
by Martin L Roth (Code Review) 08 Jan '23

08 Jan '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71628 ) Change subject: mb/google/brya/var/kano: Set the ov2740 to 0 and the hi556 to 1 for SSFC ...................................................................... mb/google/brya/var/kano: Set the ov2740 to 0 and the hi556 to 1 for SSFC When EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG is enabled and SSFC is not set, it will treat missing SSFC as zero, so Kano needs to set the ov2740 to 0 to avoid probing wrong mipi camera. Before patch >fw_config match found: UFC=UFC_MIPI_OVTI2740 >fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S >fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S >fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S >fw_config match found: UFC=UFC_MIPI_OVTI2740 >fw_config match found: ZYDRON_UFC=UFC_MIPI_HI556 >fw_config match found: UFC=UFC_MIPI_OVTI2740 >fw_config match found: STYLUS=STYLUS_PRESENT After patch >fw_config match found: UFC=UFC_MIPI_OVTI2740 >fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S >fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S >fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S >fw_config match found: UFC=UFC_MIPI_OVTI2740 >I2C: 00:20 disabled by fw_config >fw_config match found: UFC=UFC_MIPI_OVTI2740 >fw_config match found: STYLUS=STYLUS_PRESENT BUG=b:262939431 TEST=Boot on kano and check functional with ov2740 camera. Change-Id: I46fac6c820d6006956680a07198db82225630905 Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71628 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> Reviewed-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/kano/overridetree.cb 1 file changed, 44 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Ren Kuo: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb index b45fbf7..f1fe5e7 100644 --- a/src/mainboard/google/brya/variants/kano/overridetree.cb +++ b/src/mainboard/google/brya/variants/kano/overridetree.cb @@ -17,8 +17,8 @@ option STYLUS_PRESENT 1 end field ZYDRON_UFC 36 37 - option UFC_MIPI_HI556 0 - option UFC_MIPI_OVTI2740 1 + option UFC_MIPI_OVTI2740 0 + option UFC_MIPI_HI556 1 end end chip soc/intel/alderlake -- To view, visit https://review.coreboot.org/c/coreboot/+/71628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46fac6c820d6006956680a07198db82225630905 Gerrit-Change-Number: 71628 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: security/intel/txt: Add helper function to disable TXT
by Tarun Tuli (Code Review) 07 Jan '23

07 Jan '23

Attention is currently required from: Subrata Banik, Jérémy Compostella, Paul Menzel, Sridhar Siricilla, Angel Pons, Lean Sheng Tan, Werner Zeh. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71574 ) Change subject: security/intel/txt: Add helper function to disable TXT ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71574 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27f613428e82a1dd924172eab853d2ce9c32b473 Gerrit-Change-Number: 71574 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Sat, 07 Jan 2023 18:51:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/xeon_sp/Kconfig: set up HPET_MIN_TICKS
by Jonathan Zhang (Code Review) 07 Jan '23

07 Jan '23

Attention is currently required from: Johnny Lin, Christian Walter, Arthur Heymans, Elyes Haouas, Tim Chu. Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71140 ) Change subject: soc/intel/xeon_sp/Kconfig: set up HPET_MIN_TICKS ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/xeon_sp/Kconfig: https://review.coreboot.org/c/coreboot/+/71140/comment/78e2d8f7_42289a0f PS2, Line 57: SMM_TSEG > this is duplicated (see line #46) Done -- To view, visit https://review.coreboot.org/c/coreboot/+/71140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3256c3c6a4ea331efae00d78192355a1fd78d6d2 Gerrit-Change-Number: 71140 Gerrit-PatchSet: 3 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Sat, 07 Jan 2023 18:15:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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