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[M] Change in coreboot[master]: arch/x86/smbios: Replace SMBIOS type4 processor upgrade fields values...
by Martin L Roth (Code Review) 08 Jan '23

08 Jan '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71633 ) Change subject: arch/x86/smbios: Replace SMBIOS type4 processor upgrade fields values by macros ...................................................................... arch/x86/smbios: Replace SMBIOS type4 processor upgrade fields values by macros Macro definitions are from DMTF System Management BIOS (SMBIOS) Reference Specification (DSP0134) Chapter 7.5.5. Change-Id: Ifed1d773b0b349f878648b8172fd770a397e9686 Signed-off-by: Li, Jincheng <jincheng.li(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71633 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-by: Marc Jones <marc(a)marcjonesconsulting.com> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> --- M src/arch/x86/smbios.c M src/include/smbios.h 2 files changed, 101 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Marc Jones: Looks good to me, approved Martin L Roth: Looks good to me, approved Elyes Haouas: Looks good to me, but someone else must approve diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 8d9de7c..7cdf4271b 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -401,17 +401,17 @@ static int get_socket_type(void) { if (CONFIG(CPU_INTEL_SLOT_1)) - return 0x08; + return PROCESSOR_UPGRADE_SLOT_1; if (CONFIG(CPU_INTEL_SOCKET_MPGA604)) - return 0x13; + return PROCESSOR_UPGRADE_SOCKET_MPGA604; if (CONFIG(CPU_INTEL_SOCKET_LGA775)) - return 0x15; + return PROCESSOR_UPGRADE_SOCKET_LGA775; if (CONFIG(XEON_SP_COMMON_BASE)) - return 0x36; + return PROCESSOR_UPGRADE_SOCKET_LGA3647_1; if (CONFIG(SOC_INTEL_ALDERLAKE)) - return 0x40; + return PROCESSOR_UPGRADE_SOCKET_LGA1700; - return 0x02; /* Unknown */ + return PROCESSOR_UPGRADE_UNKNOWN; } unsigned int __weak smbios_processor_external_clock(void) diff --git a/src/include/smbios.h b/src/include/smbios.h index 9217f5e..446652c 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -486,6 +486,82 @@ #define SMBIOS_PROCESSOR_STATUS_POPULATED (1 << 6) #define SMBIOS_PROCESSOR_STATUS_CPU_ENABLED (1 << 0) +/* enum for socket type */ +enum smbios_processor_upgrade_field { + PROCESSOR_UPGRADE_OTHER = 0x01, + PROCESSOR_UPGRADE_UNKNOWN = 0x02, + PROCESSOR_UPGRADE_DAUGHTER_BOARD = 0x03, + PROCESSOR_UPGRADE_ZIF_SOCKET = 0x04, + PROCESSOR_UPGRADE_REPLACEABLE_PIGGY_BACK = 0x05, + PROCESSOR_UPGRADE_NONE = 0x06, + PROCESSOR_UPGRADE_LIF_SOCKET = 0x07, + PROCESSOR_UPGRADE_SLOT_1 = 0x08, + PROCESSOR_UPGRADE_SLOT_2 = 0x09, + PROCESSOR_UPGRADE_370_PIN_SOCKET = 0x0a, + PROCESSOR_UPGRADE_SLOT_A = 0x0b, + PROCESSOR_UPGRADE_SLOT_M = 0x0c, + PROCESSOR_UPGRADE_SOCKET_423 = 0x0d, + PROCESSOR_UPGRADE_SOCKET_A = 0x0e, + PROCESSOR_UPGRADE_SOCKET_478 = 0x0f, + PROCESSOR_UPGRADE_SOCKET_754 = 0x10, + PROCESSOR_UPGRADE_SOCKET_940 = 0x11, + PROCESSOR_UPGRADE_SOCKET_939 = 0x12, + PROCESSOR_UPGRADE_SOCKET_MPGA604 = 0x13, + PROCESSOR_UPGRADE_SOCKET_LGA771 = 0x14, + PROCESSOR_UPGRADE_SOCKET_LGA775 = 0x15, + PROCESSOR_UPGRADE_SOCKET_S1 = 0x16, + PROCESSOR_UPGRADE_SOCKET_AM2 = 0x17, + PROCESSOR_UPGRADE_SOCKET_F = 0x18, + PROCESSOR_UPGRADE_SOCKET_LGA1366 = 0x19, + PROCESSOR_UPGRADE_SOCKET_G34 = 0x1a, + PROCESSOR_UPGRADE_SOCKET_AM3 = 0x1b, + PROCESSOR_UPGRADE_SOCKET_C32 = 0x1c, + PROCESSOR_UPGRADE_SOCKET_LGA1156 = 0x1d, + PROCESSOR_UPGRADE_SOCKET_LGA1567 = 0x1e, + PROCESSOR_UPGRADE_SOCKET_PGA988A = 0x1f, + PROCESSOR_UPGRADE_SOCKET_BGA1288 = 0x20, + PROCESSOR_UPGRADE_SOCKET_RPGA988B = 0x21, + PROCESSOR_UPGRADE_SOCKET_BGA1023 = 0x22, + PROCESSOR_UPGRADE_SOCKET_BGA1224 = 0x23, + PROCESSOR_UPGRADE_SOCKET_LGA1155 = 0x24, + PROCESSOR_UPGRADE_SOCKET_LGA1356 = 0x25, + PROCESSOR_UPGRADE_SOCKET_LGA2011 = 0x26, + PROCESSOR_UPGRADE_SOCKET_FS1 = 0x27, + PROCESSOR_UPGRADE_SOCKET_FS2 = 0x28, + PROCESSOR_UPGRADE_SOCKET_FM1 = 0x29, + PROCESSOR_UPGRADE_SOCKET_FM2 = 0x2a, + PROCESSOR_UPGRADE_SOCKET_LGA2011_3 = 0x2b, + PROCESSOR_UPGRADE_SOCKET_LGA1356_3 = 0x2c, + PROCESSOR_UPGRADE_SOCKET_LGA1150 = 0x2d, + PROCESSOR_UPGRADE_SOCKET_BGA1168 = 0x2e, + PROCESSOR_UPGRADE_SOCKET_BGA1234 = 0x2f, + PROCESSOR_UPGRADE_SOCKET_BGA1364 = 0x30, + PROCESSOR_UPGRADE_SOCKET_AM4 = 0x31, + PROCESSOR_UPGRADE_SOCKET_LGA1151 = 0x32, + PROCESSOR_UPGRADE_SOCKET_BGA1356 = 0x33, + PROCESSOR_UPGRADE_SOCKET_BGA1440 = 0x34, + PROCESSOR_UPGRADE_SOCKET_BGA1515 = 0x35, + PROCESSOR_UPGRADE_SOCKET_LGA3647_1 = 0x36, + PROCESSOR_UPGRADE_SOCKET_SP3 = 0x37, + PROCESSOR_UPGRADE_SOCKET_SP3R2 = 0x38, + PROCESSOR_UPGRADE_SOCKET_LGA2066 = 0x39, + PROCESSOR_UPGRADE_SOCKET_BGA1392 = 0x3a, + PROCESSOR_UPGRADE_SOCKET_BGA1510 = 0x3b, + PROCESSOR_UPGRADE_SOCKET_BGA1528 = 0x3c, + PROCESSOR_UPGRADE_SOCKET_LGA4189 = 0x3d, + PROCESSOR_UPGRADE_SOCKET_LGA1200 = 0x3e, + PROCESSOR_UPGRADE_SOCKET_LGA4677 = 0x3f, + PROCESSOR_UPGRADE_SOCKET_LGA1700 = 0x40, + PROCESSOR_UPGRADE_SOCKET_BGA1744 = 0x41, + PROCESSOR_UPGRADE_SOCKET_BGA1781 = 0x42, + PROCESSOR_UPGRADE_SOCKET_BGA1211 = 0x43, + PROCESSOR_UPGRADE_SOCKET_BGA2422 = 0x44, + PROCESSOR_UPGRADE_SOCKET_LGA1211 = 0x45, + PROCESSOR_UPGRADE_SOCKET_LGA2422 = 0x46, + PROCESSOR_UPGRADE_SOCKET_LGA5773 = 0x47, + PROCESSOR_UPGRADE_SOCKET_BGA5773 = 0x48, +}; + /* defines for processor family */ #define SMBIOS_PROCESSOR_FAMILY_OTHER 0x01 #define SMBIOS_PROCESSOR_FAMILY_UNKNOWN 0x02 -- To view, visit https://review.coreboot.org/c/coreboot/+/71633 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifed1d773b0b349f878648b8172fd770a397e9686 Gerrit-Change-Number: 71633 Gerrit-PatchSet: 3 Gerrit-Owner: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: arch/x86/smbios: Replace SMBIOS type4 processor upgrade fields values...
by Martin L Roth (Code Review) 08 Jan '23

08 Jan '23

Attention is currently required from: Patrick Rudolph, Angel Pons, Jincheng Li, Martin Roth. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71633 ) Change subject: arch/x86/smbios: Replace SMBIOS type4 processor upgrade fields values by macros ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Patchset: PS2: Awesome! Thank you. -- To view, visit https://review.coreboot.org/c/coreboot/+/71633 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifed1d773b0b349f878648b8172fd770a397e9686 Gerrit-Change-Number: 71633 Gerrit-PatchSet: 2 Gerrit-Owner: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Sun, 08 Jan 2023 01:27:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/alderlake/acpi: Add Kconfig options for SCM and FCM
by Martin L Roth (Code Review) 08 Jan '23

08 Jan '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/64561 ) Change subject: soc/intel/alderlake/acpi: Add Kconfig options for SCM and FCM ...................................................................... soc/intel/alderlake/acpi: Add Kconfig options for SCM and FCM Software Connection Manager doesn't work with Linux 5.13 or later, resulting in TBT ports timing out. Not advertising this results in Firmware Connection Manager being used and TBT works correctly. Add Kconfig options to chose between SCM (Software Connection Manager) and FCM (Firmware Connection Manager). FCM is primary, as it's more compatible save for ChromeOS devices as ChromeOS uses SCM. Linux patch: torvalds/linux@c6da62a c6da62a219d028de10f2e22e93a34c7ee2b88d03 Tested with StarBook Mk VI (i7-1260P). Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Iac31d37c0873f41f7b14e1051fe214466d1ebdd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64561 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> --- M src/device/Kconfig M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/acpi/tcss.asl M src/soc/intel/meteorlake/Kconfig M src/soc/intel/meteorlake/acpi/tcss.asl M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/acpi/tcss.asl 7 files changed, 79 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved Subrata Banik: Looks good to me, approved Kapil Porwal: Looks good to me, but someone else must approve diff --git a/src/device/Kconfig b/src/device/Kconfig index d0cce77..1ff14a6 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -726,6 +726,30 @@ endif # PCIEXP_PLUGIN_SUPPORT +choice + prompt "Connection Manager" + default FIRMWARE_CONNECTION_MANAGER + help + Software Connection Manager doesn't work with Linux 5.13 or later, + resulting in TBT ports timing out. Firmware Connection Manager works + correctly. + + Linux patch: + torvalds/linux@c6da62a + c6da62a219d028de10f2e22e93a34c7ee2b88d03 + +config FIRMWARE_CONNECTION_MANAGER + bool "Firmware Connection Manager" + help + Disable SCM so that FCM can be used + +config SOFTWARE_CONNECTION_MANAGER + bool "Software Connection Manager" + help + Enable SCM so it's used instead of FCM. + +endchoice + config EARLY_PCI_BRIDGE bool "Early PCI bridge" depends on PCI diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 9d950a7..1b2f695 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -426,6 +426,9 @@ help Enables ACPI entry to provide silicon type information to IPU kernel driver. +config SOFTWARE_CONNECTION_MANAGER + default y if CHROMEOS + config ALDERLAKE_ENABLE_SOC_WORKAROUND bool default y diff --git a/src/soc/intel/alderlake/acpi/tcss.asl b/src/soc/intel/alderlake/acpi/tcss.asl index 826c607..9edaf77 100644 --- a/src/soc/intel/alderlake/acpi/tcss.asl +++ b/src/soc/intel/alderlake/acpi/tcss.asl @@ -161,6 +161,12 @@ CDW1 |= UNRECOGNIZED_REVISION } Return (Arg3) +#if CONFIG(SOFTWARE_CONNECTION_MANAGER) + /* + * Software Connection Manager doesn't work with Linux 5.13 or later and + * results in TBT ports timing out. Not advertising this results in + * Firmware Connection Manager being used and TBT works correctly. + */ } ElseIf (Arg0 == ToUUID("23A0D13A-26AB-486C-9C5F-0FFA525A575A")) { /* * Operating System Capabilities for USB4 @@ -192,6 +198,7 @@ INTER_DOMAIN_USB4_INTERNET_PROTOCOL CDW3 = Local0 Return (Arg3) +#endif } Else { CDW1 |= UNRECOGNIZED_UUID Return (Arg3) diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index a612846..7f9b941 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -325,6 +325,9 @@ int default 16 +config SOFTWARE_CONNECTION_MANAGER + default y if CHROMEOS + config SOC_INTEL_GFX_FRAMEBUFFER_OFFSET hex default 0x800000 diff --git a/src/soc/intel/meteorlake/acpi/tcss.asl b/src/soc/intel/meteorlake/acpi/tcss.asl index 6635d08..c136048 100644 --- a/src/soc/intel/meteorlake/acpi/tcss.asl +++ b/src/soc/intel/meteorlake/acpi/tcss.asl @@ -155,6 +155,12 @@ CDW1 |= UNRECOGNIZED_REVISION } Return (Arg3) +#if CONFIG(SOFTWARE_CONNECTION_MANAGER) + /* + * Software Connection Manager doesn't work with Linux 5.13 or later and + * results in TBT ports timing out. Not advertising this results in + * Firmware Connection Manager being used and TBT works correctly. + */ } ElseIf (Arg0 == ToUUID("23A0D13A-26AB-486C-9C5F-0FFA525A575A")) { /* * Operating System Capabilities for USB4 @@ -186,6 +192,7 @@ INTER_DOMAIN_USB4_INTERNET_PROTOCOL CDW3 = Local0 Return (Arg3) +#endif } Else { CDW1 |= UNRECOGNIZED_UUID Return (Arg3) diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index bcf4a82..288bb39 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -295,6 +295,9 @@ int default 16 +config SOFTWARE_CONNECTION_MANAGER + default y if CHROMEOS + # Intel recommends reserving the following resources per USB4 root port, # from TGL BIOS Spec (doc #611569) Revision 0.7.6 Section 7.2.5.1.5 # - 42 buses diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl index b24a9e6..08b3480 100644 --- a/src/soc/intel/tigerlake/acpi/tcss.asl +++ b/src/soc/intel/tigerlake/acpi/tcss.asl @@ -161,7 +161,7 @@ CDW1 |= UNRECOGNIZED_REVISION } Return (Arg3) -#if CONFIG(CHROMEOS) +#if CONFIG(SOFTWARE_CONNECTION_MANAGER) /* * Software Connection Manager doesn't work with Linux 5.13 or later and * results in TBT ports timing out. Not advertising this results in -- To view, visit https://review.coreboot.org/c/coreboot/+/64561 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac31d37c0873f41f7b14e1051fe214466d1ebdd8 Gerrit-Change-Number: 64561 Gerrit-PatchSet: 11 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/intel/alderlake/acpi: Add Kconfig options for SCM and FCM
by Martin L Roth (Code Review) 08 Jan '23

08 Jan '23

Attention is currently required from: Sean Rhodes, Tarun Tuli, Matt DeVillier, John Zhao, Tim Wawrzynczak. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64561 ) Change subject: soc/intel/alderlake/acpi: Add Kconfig options for SCM and FCM ...................................................................... Patch Set 10: Code-Review+2 (1 comment) Patchset: PS10: Thanks Sean. -- To view, visit https://review.coreboot.org/c/coreboot/+/64561 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac31d37c0873f41f7b14e1051fe214466d1ebdd8 Gerrit-Change-Number: 64561 Gerrit-PatchSet: 10 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Comment-Date: Sun, 08 Jan 2023 01:26:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Add support to configure package c-state demotion
by Martin L Roth (Code Review) 08 Jan '23

08 Jan '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71654 ) Change subject: soc/intel/meteorlake: Add support to configure package c-state demotion ...................................................................... soc/intel/meteorlake: Add support to configure package c-state demotion This patch adds the support to enable/disable package c-state demotion feature from the devicetree based on mainboard requirement. Port of commit 4be8d9e80deb ("soc/intel/adl: Add support to configure package c-state demotion") BUG=none TEST=Boot to the OS on Google/Rex. Snippet from FSP log: [SPEW ] PkgCState Demotion : 0x1 Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> Change-Id: I0a4b0b181349ce41035524482add4336cf83a68b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71654 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/meteorlake/chip.h M src/soc/intel/meteorlake/fsp_params.c 2 files changed, 33 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h index ad382e3..dfd5c36 100644 --- a/src/soc/intel/meteorlake/chip.h +++ b/src/soc/intel/meteorlake/chip.h @@ -347,6 +347,13 @@ uint8_t lan_clk; /* + * Enable or Disable Package C-state Demotion. + * Default is set to 0. + * Set this to 1 in order to disable Package C-state demotion. + */ + bool disable_package_c_state_demotion; + + /* * Enable or Disable Skipping MBP HOB. * Default is set to 0 and set to 1 to skip the MBP HOB. */ diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index acf376b..e850eaa 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -642,6 +642,7 @@ /* Enable the energy efficient turbo mode */ s_cfg->EnergyEfficientTurbo = 1; s_cfg->PmcLpmS0ixSubStateEnableMask = get_supported_lpm_mask(); + s_cfg->PkgCStateDemotion = !config->disable_package_c_state_demotion; } -- To view, visit https://review.coreboot.org/c/coreboot/+/71654 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a4b0b181349ce41035524482add4336cf83a68b Gerrit-Change-Number: 71654 Gerrit-PatchSet: 2 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/meteorlake: Set max Pkg C-states to Auto
by Martin L Roth (Code Review) 08 Jan '23

08 Jan '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71653 ) Change subject: soc/intel/meteorlake: Set max Pkg C-states to Auto ...................................................................... soc/intel/meteorlake: Set max Pkg C-states to Auto This patch configures max Pkg C-state to Auto which limits the max C-state to deep C-state. Port of commit af42906efa72 ("soc/intel/alderlake: Set max Pkg C-states to Auto") BUG=none TEST=Boot to the OS on Google/Rex. Snippet from FSP log: [SPEW ] PkgCStateLimit : 0xFF Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> Change-Id: Ic403ab83a594b04920d5cf600432939687a2598b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71653 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/meteorlake/chip.h M src/soc/intel/meteorlake/fsp_params.c 2 files changed, 45 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h index 19b34a2..ad382e3 100644 --- a/src/soc/intel/meteorlake/chip.h +++ b/src/soc/intel/meteorlake/chip.h @@ -43,6 +43,25 @@ DDI_ENABLE_HPD = 1 << 1, }; +/* + * The Max Pkg Cstate + * Values 0 - C0/C1, 1 - C2, 2 - C3, 3 - C6, 4 - C7, 5 - C7S, 6 - C8, 7 - C9, 8 - C10, + * 254 - CPU Default , 255 - Auto. + */ +enum pkgcstate_limit { + LIMIT_C0_C1 = 0, + LIMIT_C2 = 1, + LIMIT_C3 = 2, + LIMIT_C6 = 3, + LIMIT_C7 = 4, + LIMIT_C7S = 5, + LIMIT_C8 = 6, + LIMIT_C9 = 7, + LIMIT_C10 = 8, + LIMIT_CPUDEFAULT = 254, + LIMIT_AUTO = 255, +}; + /* Bit values for use in LpmStateEnableMask. */ enum lpm_state_mask { LPM_S0i2_0 = BIT(0), diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index 0cf221b..acf376b 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -638,6 +638,7 @@ s_cfg->Hwp = 1; s_cfg->Cx = 1; s_cfg->PsOnEnable = 1; + s_cfg->PkgCStateLimit = LIMIT_AUTO; /* Enable the energy efficient turbo mode */ s_cfg->EnergyEfficientTurbo = 1; s_cfg->PmcLpmS0ixSubStateEnableMask = get_supported_lpm_mask(); -- To view, visit https://review.coreboot.org/c/coreboot/+/71653 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic403ab83a594b04920d5cf600432939687a2598b Gerrit-Change-Number: 71653 Gerrit-PatchSet: 2 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: drivers/amd: Update to use defined post codes
by Martin L Roth (Code Review) 08 Jan '23

08 Jan '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71591 ) Change subject: drivers/amd: Update to use defined post codes ...................................................................... drivers/amd: Update to use defined post codes Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I2d5700534c07e89b3908a2e6b827db919a48795d Reviewed-on: https://review.coreboot.org/c/coreboot/+/71591 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/drivers/amd/agesa/cache_as_ram.S 1 file changed, 17 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Fred Reitberger: Looks good to me, approved diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index 0d678d1..e342039 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -12,6 +12,7 @@ #include <cpu/x86/lapic_def.h> #include <cpu/x86/post_code.h> +#include <amdblocks/post_codes.h> .section .init @@ -30,7 +31,7 @@ */ bootblock_pre_c_entry: - post_code(0xa0) + post_code(POST_BOOTBLOCK_PRE_C_ENTRY) AMD_ENABLE_STACK @@ -56,7 +57,7 @@ movd %mm1, %eax pushl %eax /* tsc[31:0] */ - post_code(0xa2) + post_code(POST_BOOTBLOCK_PRE_C_DONE) call bootblock_c_entry -- To view, visit https://review.coreboot.org/c/coreboot/+/71591 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d5700534c07e89b3908a2e6b827db919a48795d Gerrit-Change-Number: 71591 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/skyrim: Switch from LZMA to LZ4 compression for ramstage
by Martin L Roth (Code Review) 08 Jan '23

08 Jan '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71675 ) Change subject: mb/google/skyrim: Switch from LZMA to LZ4 compression for ramstage ...................................................................... mb/google/skyrim: Switch from LZMA to LZ4 compression for ramstage Because skyrim is loading ramstage from SPI with the DMA engine, the size of the compressed image is less important to load speed than decompression time. Because the LZ4 decompression is so much faster than LZMA, compressing with LZ4 saves us roughly 30ms in boot time. For size, we're spending roughly 57KiB: fallback/ramstage 0x9b00 stage 130864 LZMA (305316 decompressed) fallback/ramstage 0x9b00 stage 189126 LZ4 (305316 decompressed) Right now we have 2MiB empty space in Skyrim's RO before this change, and roughly 550KiB empty space in RW, so there aren't currently any size worries. Just for fun, I also tested uncompressed ramstage, and it was still 18ms faster than LZMA, but that makes it roughly 12ms slower than LZ4. BUG=b:264409477 TEST=Boot skyrim, look at boot speed. Signed-off-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Change-Id: Iedde6fc2db9d702c0ff2b0081e7baa254ac6699f Reviewed-on: https://review.coreboot.org/c/coreboot/+/71675 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/mainboard/google/skyrim/Kconfig 1 file changed, 37 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Arthur Heymans: Looks good to me, approved Fred Reitberger: Looks good to me, approved diff --git a/src/mainboard/google/skyrim/Kconfig b/src/mainboard/google/skyrim/Kconfig index 493ecb5..94659db 100644 --- a/src/mainboard/google/skyrim/Kconfig +++ b/src/mainboard/google/skyrim/Kconfig @@ -37,6 +37,7 @@ select I2C_TPM select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_TPM2 + select MB_COMPRESS_RAMSTAGE_LZ4 select SOC_AMD_MENDOCINO select SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP select SOC_AMD_COMMON_BLOCK_USE_ESPI -- To view, visit https://review.coreboot.org/c/coreboot/+/71675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iedde6fc2db9d702c0ff2b0081e7baa254ac6699f Gerrit-Change-Number: 71675 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: src/lib: Include LZMA in romstage for FSP-M
by Martin L Roth (Code Review) 08 Jan '23

08 Jan '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71674 ) Change subject: src/lib: Include LZMA in romstage for FSP-M ...................................................................... src/lib: Include LZMA in romstage for FSP-M Previously, LZMA was included in romstage because it was almost always needed to decompress ramstage. When compressing ramstage with LZ4, but using LZMA compression for FSP-M, we still need the LZMA decompression to be present, so update when the Makefile includes the LZMA decoder. Signed-off-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Change-Id: Id52d25a13420f05db8b2b563de0448f9d44638e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71674 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/lib/Makefile.inc 1 file changed, 22 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved Fred Reitberger: Looks good to me, approved diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 030959c..c83004a 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -95,7 +95,9 @@ romstage-y += fmap.c romstage-y += delay.c romstage-y += cbfs.c -romstage-$(CONFIG_COMPRESS_RAMSTAGE_LZMA) += lzma.c lzmadecode.c +ifneq ($(CONFIG_COMPRESS_RAMSTAGE_LZMA)$(CONFIG_FSP_COMPRESS_FSP_M_LZMA),) +romstage-y += lzma.c lzmadecode.c +endif romstage-y += libgcc.c romstage-y += memrange.c romstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c -- To view, visit https://review.coreboot.org/c/coreboot/+/71674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id52d25a13420f05db8b2b563de0448f9d44638e0 Gerrit-Change-Number: 71674 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: src/lib: Include LZMA in romstage for FSP-M
by Martin L Roth (Code Review) 08 Jan '23

08 Jan '23

Attention is currently required from: Martin Roth. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71674 ) Change subject: src/lib: Include LZMA in romstage for FSP-M ...................................................................... Patch Set 1: (1 comment) File src/lib/Makefile.inc: https://review.coreboot.org/c/coreboot/+/71674/comment/66a31787_81b1b740 PS1, Line 98: ifneq ($(CONFIG_COMPRESS_RAMSTAGE_LZMA)$(CONFIG_FSP_COMPRESS_FSP_M_LZMA),) > Could also just always compile it in and let the linker garbage collection take care of it. It's not a bad point, and maybe as a part of future cleanup we can go through and remove the extra conditions. -- To view, visit https://review.coreboot.org/c/coreboot/+/71674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id52d25a13420f05db8b2b563de0448f9d44638e0 Gerrit-Change-Number: 71674 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Sun, 08 Jan 2023 01:21:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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