coreboot-gerrit January 2023

coreboot-gerrit@coreboot.org

1 participants
5879 discussions

[M] Change in coreboot[master]: soc/intel: Add Kconfigs to define scaling factor for cores
by Sridhar Siricilla (Code Review) 08 Jan '23

08 Jan '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal, Arthur Heymans. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71687 ) Change subject: soc/intel: Add Kconfigs to define scaling factor for cores ...................................................................... Patch Set 2: (2 comments) File src/soc/intel/common/block/acpi/cpu_hybrid.c: https://review.coreboot.org/c/coreboot/+/71687/comment/daaca744_3b5615f5 PS1, Line 78: soc_get_scaling_factor > > Do we even need this function now? […] Ack https://review.coreboot.org/c/coreboot/+/71687/comment/5a1b75a9_1e010da0 PS1, Line 79: scal_factor.performance_core > Can't we use `CONFIG_SOC_INTEL_PERF_CORE_SCAL_FACTOR`? Ack. -- To view, visit https://review.coreboot.org/c/coreboot/+/71687 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55e4d815116ef40c5f33be64ab495e942bf35ee8 Gerrit-Change-Number: 71687 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sun, 08 Jan 2023 18:16:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: soc/intel: Add Kconfigs to define scaling factor for cores
by Sridhar Siricilla (Code Review) 08 Jan '23

08 Jan '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal, Sridhar Siricilla. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Kapil Porwal, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/71687 to look at the new patch set (#2). Change subject: soc/intel: Add Kconfigs to define scaling factor for cores ...................................................................... soc/intel: Add Kconfigs to define scaling factor for cores The patch adds Kconfigs to define scaling factor for Efficient and Performance cores instead of using hard coded values in the soc code. Also, the patches uses the Kconfigs directly to calculate the core's nominal performance. TEST=Build the code for Gimble and Rex. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I55e4d815116ef40c5f33be64ab495e942bf35ee8 --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/cpu.c M src/soc/intel/common/block/acpi/cpu_hybrid.c M src/soc/intel/common/block/include/intelblocks/acpi.h M src/soc/intel/meteorlake/Kconfig M src/soc/intel/meteorlake/cpu.c 6 files changed, 39 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/71687/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71687 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55e4d815116ef40c5f33be64ab495e942bf35ee8 Gerrit-Change-Number: 71687 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newpatchset

1 0

[L] Change in coreboot[master]: soc/amd/common/psp: Support PSP SMI handler
by ritul guru (Code Review) 08 Jan '23

08 Jan '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin L Roth, Marshall Dawson, Matt DeVillier, Paul Menzel, Arthur Heymans, Martin Roth, Fred Reitberger, Felix Held. ritul guru has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/65523 ) Change subject: soc/amd/common/psp: Support PSP SMI handler ...................................................................... Patch Set 27: (6 comments) File src/soc/amd/common/block/psp/psp_smi.c: https://review.coreboot.org/c/coreboot/+/65523/comment/34f6efe3_076e43f2 PS24, Line 68: static enum mbox_p2c_status find_psp_spi_flash_device_region(const struct spi_flash **flash) > the code won't compile, since both the store and id variable is used inside the function, but not av […] Ack https://review.coreboot.org/c/coreboot/+/65523/comment/55e4fe10_8ce835b8 PS24, Line 100: find_spi_flash_device_region > because right now this code doesn't compile when selecting this feature in a mainboard due to no fun […] Ack File src/soc/amd/common/block/psp/psp_smi.c: https://review.coreboot.org/c/coreboot/+/65523/comment/5f491533_7223b561 PS26, Line 211: /* : * Assume PSP NVRAM region address 0 writes indicate : * initialization due to PSP NVRAM region being empty/erased. : * Ensure alternative SPI flash is in similar state in order : * to keep PSP NVRAM data synchronized. : */ : if (addr == 0) { : printk(BIOS_DEBUG, "PSP: Alt SPI erase NVRAM\n"); : : if (rdev_eraseat(&store, 0, region_device_sz(&store)) : != region_device_sz(&store)) { : printk(BIOS_ERR, "PSP: Failed to erase Alt SPI NVRAM\n"); : ret = MBOX_PSP_COMMAND_PROCESS_ERROR; : goto out; : } : } > this doesn't look like the behavior i'd assume the PSP would expect. […] It is based on chip select, operation happens only on one spirom. https://review.coreboot.org/c/coreboot/+/65523/comment/53781d67_7e7e35ca PS26, Line 280: > in the CONFIG(SOC_AMD_COMMON_BLOCK_SPI_ALT) case only the pages in the secondary spi flash on SPI_CS […] yes, based on chip select. File src/soc/amd/common/block/spi/Kconfig: https://review.coreboot.org/c/coreboot/+/65523/comment/7e3b4213_a12c0c4a PS23, Line 104: SOC_AMD_COMMON_BLOCK_SPI_ALT > this looks to me to be a feature where the system has two separate spi flash chips on the two chip s […] This is when there is alternative SPIROM (dual SPIROM), which contains a backup of original SPI or any additional write to SPIROM will happen only in ALT SPIROM(based on chip select). This is independent SPIROM implementation, so should not rely on other configs. File src/soc/amd/common/block/spi/Kconfig: https://review.coreboot.org/c/coreboot/+/65523/comment/f43e8098_bb8220a0 PS26, Line 108: a SPI flash > should this be "a second SPI flash"? i'm not sure if i understand correctly what this does exactly, […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/65523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1f4646101b90bc52c492f35fd26e6ca1e496142 Gerrit-Change-Number: 65523 Gerrit-PatchSet: 27 Gerrit-Owner: ritul guru <ritul.bits(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 08 Jan 2023 17:41:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: ritul guru <ritul.bits(a)gmail.com> Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

1 0

[L] Change in coreboot[master]: soc/amd/common/psp: Support PSP SMI handler
by ritul guru (Code Review) 08 Jan '23

08 Jan '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin L Roth, ritul guru, Marshall Dawson, Matt DeVillier, Paul Menzel, Arthur Heymans, Martin Roth, Fred Reitberger. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Matt DeVillier, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/65523 to look at the new patch set (#28). Change subject: soc/amd/common/psp: Support PSP SMI handler ...................................................................... soc/amd/common/psp: Support PSP SMI handler Enable optional support for registering an SMI handler for PSP SPI flash read/write/erase operation requests. The PSP SMI needs to be configured before the PSP can actually issue SMI after being informed of the SMI trigger info via the SMM_INFO command. See AMD document 55570 revision 3.16 for additional details. The PSP will not trigger SMI until informed via the SMM area buffer that SMM requests are ready to be served. See AMD document 55758 revision 2.00 for additional details. Change-Id: Ie1f4646101b90bc52c492f35fd26e6ca1e496142 Signed-off-by: Ritul Guru <ritul.bits(a)gmail.com> --- M src/soc/amd/common/block/include/amdblocks/psp.h M src/soc/amd/common/block/include/amdblocks/smi.h M src/soc/amd/common/block/include/amdblocks/spi.h M src/soc/amd/common/block/psp/Kconfig M src/soc/amd/common/block/psp/Makefile.inc M src/soc/amd/common/block/psp/psp_def.h M src/soc/amd/common/block/psp/psp_gen2.c A src/soc/amd/common/block/psp/psp_p2c.c A src/soc/amd/common/block/psp/psp_smi.c M src/soc/amd/common/block/psp/psp_smm.c M src/soc/amd/common/block/smi/smi_util.c M src/soc/amd/common/block/spi/Kconfig M src/soc/amd/picasso/smihandler.c M src/soc/amd/stoneyridge/include/soc/smi.h 14 files changed, 702 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/65523/28 -- To view, visit https://review.coreboot.org/c/coreboot/+/65523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1f4646101b90bc52c492f35fd26e6ca1e496142 Gerrit-Change-Number: 65523 Gerrit-PatchSet: 28 Gerrit-Owner: ritul guru <ritul.bits(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: security/intel/txt: Add helper function to disable TXT
by Sridhar Siricilla (Code Review) 08 Jan '23

08 Jan '23

Attention is currently required from: Subrata Banik, Jérémy Compostella, Paul Menzel, Angel Pons, Lean Sheng Tan, Werner Zeh. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71574 ) Change subject: security/intel/txt: Add helper function to disable TXT ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71574 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27f613428e82a1dd924172eab853d2ce9c32b473 Gerrit-Change-Number: 71574 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Sun, 08 Jan 2023 16:54:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: security/intel/txt: Create Intel TXT lib with helper functions
by Sridhar Siricilla (Code Review) 08 Jan '23

08 Jan '23

Sridhar Siricilla has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71573 ) Change subject: security/intel/txt: Create Intel TXT lib with helper functions ...................................................................... security/intel/txt: Create Intel TXT lib with helper functions This patch decouples useful TXT related operations from the romstage.c file alone and moves them into a helper txtlib.c. This effort will be helpful for SoC users to perform TXT related operations (like Disabling TXT) even without selecting INTEL_TXT config. At present, those helper functions are only available upon selecting INTEL_TXT which is not getting enabled for most of the SoC platform in the scope of the Chromebooks. TEST=Able to access functions from txtlib.c even without selecting INTEL_TXT config. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Iff5b4e705e18cbaf181b4c71bfed368c3ed047ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/71573 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tarun Tuli <taruntuli(a)google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/security/intel/txt/Kconfig M src/security/intel/txt/Makefile.inc M src/security/intel/txt/romstage.c A src/security/intel/txt/txtlib.c A src/security/intel/txt/txtlib.h 5 files changed, 96 insertions(+), 38 deletions(-) Approvals: build bot (Jenkins): Verified Sridhar Siricilla: Looks good to me, approved Tarun Tuli: Looks good to me, approved diff --git a/src/security/intel/txt/Kconfig b/src/security/intel/txt/Kconfig index 19eecc4..637a6a7 100644 --- a/src/security/intel/txt/Kconfig +++ b/src/security/intel/txt/Kconfig @@ -1,8 +1,17 @@ # SPDX-License-Identifier: GPL-2.0-only +config INTEL_TXT_LIB + bool + default n + help + This option includes library functions related to the TXT + operation which SoC would still like to access without enabling + INTEL_TXT config. + config INTEL_TXT bool "Intel TXT support" default n + select INTEL_TXT_LIB select MRC_SETTINGS_PROTECT if CACHE_MRC_SETTINGS select ENABLE_VMX if CPU_INTEL_COMMON select AP_IN_SIPI_WAIT diff --git a/src/security/intel/txt/Makefile.inc b/src/security/intel/txt/Makefile.inc index 7132ca8..e19bacf 100644 --- a/src/security/intel/txt/Makefile.inc +++ b/src/security/intel/txt/Makefile.inc @@ -1,3 +1,5 @@ +romstage-$(CONFIG_INTEL_TXT_LIB) += txtlib.c + ifeq ($(CONFIG_INTEL_TXT),y) all-y += logging.c diff --git a/src/security/intel/txt/romstage.c b/src/security/intel/txt/romstage.c index e1329dd..fa0ba3c 100644 --- a/src/security/intel/txt/romstage.c +++ b/src/security/intel/txt/romstage.c @@ -4,52 +4,15 @@ #include <console/console.h> #include <cpu/intel/common/common.h> #include <cpu/x86/cr.h> -#include <cpu/x86/msr.h> #include <device/mmio.h> #include <southbridge/intel/common/pmbase.h> -#include <timer.h> #include <types.h> -#include <security/tpm/tis.h> - #include "txt.h" +#include "txtlib.h" #include "txt_register.h" #include "txt_getsec.h" -static bool is_establishment_bit_asserted(void) -{ - struct stopwatch timer; - uint8_t access; - - /* Spec says no less than 30 milliseconds */ - stopwatch_init_msecs_expire(&timer, 50); - - while (true) { - access = read8((void *)TPM_ACCESS_REG); - - /* Register returns all ones if TPM is missing */ - if (access == 0xff) - return false; - - if (access & TPM_ACCESS_VALID) - break; - - /* On timeout, assume that the TPM is not working */ - if (stopwatch_expired(&timer)) - return false; - } - - /* This bit uses inverted logic: if cleared, establishment is asserted */ - return !(access & TPM_ACCESS_ESTABLISHMENT); -} - -static bool is_txt_cpu(void) -{ - const uint32_t ecx = cpu_get_feature_flags_ecx(); - - return (ecx & (CPUID_SMX | CPUID_VMX)) == (CPUID_SMX | CPUID_VMX); -} - static bool is_txt_chipset(void) { uint32_t eax; diff --git a/src/security/intel/txt/txtlib.c b/src/security/intel/txt/txtlib.c new file mode 100644 index 0000000..3ec2322 --- /dev/null +++ b/src/security/intel/txt/txtlib.c @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/cpu.h> +#include <cpu/intel/common/common.h> +#include <cpu/x86/msr.h> +#include <device/mmio.h> +#include <security/intel/txt/txt.h> +#include <security/tpm/tis.h> +#include <timer.h> + +#include "txtlib.h" +#include "txt_register.h" + +bool is_establishment_bit_asserted(void) +{ + struct stopwatch timer; + uint8_t access; + + /* Spec says no less than 30 milliseconds */ + stopwatch_init_msecs_expire(&timer, 50); + + while (true) { + access = read8((void *)TPM_ACCESS_REG); + + /* Register returns all ones if TPM is missing */ + if (access == 0xff) + return false; + + if (access & TPM_ACCESS_VALID) + break; + + /* On timeout, assume that the TPM is not working */ + if (stopwatch_expired(&timer)) + return false; + } + + /* This bit uses inverted logic: if cleared, establishment is asserted */ + return !(access & TPM_ACCESS_ESTABLISHMENT); +} + +bool is_txt_cpu(void) +{ + const uint32_t ecx = cpu_get_feature_flags_ecx(); + + return (ecx & (CPUID_SMX | CPUID_VMX)) == (CPUID_SMX | CPUID_VMX); +} diff --git a/src/security/intel/txt/txtlib.h b/src/security/intel/txt/txtlib.h new file mode 100644 index 0000000..35703b6 --- /dev/null +++ b/src/security/intel/txt/txtlib.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SECURITY_INTEL_TXT_LIB_H_ +#define SECURITY_INTEL_TXT_LIB_H_ + +#include <types.h> + +bool is_establishment_bit_asserted(void); + +bool is_txt_cpu(void); + +#endif /* SECURITY_INTEL_TXT_LIB_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/71573 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff5b4e705e18cbaf181b4c71bfed368c3ed047ed Gerrit-Change-Number: 71573 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: security/intel/txt: Create Intel TXT lib with helper functions
by Sridhar Siricilla (Code Review) 08 Jan '23

08 Jan '23

Attention is currently required from: Subrata Banik, Jérémy Compostella, Angel Pons, Lean Sheng Tan, Werner Zeh. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71573 ) Change subject: security/intel/txt: Create Intel TXT lib with helper functions ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71573 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff5b4e705e18cbaf181b4c71bfed368c3ed047ed Gerrit-Change-Number: 71573 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Sun, 08 Jan 2023 16:50:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: cpu/x86/smm: Enable setting SMM console log level from mainboard
by Johnny Lin (Code Review) 08 Jan '23

08 Jan '23

Attention is currently required from: Marc Jones, Martin L Roth, Patrick Rudolph, Jonathan Zhang, Paul Menzel, Rocky Phagura, Jingle Hsu, Angel Pons, Arthur Heymans, Morgan Jang, Kyösti Mälkki. Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49460 ) Change subject: cpu/x86/smm: Enable setting SMM console log level from mainboard ...................................................................... Patch Set 29: (4 comments) File src/cpu/x86/Kconfig: https://review.coreboot.org/c/coreboot/+/49460/comment/2b66ea21_7d8098ae PS28, Line 217: This enables setting SMM console log level from mainboard, it can let : SMM have different log level than other stages for more flexibility. > “from mainboard” is ambiguous for me. Maybe keep using “at runtime”. […] Done https://review.coreboot.org/c/coreboot/+/49460/comment/be314e8f_275602f7 PS28, Line 219: certain data that requires searching > I do not know, what you mean here. […] Rephrased "reading the log level from non-volatile memory such as flash VPD or CMOS is not very ideal to be done in SMM". File src/cpu/x86/smm/smm_module_handler.c: https://review.coreboot.org/c/coreboot/+/49460/comment/e321a1e1_e225c8bd PS28, Line 58: return smm_runtime.smm_log_level; > Can’t you do the check in C, and return 0 if `!IS_ENABLED(RUNTIME_CONFIGURABLE_SMM_LOGLEVEL)`? Do you mean removing the preprocessor at line 55 '#if CONFIG(RUNTIME_CONFIGURABLE_SMM_LOGLEVEL)' and use C instead? That would cause build error "redefinition of 'get_console_loglevel'" when CONSOLE_OVERRIDE_LOGLEVEL is not selected. Or do you mean adding a check in the function? but smm_log_level would be set to 0 in src/cpu/x86/smm/smm_module_loader.c when RUNTIME_CONFIGURABLE_SMM_LOGLEVEL is not selected. File src/include/cpu/x86/smm.h: https://review.coreboot.org/c/coreboot/+/49460/comment/667a347f_62db060b PS28, Line 70: u8 smm_log_level; > In `src/console/init.c` `get_log_level()` returns int. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/49460 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81722a4f1bf75ec942cc06e403ad702dfe938e71 Gerrit-Change-Number: 49460 Gerrit-PatchSet: 29 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Rocky Phagura Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rocky Phagura <rphagura(a)fb.com> Gerrit-Attention: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Sun, 08 Jan 2023 15:01:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: cpu/x86/smm: Enable setting SMM console log level from mainboard
by Johnny Lin (Code Review) 08 Jan '23

08 Jan '23

Attention is currently required from: Marc Jones, Martin L Roth, Patrick Rudolph, Jonathan Zhang, Johnny Lin, Rocky Phagura, Jingle Hsu, Angel Pons, Arthur Heymans, Morgan Jang, Kyösti Mälkki. Hello build bot (Jenkins), Marc Jones, Nico Huber, Patrick Rudolph, Jonathan Zhang, Rocky Phagura, Jingle Hsu, Angel Pons, Rocky Phagura, Arthur Heymans, Morgan Jang, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49460 to look at the new patch set (#29). Change subject: cpu/x86/smm: Enable setting SMM console log level from mainboard ...................................................................... cpu/x86/smm: Enable setting SMM console log level from mainboard Add a Kconfig RUNTIME_CONFIGURABLE_SMM_LOGLEVEL that enables mainboard to override mainboard_set_smm_log_level for SMM log level. This can let SMM have different log level than other stages for more flexibility. Another reason is that getting certain data that requires searching from flash VPD or CMOS is not very ideal to be done in SMM, so in this change the value can be passed via the member variable in struct smm_runtime and be referenced directly in SMM. One example is that mainboard can get the desired SMM log level from VPD/CMOS, and pass SMM console log level via the variable and in SMM it can be referenced in get_console_loglevel() override function directly. Tested=On OCP Delta Lake, verified SMM log level can be overridden. Change-Id: I81722a4f1bf75ec942cc06e403ad702dfe938e71 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/cpu/x86/Kconfig M src/cpu/x86/smm/smm_module_handler.c M src/cpu/x86/smm/smm_module_loader.c M src/include/cpu/x86/smm.h 4 files changed, 53 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/49460/29 -- To view, visit https://review.coreboot.org/c/coreboot/+/49460 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81722a4f1bf75ec942cc06e403ad702dfe938e71 Gerrit-Change-Number: 49460 Gerrit-PatchSet: 29 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Rocky Phagura Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Rocky Phagura <rphagura(a)fb.com> Gerrit-Attention: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: include/memory_info.h: Add soc_num to dimm_info struct
by Elyes Haouas (Code Review) 08 Jan '23

08 Jan '23

Attention is currently required from: Shuming Chu (Shuming). Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70662 ) Change subject: include/memory_info.h: Add soc_num to dimm_info struct ...................................................................... Patch Set 2: (1 comment) File src/include/memory_info.h: https://review.coreboot.org/c/coreboot/+/70662/comment/350afc20_afa53ebe PS2, Line 51: dimm_num I'm confused isn't dimm_num = soc_num ? -- To view, visit https://review.coreboot.org/c/coreboot/+/70662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b9e2b87fda2d7c32ecb8ce9d989795c8b869cea Gerrit-Change-Number: 70662 Gerrit-PatchSet: 2 Gerrit-Owner: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Comment-Date: Sun, 08 Jan 2023 06:38:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2023