coreboot-gerrit January 2023

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[S] Change in coreboot[master]: security/intel/txt: Add helper function to disable TXT
by Eric Lai (Code Review) 09 Jan '23

09 Jan '23

Attention is currently required from: Subrata Banik, Jérémy Compostella, Paul Menzel, Angel Pons, Lean Sheng Tan, Werner Zeh. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71574 ) Change subject: security/intel/txt: Add helper function to disable TXT ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71574 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27f613428e82a1dd924172eab853d2ce9c32b473 Gerrit-Change-Number: 71574 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Mon, 09 Jan 2023 00:16:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya: Allow respective variant to choose NEM config
by Eric Lai (Code Review) 09 Jan '23

09 Jan '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Martin Roth. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71743 ) Change subject: mb/google/brya: Allow respective variant to choose NEM config ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71743 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbd492a3d210739120c7ad16415cb7912f5b70ec Gerrit-Change-Number: 71743 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Mon, 09 Jan 2023 00:09:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/dedede/var/dibbi: Generate SPD ID for supported parts
by Eric Lai (Code Review) 09 Jan '23

09 Jan '23

Attention is currently required from: Sam McNally, Liam Flaherty. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71710 ) Change subject: mb/google/dedede/var/dibbi: Generate SPD ID for supported parts ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c95ced79e14bb4a99aa1fa5f4fc3bc0681cc1cc Gerrit-Change-Number: 71710 Gerrit-PatchSet: 3 Gerrit-Owner: Liam Flaherty <liamflaherty(a)chromium.org> Gerrit-Reviewer: Adam Mills <adamjmills(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sam McNally <sammc(a)google.com> Gerrit-Attention: Liam Flaherty <liamflaherty(a)chromium.org> Gerrit-Comment-Date: Mon, 09 Jan 2023 00:05:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/dedede/var/dibbi: Generate SPD ID for supported parts
by Adam Mills (Code Review) 08 Jan '23

08 Jan '23

Attention is currently required from: Sam McNally, Liam Flaherty. Adam Mills has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71710 ) Change subject: mb/google/dedede/var/dibbi: Generate SPD ID for supported parts ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/71710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c95ced79e14bb4a99aa1fa5f4fc3bc0681cc1cc Gerrit-Change-Number: 71710 Gerrit-PatchSet: 3 Gerrit-Owner: Liam Flaherty <liamflaherty(a)chromium.org> Gerrit-Reviewer: Adam Mills <adamjmills(a)google.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sam McNally <sammc(a)google.com> Gerrit-Attention: Liam Flaherty <liamflaherty(a)chromium.org> Gerrit-Comment-Date: Sun, 08 Jan 2023 23:07:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/dedede/var/dibbi: Generate SPD ID for supported parts
by Liam Flaherty (Code Review) 08 Jan '23

08 Jan '23

Attention is currently required from: Sam McNally. Liam Flaherty has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71710 ) Change subject: mb/google/dedede/var/dibbi: Generate SPD ID for supported parts ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/dedede/variants/dibbi/memory/mem_parts_used.txt: https://review.coreboot.org/c/coreboot/+/71710/comment/d23e3257_ab32831f PS2, Line 1: # This is a CSV file containing a list of memory parts used by this variant. > Please keep this comment. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/71710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c95ced79e14bb4a99aa1fa5f4fc3bc0681cc1cc Gerrit-Change-Number: 71710 Gerrit-PatchSet: 3 Gerrit-Owner: Liam Flaherty <liamflaherty(a)chromium.org> Gerrit-Reviewer: Adam Mills <adamjmills(a)google.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sam McNally <sammc(a)google.com> Gerrit-Comment-Date: Sun, 08 Jan 2023 23:05:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sam McNally <sammc(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/dedede/var/dibbi: Generate SPD ID for supported parts
by Liam Flaherty (Code Review) 08 Jan '23

08 Jan '23

Attention is currently required from: Liam Flaherty. Hello Sam McNally, build bot (Jenkins), Adam Mills, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/71710 to look at the new patch set (#3). Change subject: mb/google/dedede/var/dibbi: Generate SPD ID for supported parts ...................................................................... mb/google/dedede/var/dibbi: Generate SPD ID for supported parts Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. BUG=b:260934724, b:255447299 BRANCH=dedede TEST=build Change-Id: I8c95ced79e14bb4a99aa1fa5f4fc3bc0681cc1cc Signed-off-by: Liam Flaherty <liamflaherty(a)chromium.org> --- M src/mainboard/google/dedede/variants/dibbi/memory/Makefile.inc M src/mainboard/google/dedede/variants/dibbi/memory/dram_id.generated.txt M src/mainboard/google/dedede/variants/dibbi/memory/mem_parts_used.txt 3 files changed, 28 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/71710/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/71710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c95ced79e14bb4a99aa1fa5f4fc3bc0681cc1cc Gerrit-Change-Number: 71710 Gerrit-PatchSet: 3 Gerrit-Owner: Liam Flaherty <liamflaherty(a)chromium.org> Gerrit-Reviewer: Adam Mills <adamjmills(a)google.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Liam Flaherty <liamflaherty(a)chromium.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/nissa/var/craask: remove SAR UNUSED fw_config
by Reka Norman (Code Review) 08 Jan '23

08 Jan '23

Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71690 ) Change subject: mb/google/nissa/var/craask: remove SAR UNUSED fw_config ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/brya/variants/craask/overridetree.cb: https://review.coreboot.org/c/coreboot/+/71690/comment/cb7de06c_8bcc9f1e PS2, Line 23: field WIFI_SAR_ID 13 15 : option ID_0 0 : end > So get rid of the option and just hardcode it to option ID_0? The field is mostly to reserve space in fw_config in case multiple SAR tables are needed in the future. Yes we could hardcode it for now then add the field later if needed, but I think adding it now is fine too. > Yeah, value 7 wasn't used, because you can't get a 7 with just 2 bits. It's 3 bits, the start and end bits are both inclusive. > Why was that even added? There's a craask SKU which uses Intel wifi but does not need a SAR table, so UNUSED was meant to support that. But it turns out it's fine to use the same SAR table used for other SKUs on that SKU too, even though it's not strictly necessary. So we decided to do that to simplify things. -- To view, visit https://review.coreboot.org/c/coreboot/+/71690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4298376899f881dd2265aef5a0bbc5bcc46728a1 Gerrit-Change-Number: 71690 Gerrit-PatchSet: 3 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Sun, 08 Jan 2023 22:34:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya: Allow respective variant to choose NEM config
by Reka Norman (Code Review) 08 Jan '23

08 Jan '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Martin Roth. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71743 ) Change subject: mb/google/brya: Allow respective variant to choose NEM config ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71743 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbd492a3d210739120c7ad16415cb7912f5b70ec Gerrit-Change-Number: 71743 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Sun, 08 Jan 2023 22:12:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/common: Untie PRMRR from SGX
by Sridhar Siricilla (Code Review) 08 Jan '23

08 Jan '23

Sridhar Siricilla has submitted this change. ( https://review.coreboot.org/c/coreboot/+/70819 ) Change subject: soc/intel/common: Untie PRMRR from SGX ...................................................................... soc/intel/common: Untie PRMRR from SGX PRMRR is used by many Intel SOC features, not just Intel SGX. As of now SGX and Key Locker are the features that need PRMRR. Untie it from Intel SGX specific files and move to common cpulib. Also rename PRMRR size config option. Use the renamed PRMRR size config option to set the PRMRR size. TEST=Able to set PRMRR size using config. Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com> Change-Id: I0cd49a87be0293530705802fd9b830201a5863c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70819 Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/sgx/Kconfig 3 files changed, 89 insertions(+), 43 deletions(-) Approvals: build bot (Jenkins): Verified Sridhar Siricilla: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 985bd68..1324804 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -171,3 +171,65 @@ mechanism to encrypt and decrypt data with an AES key without having access to the raw key value by converting AES keys into "handles". The specification of Key Locker can be found via document #343965 on Intel's site. + +config SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE + int + depends on INTEL_KEYLOCKER || SOC_INTEL_COMMON_BLOCK_SGX_ENABLE + default 256 if SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_256MB || SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_MAX + default 128 if SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_128MB + default 64 if SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_64MB + default 32 if SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_32MB + default 16 if SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_16MB + default 8 if SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_8MB + default 4 if SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_4MB + default 2 if SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_2MB + default 0 if SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_0MB + default 0 + +choice + prompt "PRMRR size" + depends on INTEL_KEYLOCKER || SOC_INTEL_COMMON_BLOCK_SGX + default SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_MAX if SOC_INTEL_COMMON_BLOCK_SGX_ENABLE + default SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_2MB if !SOC_INTEL_COMMON_BLOCK_SGX_ENABLE && INTEL_KEYLOCKER + default SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_0MB if !SOC_INTEL_COMMON_BLOCK_SGX_ENABLE && !INTEL_KEYLOCKER + help + PRMRR (Protected Memory Range) is the space in RAM that is used to provide a + protected memory area (e.g. for the Intel SGX Secure Enclaves and Intel + Key Locker). The memory region is accessible only by the processor itself to + protect the data from unauthorized access. + + This option allows to select PRMRR size for the intended feature. Depending on + the SoC a lower, compatible value may be chosen at runtime as not all values + are supported on all families. + +config SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_MAX + bool "Maximum" + +config SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_256MB + bool "256 MiB" + +config SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_128MB + bool "128 MiB" + +config SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_64MB + bool "64 MiB" + +config SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_32MB + bool "32 MiB" + +config SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_16MB + bool "16 MiB" + +config SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_8MB + bool "8 MiB" + +config SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_4MB + bool "4 MiB" + +config SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_2MB + bool "2 MiB" + +config SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_0MB + bool "0 MiB" + +endchoice diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 072b2fd..bfa4818 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -447,7 +447,7 @@ if (!check_prm_features_enabled()) return 0; - if (!CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE)) + if (!CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE) return 0; msr = rdmsr(MSR_PRMRR_VALID_CONFIG); @@ -462,7 +462,7 @@ for (i = 8; i >= 0; i--) { valid_size = msr.lo & (1 << i); - if (valid_size && valid_size <= CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE) + if (valid_size && valid_size <= CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE) break; else if (i == 0) valid_size = 0; @@ -470,7 +470,7 @@ if (!valid_size) { printk(BIOS_WARNING, "Unsupported PRMRR size of %i MiB, check your config!\n", - CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE); + CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE); return 0; } diff --git a/src/soc/intel/common/block/sgx/Kconfig b/src/soc/intel/common/block/sgx/Kconfig index d9f941d..6d636ad 100644 --- a/src/soc/intel/common/block/sgx/Kconfig +++ b/src/soc/intel/common/block/sgx/Kconfig @@ -21,45 +21,7 @@ used by applications to set aside private regions (so-called Secure Enclaves) of code and data. - SGX will only be enabled when supported by the CPU! - -config SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE - int - depends on SOC_INTEL_COMMON_BLOCK_SGX_ENABLE - default 256 if SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_MAX - default 256 if SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_256MB - default 128 if SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_128MB - default 64 if SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_64MB - default 32 if SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_32MB - -choice - prompt "PRMRR size" - depends on SOC_INTEL_COMMON_BLOCK_SGX_ENABLE - default SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_MAX if SOC_INTEL_COMMON_BLOCK_SGX_ENABLE - help - PRMRR (Protected Memory Range) is the space in RAM that is used to provide a protected - memory area (e.g. for the Intel SGX Secure Enclaves). The memory region is accessible - only by the processor itself to protect the data from unauthorized access. - - This option selects the maximum size that gets reserved. Depending on the SoC a lower, - compatible value may be chosen at runtime as not all values are supported on all - families. - -config SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_MAX - bool "Maximum" - -config SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_256MB - bool "256 MiB" - -config SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_128MB - bool "128 MiB" - -config SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_64MB - bool "64 MiB" - -config SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_32MB - bool "32 MiB" - -endchoice + SGX will only be enabled when supported by the CPU! Configure PRMRR size using + SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE config option. endif -- To view, visit https://review.coreboot.org/c/coreboot/+/70819 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cd49a87be0293530705802fd9b830201a5863c2 Gerrit-Change-Number: 70819 Gerrit-PatchSet: 24 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Will Kim <norwayforest92(a)gmail.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/intel/common: Untie PRMRR from SGX
by Sridhar Siricilla (Code Review) 08 Jan '23

08 Jan '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Pratikkumar V Prajapati. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70819 ) Change subject: soc/intel/common: Untie PRMRR from SGX ...................................................................... Patch Set 23: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/70819 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cd49a87be0293530705802fd9b830201a5863c2 Gerrit-Change-Number: 70819 Gerrit-PatchSet: 23 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Will Kim <norwayforest92(a)gmail.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Sun, 08 Jan 2023 19:36:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit January 2023