coreboot-gerrit August 2022

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Change in coreboot[master]: [UNTESTED] intel/stm: Place resource list right below MSEG
by Nico Huber (Code Review) 10 Jun '23

10 Jun '23

Hello Kyösti Mälkki, Aaron Durbin, Arthur Heymans, cedarhouse1(a)comcast.net, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38765 to review the following change. Change subject: [UNTESTED] intel/stm: Place resource list right below MSEG ...................................................................... [UNTESTED] intel/stm: Place resource list right below MSEG Can we do this? what do I miss? Change-Id: I9c5970433a3851b5c9662c8870efaf2943498d27 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/cpu/x86/smm/smm_module_loader.c M src/security/intel/stm/StmPlatformSmm.c 2 files changed, 8 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/38765/1 diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 81020a4..2ef11340 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -315,13 +315,13 @@ /* The SMM module is placed within the provided region in the following * manner: * +-----------------+ <- smram + size - * | stacks | - * +-----------------+ <- smram + size - total_stack_size - * | fxsave area | - * +-----------------+ <- smram + size - total_stack_size - fxsave_size * | BIOS resource | * | list (STM) | - * +-----------------+ <- .. - CONFIG_BIOS_RESOURCE_LIST_SIZE + * +-----------------+ <- smram + size - CONFIG_BIOS_RESOURCE_LIST_SIZE + * | stacks | + * +-----------------+ <- .. - total_stack_size + * | fxsave area | + * +-----------------+ <- .. - total_stack_size - fxsave_size * | ... | * +-----------------+ <- smram + handler_size + SMM_DEFAULT_SIZE * | handler | @@ -362,11 +362,10 @@ /* Stacks start at the top of the region. */ base = smram; + base += size; if (CONFIG(STM)) - base += size - CONFIG_MSEG_SIZE; // take out the mseg - else - base += size; + base -= CONFIG_MSEG_SIZE + CONFIG_BIOS_RESOURCE_LIST_SIZE; params->stack_top = base; @@ -396,11 +395,6 @@ /* Does the required amount of memory exceed the SMRAM region size? */ total_size = total_stack_size + handler_size; total_size += fxsave_size + SMM_DEFAULT_SIZE; - - // account for the bios resource list - if (CONFIG(STM)) - total_size += CONFIG_BIOS_RESOURCE_LIST_SIZE; - if (total_size > size) return -1; diff --git a/src/security/intel/stm/StmPlatformSmm.c b/src/security/intel/stm/StmPlatformSmm.c index d7064b0..eb69301 100644 --- a/src/security/intel/stm/StmPlatformSmm.c +++ b/src/security/intel/stm/StmPlatformSmm.c @@ -166,12 +166,7 @@ // need to create the BIOS resource list once // first calculate the location in SMRAM - addr_calc = (mseg - (CONFIG_SMM_MODULE_STACK_SIZE * num_cpus)); - - if (CONFIG(SSE)) - addr_calc -= FXSAVE_SIZE * num_cpus; - - addr_calc -= CONFIG_BIOS_RESOURCE_LIST_SIZE; + addr_calc = mseg - CONFIG_BIOS_RESOURCE_LIST_SIZE; stm_resource_heap = (uint8_t *) addr_calc; printk(BIOS_DEBUG, "STM: stm_resource_heap located at %p\n", stm_resource_heap); -- To view, visit https://review.coreboot.org/c/coreboot/+/38765 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c5970433a3851b5c9662c8870efaf2943498d27 Gerrit-Change-Number: 38765 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: cedarhouse1(a)comcast.net Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/amd/{pi,agesa}/hudson/smbus_spd.c: use coreboot code style and calls
by Michał Żygowski (Code Review) 10 Jun '23

10 Jun '23

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38163 ) Change subject: sb/amd/{pi,agesa}/hudson/smbus_spd.c: use coreboot code style and calls ...................................................................... sb/amd/{pi,agesa}/hudson/smbus_spd.c: use coreboot code style and calls Use code comments in the coreboot style and replace outb/inb.rdtsc calls to use coreboot provided functions. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I40919df7d6dfbadd09800c8e689382483ffaca14 --- M src/southbridge/amd/agesa/hudson/smbus_spd.c M src/southbridge/amd/pi/hudson/smbus_spd.c 2 files changed, 118 insertions(+), 99 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/38163/1 diff --git a/src/southbridge/amd/agesa/hudson/smbus_spd.c b/src/southbridge/amd/agesa/hudson/smbus_spd.c index 9ddae38..ac52887 100644 --- a/src/southbridge/amd/agesa/hudson/smbus_spd.c +++ b/src/southbridge/amd/agesa/hudson/smbus_spd.c @@ -14,89 +14,98 @@ */ #include <amdblocks/acpimmio.h> +#include <arch/io.h> +#include <cpu/x86/tsc.h> #include <device/pci_def.h> #include <device/device.h> #include <console/console.h> -/* warning: Porting.h includes an open #pragma pack(1) */ -#include <Porting.h> #include <AGESA.h> -#include <amdlib.h> #include <northbridge/amd/agesa/dimmSpd.h> -/*----------------------------------------------------------------------------- - * - * readSmbusByteData - read a single SPD byte from any offset - */ - -static int readSmbusByteData (int iobase, int address, char *buffer, int offset) +/* readSmbusByteData - read a single SPD byte from any offset */ +static int readSmbusByteData(uint16_t iobase, int address, char *buffer, + int offset) { unsigned int status; - UINT64 limit; + unsigned long long limit; - address |= 1; // set read bit + address |= 1; /* set read bit */ + outb(0xff, iobase); /* clear error status */ + outb(0x1f, iobase + 1); /* clear error status */ + outb(offset, iobase + 3); /* offset in eeprom */ + outb(address, iobase + 4); /* slave address and read bit */ + outb(0x48, iobase + 2); /* read byte command */ - __outbyte (iobase + 0, 0xFF); // clear error status - __outbyte (iobase + 1, 0x1F); // clear error status - __outbyte (iobase + 3, offset); // offset in eeprom - __outbyte (iobase + 4, address); // slave address and read bit - __outbyte (iobase + 2, 0x48); // read byte command - - // time limit to avoid hanging for unexpected error status (should never happen) - limit = __rdtsc () + 2000000000 / 10; + /* + * time limit to avoid hanging for unexpected error status + * (should never happen) + */ + limit = rdtscll() + 2000000000 / 10; for (;;) { - status = __inbyte (iobase); - if (__rdtsc () > limit) break; - if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((status & 1) == 1) continue; // HostBusy set, keep waiting + status = inb(iobase); + if (rdtscll() > limit) + break; + /* SMBusInterrupt not set, keep waiting */ + if ((status & 2) == 0) + continue; + /* HostBusy set, keep waiting */ + if ((status & 1) == 1) + continue; break; } - buffer [0] = __inbyte (iobase + 5); - if (status == 2) status = 0; // check for done with no errors + buffer[0] = inb(iobase + 5); + /* check for done with no errors */ + if (status == 2) + status = 0; return status; } -/*----------------------------------------------------------------------------- - * +/* * readSmbusByte - read a single SPD byte from the default offset * this function is faster function readSmbusByteData */ - -static int readSmbusByte (int iobase, int address, char *buffer) +static int readSmbusByte(uint16_t iobase, int address, char *buffer) { unsigned int status; - UINT64 limit; + unsigned long long limit; - __outbyte (iobase + 0, 0xFF); // clear error status - __outbyte (iobase + 2, 0x44); // read command + outb(0xff, iobase + 0); /* clear error status */ + outb(0x44, iobase + 2); /* read command */ - // time limit to avoid hanging for unexpected error status - limit = __rdtsc () + 2000000000 / 10; + /* time limit to avoid hanging for unexpected error status*/ + limit = rdtscll() + 2000000000 / 10; for (;;) { - status = __inbyte (iobase); - if (__rdtsc () > limit) break; - if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((status & 1) == 1) continue; // HostBusy set, keep waiting + status = inb(iobase); + if (rdtscll() > limit) + break; + /* SMBusInterrupt not set, keep waiting */ + if ((status & 2) == 0) + continue; + /* HostBusy set, keep waiting */ + if ((status & 1) == 1) + continue; break; } - buffer [0] = __inbyte (iobase + 5); - if (status == 2) status = 0; // check for done with no errors + buffer[0] = inb(iobase + 5); + /* check for done with no errors */ + if (status == 2) + status = 0; return status; } -/*--------------------------------------------------------------------------- - * +/* * readspd - Read one or more SPD bytes from a DIMM. * Start with offset zero and read sequentially. * Optimization relies on autoincrement to avoid * sending offset for every byte. - * Reads 128 bytes in 7-8 ms at 400 KHz. + * Reads 128 bytes in 7-8 ms at 400 KHz. */ - -static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count) +static int readspd(uint16_t iobase, int SmbusSlaveAddress, char *buffer, + int count) { int index, error; @@ -127,15 +136,16 @@ return 0; } -static void setupFch (int ioBase) +static void setupFch(uint16_t ioBase) { pm_write16(0x2c, ioBase | 1); - __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz + /* set SMBus clock to 400 KHz */ + outb(66000000 / 400000 / 4, ioBase + 0x0e); } int hudson_readSpd(int spdAddress, char *buf, size_t len) { - int ioBase = 0xB00; + uint16_t ioBase = 0xb00; setupFch (ioBase); return readspd (ioBase, spdAddress, buf, len); } diff --git a/src/southbridge/amd/pi/hudson/smbus_spd.c b/src/southbridge/amd/pi/hudson/smbus_spd.c index 8523db5..ac52887 100644 --- a/src/southbridge/amd/pi/hudson/smbus_spd.c +++ b/src/southbridge/amd/pi/hudson/smbus_spd.c @@ -14,90 +14,98 @@ */ #include <amdblocks/acpimmio.h> -#include <console/console.h> +#include <arch/io.h> +#include <cpu/x86/tsc.h> #include <device/pci_def.h> #include <device/device.h> - -/* warning: Porting.h includes an open #pragma pack(1) */ -#include <Porting.h> +#include <console/console.h> #include <AGESA.h> -#include <amdlib.h> -#include <northbridge/amd/pi/dimmSpd.h> +#include <northbridge/amd/agesa/dimmSpd.h> -/*----------------------------------------------------------------------------- - * - * readSmbusByteData - read a single SPD byte from any offset - */ - -static int readSmbusByteData (int iobase, int address, char *buffer, int offset) +/* readSmbusByteData - read a single SPD byte from any offset */ +static int readSmbusByteData(uint16_t iobase, int address, char *buffer, + int offset) { unsigned int status; - UINT64 limit; + unsigned long long limit; - address |= 1; // set read bit + address |= 1; /* set read bit */ + outb(0xff, iobase); /* clear error status */ + outb(0x1f, iobase + 1); /* clear error status */ + outb(offset, iobase + 3); /* offset in eeprom */ + outb(address, iobase + 4); /* slave address and read bit */ + outb(0x48, iobase + 2); /* read byte command */ - __outbyte (iobase + 0, 0xFF); // clear error status - __outbyte (iobase + 1, 0x1F); // clear error status - __outbyte (iobase + 3, offset); // offset in eeprom - __outbyte (iobase + 4, address); // slave address and read bit - __outbyte (iobase + 2, 0x48); // read byte command - - // time limit to avoid hanging for unexpected error status (should never happen) - limit = __rdtsc () + 2000000000 / 10; + /* + * time limit to avoid hanging for unexpected error status + * (should never happen) + */ + limit = rdtscll() + 2000000000 / 10; for (;;) { - status = __inbyte (iobase); - if (__rdtsc () > limit) break; - if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((status & 1) == 1) continue; // HostBusy set, keep waiting + status = inb(iobase); + if (rdtscll() > limit) + break; + /* SMBusInterrupt not set, keep waiting */ + if ((status & 2) == 0) + continue; + /* HostBusy set, keep waiting */ + if ((status & 1) == 1) + continue; break; } - buffer [0] = __inbyte (iobase + 5); - if (status == 2) status = 0; // check for done with no errors + buffer[0] = inb(iobase + 5); + /* check for done with no errors */ + if (status == 2) + status = 0; return status; } -/*----------------------------------------------------------------------------- - * +/* * readSmbusByte - read a single SPD byte from the default offset * this function is faster function readSmbusByteData */ - -static int readSmbusByte (int iobase, int address, char *buffer) +static int readSmbusByte(uint16_t iobase, int address, char *buffer) { unsigned int status; - UINT64 limit; + unsigned long long limit; - __outbyte (iobase + 0, 0xFF); // clear error status - __outbyte (iobase + 2, 0x44); // read command + outb(0xff, iobase + 0); /* clear error status */ + outb(0x44, iobase + 2); /* read command */ - // time limit to avoid hanging for unexpected error status - limit = __rdtsc () + 2000000000 / 10; + /* time limit to avoid hanging for unexpected error status*/ + limit = rdtscll() + 2000000000 / 10; for (;;) { - status = __inbyte (iobase); - if (__rdtsc () > limit) break; - if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((status & 1) == 1) continue; // HostBusy set, keep waiting + status = inb(iobase); + if (rdtscll() > limit) + break; + /* SMBusInterrupt not set, keep waiting */ + if ((status & 2) == 0) + continue; + /* HostBusy set, keep waiting */ + if ((status & 1) == 1) + continue; break; } - buffer [0] = __inbyte (iobase + 5); - if (status == 2) status = 0; // check for done with no errors + buffer[0] = inb(iobase + 5); + /* check for done with no errors */ + if (status == 2) + status = 0; return status; } -/*--------------------------------------------------------------------------- - * +/* * readspd - Read one or more SPD bytes from a DIMM. * Start with offset zero and read sequentially. * Optimization relies on autoincrement to avoid * sending offset for every byte. - * Reads 128 bytes in 7-8 ms at 400 KHz. + * Reads 128 bytes in 7-8 ms at 400 KHz. */ - -static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count) +static int readspd(uint16_t iobase, int SmbusSlaveAddress, char *buffer, + int count) { int index, error; @@ -128,15 +136,16 @@ return 0; } -static void setupFch (int ioBase) +static void setupFch(uint16_t ioBase) { pm_write16(0x2c, ioBase | 1); - __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz + /* set SMBus clock to 400 KHz */ + outb(66000000 / 400000 / 4, ioBase + 0x0e); } int hudson_readSpd(int spdAddress, char *buf, size_t len) { - int ioBase = 0xB00; + uint16_t ioBase = 0xb00; setupFch (ioBase); return readspd (ioBase, spdAddress, buf, len); } -- To view, visit https://review.coreboot.org/c/coreboot/+/38163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40919df7d6dfbadd09800c8e689382483ffaca14 Gerrit-Change-Number: 38163 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: vendorcode/google: load sar config from CBFS first then VPD
by Marco Chen (Code Review) 10 Jun '23

10 Jun '23

Hello Marco Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/33661 to review the following change. Change subject: vendorcode/google: load sar config from CBFS first then VPD ...................................................................... vendorcode/google: load sar config from CBFS first then VPD SAR config provisioned in RO VPD can be done in the factory only. Once it is wrong, we can override the SAR config by updating FW RW which can carry new SAR config in CBFS. As a result, we should check CBFS first then VPD. Change-Id: I5aa6235fb7a6d0b2ed52893a42f7bd57806af6c1 Signed-off-by: Marco Chen <marcochen(a)chromium.org> --- M src/vendorcode/google/chromeos/sar.c 1 file changed, 23 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/33661/1 diff --git a/src/vendorcode/google/chromeos/sar.c b/src/vendorcode/google/chromeos/sar.c index bbcb211..a5a2c3b 100644 --- a/src/vendorcode/google/chromeos/sar.c +++ b/src/vendorcode/google/chromeos/sar.c @@ -82,36 +82,37 @@ sizeof(struct wifi_sar_delta_table); } - /* Try to read the SAR limit entry from VPD */ - if (!vpd_gets(wifi_sar_limit_key, wifi_sar_limit_str, - buffer_size, VPD_ANY)) { - printk(BIOS_ERR, "Error: Could not locate '%s' in VPD.\n", - wifi_sar_limit_key); - - if (!CONFIG(WIFI_SAR_CBFS)) - return -1; - + if (CONFIG(WIFI_SAR_CBFS)) { printk(BIOS_DEBUG, "Checking CBFS for default SAR values\n"); sar_cbfs_len = load_sar_file_from_cbfs( (void *) wifi_sar_limit_str, sar_expected_len); - if (sar_cbfs_len != sar_expected_len) { - printk(BIOS_ERR, "%s has bad len in CBFS\n", - WIFI_SAR_CBFS_FILENAME); - return -1; - } - } else { - /* VPD key "wifi_sar" found. strlen is checked with addition of - * 1 as we have created buffer size 1 char larger for the reason - * mentioned at start of this function itself */ - if (strlen(wifi_sar_limit_str) + 1 != sar_expected_len) { - printk(BIOS_ERR, "WIFI SAR key has bad len in VPD\n"); - return -1; - } + if (sar_cbfs_len == sar_expected_len) + goto done; + + printk(BIOS_ERR, "%s has bad len in CBFS\n", + WIFI_SAR_CBFS_FILENAME); } + /* Try to read the SAR limit entry from VPD */ + if (!vpd_gets(wifi_sar_limit_key, wifi_sar_limit_str, + buffer_size, VPD_ANY)) { + printk(BIOS_ERR, "Error: Could not locate '%s' in VPD.\n", + wifi_sar_limit_key); + return -1; + } + + /* VPD key "wifi_sar" found. strlen is checked with addition of + * 1 as we have created buffer size 1 char larger for the reason + * mentioned at start of this function itself */ + if (strlen(wifi_sar_limit_str) + 1 != sar_expected_len) { + printk(BIOS_ERR, "WIFI SAR key has bad len in VPD\n"); + return -1; + } + +done: /* Decode the heximal encoded string to binary values */ if (hexstrtobin(wifi_sar_limit_str, bin_buffer, bin_buff_adjusted_size) < bin_buff_adjusted_size) { -- To view, visit https://review.coreboot.org/c/coreboot/+/33661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5aa6235fb7a6d0b2ed52893a42f7bd57806af6c1 Gerrit-Change-Number: 33661 Gerrit-PatchSet: 1 Gerrit-Owner: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: [test only] USB2 DBC
by Kane Chen (Code Review) 10 Jun '23

10 Jun '23

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41691 ) Change subject: [test only] USB2 DBC ...................................................................... [test only] USB2 DBC Signed-off-by: Kane Chen <kane.chen(a)intel.com> Change-Id: I32eae987827b8a5dbe13bc91e97a330291289f7b --- M src/soc/intel/tigerlake/romstage/fsp_params.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/41691/1 diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index ede5059..19c73d2 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -198,6 +198,8 @@ soc_memory_init_params(m_cfg, config); mainboard_memory_init_params(mupd); + m_cfg->PlatformDebugConsent = 5; + } __weak void mainboard_memory_init_params(FSPM_UPD *mupd) -- To view, visit https://review.coreboot.org/c/coreboot/+/41691 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32eae987827b8a5dbe13bc91e97a330291289f7b Gerrit-Change-Number: 41691 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation: Add GbE and test results disabling it
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41290 ) Change subject: Documentation: Add GbE and test results disabling it ...................................................................... Documentation: Add GbE and test results disabling it The GbE region should not be disabled without further IFD modifications. Change-Id: Ie7e3104bcf9cf28b32f15ec4268d8a3fa35c0d9f Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- A Documentation/soc/intel/gbe.md M Documentation/soc/intel/index.md 2 files changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/41290/1 diff --git a/Documentation/soc/intel/gbe.md b/Documentation/soc/intel/gbe.md new file mode 100644 index 0000000..19094c6 --- /dev/null +++ b/Documentation/soc/intel/gbe.md @@ -0,0 +1,21 @@ +# Intel Flash descriptor GbE region + +The gigabit ethernet (GbE) region is an 8 KiB reserved area of the x86 boot +NOR SPI flash. The position withing the flash is specified by the IFD. + +The GbE regiong stores configuration data, for e.g. the MAC address +of the Intel onboard network interface card. Thus if the Intel onboard +network card isn't used by the mainboard, there's no GbE region present. + +The GbE region is named `gbe` in flashrom and ifdtool. + +# Removing the GbE + +Removing the GbE (marking the region as unused in the IFD) on a platform +that has the onboard NIC enabled in fuses results in a no boot. + +# Clearing the GbE region + +Overwriting the GbE region allows to boot and the GbE PCI device shows +up on GNU/Linux. The e1000e fails to load with 'error -3'. + diff --git a/Documentation/soc/intel/index.md b/Documentation/soc/intel/index.md index f30ff9a..2df1fe6 100644 --- a/Documentation/soc/intel/index.md +++ b/Documentation/soc/intel/index.md @@ -10,3 +10,7 @@ - [MP Initialization](mp_init/mp_init.md) - [Firmware Interface Table](fit.md) - [Apollolake](apollolake/index.md) + +## IFD + +- [GbE region](gbe.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/41290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7e3104bcf9cf28b32f15ec4268d8a3fa35c0d9f Gerrit-Change-Number: 41290 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Documentation: Explain DDR3 read training
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32334 Change subject: Documentation: Explain DDR3 read training ...................................................................... Documentation: Explain DDR3 read training Add lots of colorful graphics to explain DDR3 read training in detail, what is done inside MCH and what needs to be done on firmware level. Besides read training give a short explenation what DDR3 "FlyBy" is and compare it with DDR2 DIMMs. Besides the SVG all sources files are added. Change-Id: Ib477bd332984c397289404cfc33c65a2d4469257 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/getting_started/index.md A Documentation/getting_started/ram_initialization/16delay.dia A Documentation/getting_started/ram_initialization/16delay.svg A Documentation/getting_started/ram_initialization/64delay.dia A Documentation/getting_started/ram_initialization/64delay.svg A Documentation/getting_started/ram_initialization/DRAM_data_clock_lanes_skew.dia A Documentation/getting_started/ram_initialization/DRAM_data_clock_lanes_skew.svg A Documentation/getting_started/ram_initialization/ddr3_flyby.md A Documentation/getting_started/ram_initialization/ddr3_vs_ddr2.dia A Documentation/getting_started/ram_initialization/ddr3_vs_ddr2.svg A Documentation/getting_started/ram_initialization/index.md A Documentation/getting_started/ram_initialization/read_training.dia A Documentation/getting_started/ram_initialization/read_training.svg A Documentation/getting_started/ram_initialization/read_training2.dia A Documentation/getting_started/ram_initialization/read_training2.svg A Documentation/getting_started/ram_initialization/read_training3.dia A Documentation/getting_started/ram_initialization/read_training3.svg A Documentation/getting_started/ram_initialization/read_training_pattern.dia A Documentation/getting_started/ram_initialization/read_training_pattern.svg A Documentation/getting_started/ram_initialization/readtraining.md A Documentation/getting_started/ram_initialization/recv_blocks.dia A Documentation/getting_started/ram_initialization/recv_blocks.svg 22 files changed, 1,989 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/32334/1 diff --git a/Documentation/getting_started/index.md b/Documentation/getting_started/index.md index 52d873e..a265c5d 100644 --- a/Documentation/getting_started/index.md +++ b/Documentation/getting_started/index.md @@ -7,3 +7,4 @@ * [Gerrit Guidelines](gerrit_guidelines.md) * [Documentation License](license.md) * [Writing Documentation](writing_documentation.md) +* [DDR3 memory initialization](ram_initialization/index.md) diff --git a/Documentation/getting_started/ram_initialization/16delay.dia b/Documentation/getting_started/ram_initialization/16delay.dia new file mode 100644 index 0000000..d0e0095 --- /dev/null +++ b/Documentation/getting_started/ram_initialization/16delay.dia Binary files differ diff --git a/Documentation/getting_started/ram_initialization/16delay.svg b/Documentation/getting_started/ram_initialization/16delay.svg new file mode 100644 index 0000000..f661ddd --- /dev/null +++ b/Documentation/getting_started/ram_initialization/16delay.svg @@ -0,0 +1,177 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.0//EN" "http://www.w3.org/TR/2001/PR-SVG-20010719/DTD/svg10.dtd"> +<svg width="38cm" height="18cm" viewBox="366 265 754 351" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"> + <g> + <rect style="fill: #ffffff" x="367.719" y="266.052" width="751.775" height="348.316"/> + <rect style="fill: none; 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As every DIMM only needs to terminate the line once at end of PCB, +the DC resistance is much lower as on DDR2 "tree" routing topology, which did +terminate on every IC. + +The disadvantage of "fly-by" is the more complex memory training that needs to +be done to find the DATA lane skew. + +After the skew has been measured, the DATA lanes needs to be delayed by the +memory controller, to make sure all signals are still synchronous to the CLK, +as seen be the memory controller (on READ) or the DRAM (on WRITE). + +![][flyby] + +[flyby]: ddr3_vs_ddr2.svg + +```eval_rst ++---------------------------+------------+----------------+ +| Feature | DDR2 | DDR3 | ++===========================+============+================+ +| Frequency | 200-533 | 400-800 | ++---------------------------+------------+----------------+ +| Routing | complex | easy | ++---------------------------+------------+----------------+ +| Termination DC resistance | very high | low | ++---------------------------+------------+----------------+ +| Memory training | easy | complex | ++---------------------------+------------+----------------+ +``` + diff --git a/Documentation/getting_started/ram_initialization/ddr3_vs_ddr2.dia b/Documentation/getting_started/ram_initialization/ddr3_vs_ddr2.dia new file mode 100644 index 0000000..e4b4d09 --- /dev/null +++ b/Documentation/getting_started/ram_initialization/ddr3_vs_ddr2.dia Binary files differ diff --git a/Documentation/getting_started/ram_initialization/ddr3_vs_ddr2.svg b/Documentation/getting_started/ram_initialization/ddr3_vs_ddr2.svg new file mode 100644 index 0000000..0b8db34 --- /dev/null +++ b/Documentation/getting_started/ram_initialization/ddr3_vs_ddr2.svg @@ -0,0 +1,298 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.0//EN" "http://www.w3.org/TR/2001/PR-SVG-20010719/DTD/svg10.dtd"> +<svg width="17cm" height="10cm" viewBox="507 221 325 192" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"> + <g> + <rect style="fill: #ffffff" x="508.366" y="221.748" width="323.85" height="190.069"/> + <rect style="fill: none; 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It is usually done by firmware. +As soon as the skew is known, the DATA lanes can be individually delayed +by a constant rate to synchronize the DATA arriving at the MCH. + +For read training the DIMM is placed into a special mode where it outputs +a known pattern. The pattern looks like this: + +![][pat] + +[pat]: read_training_pattern.svg + +Due to the different skew of the lanes, the data arrives at different times +on the MCH. It's no longer synchronous to the CLK or other DATA lanes: + +![][read1] + +[read1]: read_training.svg + +The MCH must delay the signals to synchronize them again. + +### Delay units +The MCH is able to delay all lanes individually or at once. The delay +circuit inside the MCH consists of a *phase delay unit* and *CLK delay units*. +The *phase delay unit* delays by a fraction of the CLK, while the +*CLK delay unit* delays in multiple of the CLK. + +They can be configured by firmware using registers inside the MCH. + +#### Phase delay +The phase delay unit might look like this: + +![][delay64] + +[delay64]: 64delay.svg + +The phase delay can be adjusted by software by writing a register that selects +the MUX input. In this example the signal can be shifted by 64 1/64 CLKs. + +Applied to the DQS as seen on READ command, the signal can be delayed to be synchronous +to the CLK as seen by the MCH: + +![][read2] + +[read2]: read_training2.svg + + +#### CLK delay +The CLK delay unit might look like this: + +![][delay16] + +[delay16]: 16delay.svg + +The CLK delay can be adjusted by software by writing a register that selects +the MUX input. In this example the signal can be delayed by 16 CLKs. + +Applied to the DQS as seen on READ command, the signal can be delayed to be synchronous +to the other DQS lanes: + +![][read3] + +[read3]: read_training3.svg + +#### Combined delay + +Both units are connected in row for each DQS/DATA lane: + +![][blocks] + +[blocks]: recv_blocks.svg + +For each lane (here 8 + 1), there's a 10bit register allowing to adjust the +delay. + +## Finding the right delay + +Assuming a 1/64th phase delay unit, the firmware guesses the initial skew and then places the phase in the alternating data pattern. It then adjest the phase and measures the sampled value. + +The following algorithm is used: + +1. Samples all lanes using 128 (64 + 1 full CLK) different phase delays. It allows to find the rising edge in the pattern. +2. In the next step the phase delay is reduced by 32 (1/2 CLK) to position the sample in a logic "low". +3. For each lane the delay is reduced by 128 (2 CLKs) until a logic "high" is sampled. That the preamble of the pattern. +4. As next step the delay is increased by 96 (1.5 CLKs) to position at the first falling edge. +5. Multiple samples in the range -0.5 to 0.5 CLKS are done to find the exact point of falling edge. + +Read training has now found the exact delay for each lane and stores the values for the next boot. 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Change in ...coreboot[master]: arch/x86/mmio: Avoid pointer aliasing in write8()
by Nico Huber (Code Review) 10 Jun '23

10 Jun '23

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31945 Change subject: arch/x86/mmio: Avoid pointer aliasing in write8() ...................................................................... arch/x86/mmio: Avoid pointer aliasing in write8() Don't literally dereference a pointer to `char`. Use array indexing instead to avoid aliasing rules. Otherwise, the compiler might treat any memory as clobbered. Change-Id: I441c27e789ad92a8125c92837244474a26250c8a Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/arch/x86/include/arch/mmio.h 1 file changed, 9 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/31945/1 diff --git a/src/arch/x86/include/arch/mmio.h b/src/arch/x86/include/arch/mmio.h index f271a97..790b699 100644 --- a/src/arch/x86/include/arch/mmio.h +++ b/src/arch/x86/include/arch/mmio.h @@ -45,7 +45,15 @@ static __always_inline void write8(volatile void *addr, uint8_t value) { - *((volatile uint8_t *)(addr)) = value; + /* + * Don't literally dereference a pointer to `char`. Use array + * indexing instead to avoid aliasing rules. Otherwise, the + * compiler might treat any memory as clobbered. + */ + volatile struct { + uint8_t reg[1]; + } *const ref = addr; + ref->reg[0] = value; } static __always_inline void write16(volatile void *addr, -- To view, visit https://review.coreboot.org/c/coreboot/+/31945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I441c27e789ad92a8125c92837244474a26250c8a Gerrit-Change-Number: 31945 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: Doc/mb/lenovo/montevina_series: Describe GbE generating
by Evgeny Zinoviev (Code Review) 10 Jun '23

10 Jun '23

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39761 ) Change subject: Doc/mb/lenovo/montevina_series: Describe GbE generating ...................................................................... Doc/mb/lenovo/montevina_series: Describe GbE generating Instead of using the gbe region extracted from stock dump, one may want to generate the new one. util/bincfg can do that, but it's not documented anywhere yet. This patch describes how to do that along with changing the MAC address. Change-Id: I9318514b125b53f8ad76ad99755690ec6f681441 Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M Documentation/mainboard/lenovo/montevina_series.md 1 file changed, 30 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/39761/1 diff --git a/Documentation/mainboard/lenovo/montevina_series.md b/Documentation/mainboard/lenovo/montevina_series.md index 62e8796..39dee2f 100644 --- a/Documentation/mainboard/lenovo/montevina_series.md +++ b/Documentation/mainboard/lenovo/montevina_series.md @@ -33,6 +33,9 @@ $ ifdtool -x backup.rom ``` +Note that you can also [generate new GbE region](#generating-gbe-region) and use +it instead. + Now you need to patch the flash descriptor. You can either [modify the one from your backup with **ifdtool**](#modifying-flash-descriptor-using-ifdtool), or [generate a completely new one with **bincfg**](#creating-a-new-flash-descriptor-using-bincfg). @@ -122,6 +125,7 @@ (/path/to/flashregion_0_flashdescriptor.bin) Path and filename of the descriptor.bin file [*] Add gigabit ethernet configuration + # Note: if you used bincfg, specify path to generated util/bincfg/flashregion_3_gbe.bin (/path/to/flashregion_3_gbe.bin) Path to gigabit ethernet configuration ``` @@ -136,6 +140,32 @@ # flashrom -p YOUR_PROGRAMMER -w coreboot.rom --ifd -i bios ``` +## Generating GbE region + +GbE region contains configuration data for Intel integrated Gigabit Ethernet. +You can generate new GbE Region by using **bincfg**. To do that, go to +`util/bincfg`. + +It's good idea to set MAC address first, so open then `gbe-ich9m.set` file and +change values of `macaddress0` .. `macaddress5` fields. For example, if you want +to set MAC address to `00:01:02:03:04:05`: + +``` + "macaddress0" = 0x0, + "macaddress1" = 0x1, + "macaddress2" = 0x2, + "macaddress3" = 0x3, + "macaddress4" = 0x4, + "macaddress5" = 0x5 +``` + +Then run: +```console +$ make gen-gbe-ich9m +``` + +The new GbE region will be saved to `flashregion_3_gbe.bin`. + ## Flash layout The flash layouts of the OEM firmware are as follows: -- To view, visit https://review.coreboot.org/c/coreboot/+/39761 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9318514b125b53f8ad76ad99755690ec6f681441 Gerrit-Change-Number: 39761 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newchange

5 9

Change in coreboot[master]: config: Build QEMU i440fx with undefined behavior sanitizer
by Paul Menzel (Code Review) 10 Jun '23

10 Jun '23

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41699 ) Change subject: config: Build QEMU i440fx with undefined behavior sanitizer ...................................................................... config: Build QEMU i440fx with undefined behavior sanitizer Change-Id: I483f7d7e26fe06514d3a4c823e5a598ae3b682a0 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- A configs/config.emulation_qemu_x86_i440fx_ubsan 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/41699/1 diff --git a/configs/config.emulation_qemu_x86_i440fx_ubsan b/configs/config.emulation_qemu_x86_i440fx_ubsan new file mode 100644 index 0000000..ceae016 --- /dev/null +++ b/configs/config.emulation_qemu_x86_i440fx_ubsan @@ -0,0 +1 @@ +CONFIG_UBSAN=y -- To view, visit https://review.coreboot.org/c/coreboot/+/41699 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I483f7d7e26fe06514d3a4c823e5a598ae3b682a0 Gerrit-Change-Number: 41699 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: Add Kconfig option for ACPI S3 support
by Paul Menzel (Code Review) 10 Jun '23

10 Jun '23

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41877 ) Change subject: Add Kconfig option for ACPI S3 support ...................................................................... Add Kconfig option for ACPI S3 support Being able to disable ACPI S3 saves 150 ms on the ASRock E350M1. Change-Id: Ie25c6ab5cd927287f0e2ff00cce042a95f7d377c Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/Kconfig M src/lib/hardwaremain.c 2 files changed, 20 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/41877/1 diff --git a/src/Kconfig b/src/Kconfig index 2a2a144..0e89eb6 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -135,6 +135,22 @@ every boot. Use this if you want the NVRAM configuration to never be modified from its default values. +config DO_ACPI_RESUME + bool "Enable ACPI S3 resume" + default y + depends on HAVE_ACPI_RESUME + help + Adds S3 to the available sleepstates + + Enabling ACPI S3 resume support delays the boot-up on certain boards. + For example, the delay it 200 ms on the AMD AGESA board ASRock E350M1. + + If you do not need ACPI S3 resume support, select this option. + + (And why should you, with coreboot, an SSD and an optimized OS, you + boot as fast as with resuming from ACPI S3, and have less code paths + to maintain and test.) + config COMPRESS_RAMSTAGE bool "Compress ramstage with LZMA" depends on HAVE_RAMSTAGE diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 935393e..20b7c25 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -19,7 +19,7 @@ #include <stdlib.h> #include <boot/tables.h> #include <program_loading.h> -#if CONFIG(HAVE_ACPI_RESUME) +#if CONFIG(DO_ACPI_RESUME) #include <acpi/acpi.h> #endif #include <timer.h> @@ -151,7 +151,7 @@ static boot_state_t bs_os_resume_check(void *arg) { -#if CONFIG(HAVE_ACPI_RESUME) +#if CONFIG(DO_ACPI_RESUME) void *wake_vector; wake_vector = acpi_find_wakeup_vector(); @@ -168,7 +168,7 @@ static boot_state_t bs_os_resume(void *wake_vector) { -#if CONFIG(HAVE_ACPI_RESUME) +#if CONFIG(DO_ACPI_RESUME) arch_bootstate_coreboot_exit(); acpi_resume(wake_vector); #endif @@ -445,7 +445,7 @@ post_code(POST_ENTRY_RAMSTAGE); /* Handoff sleep type from romstage. */ -#if CONFIG(HAVE_ACPI_RESUME) +#if CONFIG(DO_ACPI_RESUME) acpi_is_wakeup(); #endif threads_initialize(); -- To view, visit https://review.coreboot.org/c/coreboot/+/41877 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie25c6ab5cd927287f0e2ff00cce042a95f7d377c Gerrit-Change-Number: 41877 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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