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Change in coreboot[master]: commonlib/elog: add event log parsing tables
by Michał Żygowski (Code Review) 07 Aug '23

07 Aug '23

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40343 ) Change subject: commonlib/elog: add event log parsing tables ...................................................................... commonlib/elog: add event log parsing tables Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I7b8f92f4aaf0e91244fcdec5a4da0ff843bbacda --- A src/commonlib/include/commonlib/elog.h 1 file changed, 402 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/40343/1 diff --git a/src/commonlib/include/commonlib/elog.h b/src/commonlib/include/commonlib/elog.h new file mode 100644 index 0000000..9034579 --- /dev/null +++ b/src/commonlib/include/commonlib/elog.h @@ -0,0 +1,402 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef ELOG_H_ +#define ELOG_H_ + +#include <stdint.h> + +#define MAX_EVENT_SIZE 0x7F + +/* End of log */ +#define ELOG_TYPE_EOL 0xFF + +struct event_header { + uint8_t type; + uint8_t length; + uint8_t year; + uint8_t month; + uint8_t day; + uint8_t hour; + uint8_t minute; + uint8_t second; +} __packed; + +/* + * Standard SMBIOS event log types below 0x80 + */ +#define ELOG_TYPE_UNDEFINED_EVENT 0x00 +#define ELOG_TYPE_SINGLE_BIT_ECC_MEM_ERR 0x01 +#define ELOG_TYPE_MULTI_BIT_ECC_MEM_ERR 0x02 +#define ELOG_TYPE_MEM_PARITY_ERR 0x03 +#define ELOG_TYPE_BUS_TIMEOUT 0x04 +#define ELOG_TYPE_IO_CHECK 0x05 +#define ELOG_TYPE_SW_NMI 0x06 +#define ELOG_TYPE_POST_MEM_RESIZE 0x07 +#define ELOG_TYPE_POST_ERR 0x08 +#define ELOG_TYPE_PCI_PERR 0x09 +#define ELOG_TYPE_PCI_SERR 0x0A +#define ELOG_TYPE_CPU_FAIL 0x0B +#define ELOG_TYPE_EISA_TIMEOUT 0x0C +#define ELOG_TYPE_CORRECTABLE_MEMLOG_DIS 0x0D +#define ELOG_TYPE_LOG_DISABLED 0x0E +#define ELOG_TYPE_UNDEFINED_EVENT2 0x0F +#define ELOG_TYPE_SYS_LIMIT_EXCEED 0x10 +#define ELOG_TYPE_ASYNC_HW_TIMER_EXPIRED 0x11 +#define ELOG_TYPE_SYS_CONFIG_INFO 0x12 +#define ELOG_TYPE_HDD_INFO 0x13 +#define ELOG_TYPE_SYS_RECONFIG 0x14 +#define ELOG_TYPE_CPU_ERROR 0x15 +#define ELOG_TYPE_LOG_CLEAR 0x16 +#define ELOG_TYPE_BOOT 0x17 + +/* + * Extended defined OEM event types start at 0x80 + */ + +/* OS/kernel events */ +#define ELOG_TYPE_OS_EVENT 0x81 + +/* Last event from coreboot */ +#define ELOG_TYPE_OS_BOOT 0x90 + +/* Embedded controller event */ +#define ELOG_TYPE_EC_EVENT 0x91 +#define EC_EVENT_LID_CLOSED 0x01 +#define EC_EVENT_LID_OPEN 0x02 +#define EC_EVENT_POWER_BUTTON 0x03 +#define EC_EVENT_AC_CONNECTED 0x04 +#define EC_EVENT_AC_DISCONNECTED 0x05 +#define EC_EVENT_BATTERY_LOW 0x06 +#define EC_EVENT_BATTERY_CRITICAL 0x07 +#define EC_EVENT_BATTERY 0x08 +#define EC_EVENT_THERMAL_THRESHOLD 0x09 +#define EC_EVENT_DEVICE_EVENT 0x0a +#define EC_EVENT_THERMAL 0x0b +#define EC_EVENT_USB_CHARGER 0x0c +#define EC_EVENT_KEY_PRESSED 0x0d +#define EC_EVENT_INTERFACE_READY 0x0e +#define EC_EVENT_KEYBOARD_RECOVERY 0x0f +#define EC_EVENT_THERMAL_SHUTDOWN 0x10 +#define EC_EVENT_BATTERY_SHUTDOWN 0x11 +#define EC_EVENT_FAN_ERROR 0x12 +#define EC_EVENT_THROTTLE_STOP 0x13 +#define EC_EVENT_HANG_DETECT 0x14 +#define EC_EVENT_HANG_REBOOT 0x15 +#define EC_EVENT_PD_MCU 0x16 +#define EC_EVENT_BATTERY_STATUS 0x17 +#define EC_EVENT_PANIC 0x18 +#define EC_EVENT_KEYBOARD_FASTBOOT 0x19 +#define EC_EVENT_RTC 0x1a +#define EC_EVENT_MKBP 0x1b +#define EC_EVENT_USB_MUX 0x1c +#define EC_EVENT_MODE_CHANGE 0x1d +#define EC_EVENT_KEYBOARD_RECOVERY_HWREINIT 0x1e +#define EC_EVENT_EXTENDED 0x1f + +/* Power */ +#define ELOG_TYPE_POWER_FAIL 0x92 +#define ELOG_TYPE_SUS_POWER_FAIL 0x93 +#define ELOG_TYPE_PWROK_FAIL 0x94 +#define ELOG_TYPE_SYS_PWROK_FAIL 0x95 +#define ELOG_TYPE_POWER_ON 0x96 +#define ELOG_TYPE_POWER_BUTTON 0x97 +#define ELOG_TYPE_POWER_BUTTON_OVERRIDE 0x98 + +/* Reset */ +#define ELOG_TYPE_RESET_BUTTON 0x99 +#define ELOG_TYPE_SYSTEM_RESET 0x9a +#define ELOG_TYPE_RTC_RESET 0x9b +#define ELOG_TYPE_TCO_RESET 0x9c + +/* Sleep/Wake */ +#define ELOG_TYPE_ACPI_ENTER 0x9d +/* + * Deep Sx wake variant is provided below - 0xad + * Sleep/"wake pending" event log provided below - 0xb1 - 0x01/0x02 + */ + +#define ELOG_TYPE_ACPI_WAKE 0x9e +#define ELOG_TYPE_WAKE_SOURCE 0x9f +#define ELOG_WAKE_SOURCE_PCIE 0x00 +#define ELOG_WAKE_SOURCE_PME 0x01 +#define ELOG_WAKE_SOURCE_PME_INTERNAL 0x02 +#define ELOG_WAKE_SOURCE_RTC 0x03 +#define ELOG_WAKE_SOURCE_GPIO 0x04 +#define ELOG_WAKE_SOURCE_SMBUS 0x05 +#define ELOG_WAKE_SOURCE_PWRBTN 0x06 +#define ELOG_WAKE_SOURCE_PME_HDA 0x07 +#define ELOG_WAKE_SOURCE_PME_GBE 0x08 +#define ELOG_WAKE_SOURCE_PME_EMMC 0x09 +#define ELOG_WAKE_SOURCE_PME_SDCARD 0x0a +#define ELOG_WAKE_SOURCE_PME_PCIE1 0x0b +#define ELOG_WAKE_SOURCE_PME_PCIE2 0x0c +#define ELOG_WAKE_SOURCE_PME_PCIE3 0x0d +#define ELOG_WAKE_SOURCE_PME_PCIE4 0x0e +#define ELOG_WAKE_SOURCE_PME_PCIE5 0x0f +#define ELOG_WAKE_SOURCE_PME_PCIE6 0x10 +#define ELOG_WAKE_SOURCE_PME_PCIE7 0x11 +#define ELOG_WAKE_SOURCE_PME_PCIE8 0x12 +#define ELOG_WAKE_SOURCE_PME_PCIE9 0x13 +#define ELOG_WAKE_SOURCE_PME_PCIE10 0x14 +#define ELOG_WAKE_SOURCE_PME_PCIE11 0x15 +#define ELOG_WAKE_SOURCE_PME_PCIE12 0x16 +#define ELOG_WAKE_SOURCE_PME_SATA 0x17 +#define ELOG_WAKE_SOURCE_PME_CSE 0x18 +#define ELOG_WAKE_SOURCE_PME_CSE2 0x19 +#define ELOG_WAKE_SOURCE_PME_CSE3 0x1a +#define ELOG_WAKE_SOURCE_PME_XHCI 0x1b +#define ELOG_WAKE_SOURCE_PME_XDCI 0x1c +#define ELOG_WAKE_SOURCE_PME_XHCI_USB_2 0x1d +#define ELOG_WAKE_SOURCE_PME_XHCI_USB_3 0x1e +#define ELOG_WAKE_SOURCE_PME_WIFI 0x1f + +struct elog_event_data_wake { + uint8_t source; + uint32_t instance; +} __packed; + +/* Chrome OS related events */ +#define ELOG_TYPE_CROS_DEVELOPER_MODE 0xa0 +#define ELOG_TYPE_CROS_RECOVERY_MODE 0xa1 +#define ELOG_CROS_RECOVERY_MODE_BUTTON 0x02 + +/* Management Engine Events */ +#define ELOG_TYPE_MANAGEMENT_ENGINE 0xa2 +#define ELOG_TYPE_MANAGEMENT_ENGINE_EXT 0xa4 + +struct elog_event_data_me_extended { + uint8_t current_working_state; + uint8_t operation_state; + uint8_t operation_mode; + uint8_t error_code; + uint8_t progress_code; + uint8_t current_pmevent; + uint8_t current_state; +} __packed; + +/* Last post code from previous boot */ +#define ELOG_TYPE_LAST_POST_CODE 0xa3 +#define ELOG_TYPE_POST_EXTRA 0xa6 + +/* EC Shutdown Reason */ +#define ELOG_TYPE_EC_SHUTDOWN 0xa5 + +/* + * ARM/generic versions of sleep/wake - These came from another firmware + * apparently, but not all the firmware sources were updated so that the + * elog namespace was coherent. + */ +#define ELOG_TYPE_SLEEP 0xa7 +#define ELOG_TYPE_WAKE 0xa8 +#define ELOG_TYPE_FW_WAKE 0xa9 + +/* Memory Cache Update */ +#define ELOG_TYPE_MEM_CACHE_UPDATE 0xaa +#define ELOG_MEM_CACHE_UPDATE_SLOT_NORMAL 0 +#define ELOG_MEM_CACHE_UPDATE_SLOT_RECOVERY 1 +#define ELOG_MEM_CACHE_UPDATE_SLOT_VARIABLE 2 +#define ELOG_MEM_CACHE_UPDATE_STATUS_SUCCESS 0 +#define ELOG_MEM_CACHE_UPDATE_STATUS_FAIL 1 + +struct elog_event_mem_cache_update { + uint8_t slot; + uint8_t status; +} __packed; + +/* CPU Thermal Trip */ +#define ELOG_TYPE_THERM_TRIP 0xab + +/* Cr50 */ +#define ELOG_TYPE_CR50_UPDATE 0xac + +/* Deep Sx wake variant */ +#define ELOG_TYPE_ACPI_DEEP_WAKE 0xad + +/* EC Device Event */ +#define ELOG_TYPE_EC_DEVICE_EVENT 0xae +#define ELOG_EC_DEVICE_EVENT_TRACKPAD 0x01 +#define ELOG_EC_DEVICE_EVENT_DSP 0x02 +#define ELOG_EC_DEVICE_EVENT_WIFI 0x03 + +/* S0ix sleep/wake */ +#define ELOG_TYPE_S0IX_ENTER 0xaf +#define ELOG_TYPE_S0IX_EXIT 0xb0 + +/* Extended events */ +#define ELOG_TYPE_EXTENDED_EVENT 0xb1 +#define ELOG_SLEEP_PENDING_PM1_WAKE 0x01 +#define ELOG_SLEEP_PENDING_GPE0_WAKE 0x02 + +/* Cr50 reset to enable TPM */ +#define ELOG_TYPE_CR50_NEED_RESET 0xb2 + +/* Intruder detection */ +#define ELOG_TYPE_INTRUDER_DETECTION 0xb3 +#define ELOG_CASE_OPENED 0x01 +#define ELOG_CASE_CLOSED 0x02 + +struct elog_event_extended_event { + uint8_t event_type; + uint32_t event_complement; +} __packed; + +struct elog_event_name { + uint8_t event_type; + char *event_name; +}; + +static const struct elog_event_name elog_event_to_name[] = { + { ELOG_TYPE_UNDEFINED_EVENT, "UNDEFINED EVENT" }, + { ELOG_TYPE_SINGLE_BIT_ECC_MEM_ERR, "Single-Bit ECC memory error" }, + { ELOG_TYPE_MULTI_BIT_ECC_MEM_ERR, "Multi-Bit ECC memory error" }, + { ELOG_TYPE_MEM_PARITY_ERR, "Memory parity error" }, + { ELOG_TYPE_BUS_TIMEOUT, "Bus time-out" }, + { ELOG_TYPE_IO_CHECK, "IO channel check" }, + { ELOG_TYPE_SW_NMI, "Software NMI" }, + { ELOG_TYPE_POST_MEM_RESIZE, "Post memory resize" }, + { ELOG_TYPE_POST_ERR, "Post error" }, + { ELOG_TYPE_PCI_PERR, "PCI parity error" }, + { ELOG_TYPE_PCI_SERR, "PCI system error" }, + { ELOG_TYPE_CPU_FAIL, "CPU failure" }, + { ELOG_TYPE_EISA_TIMEOUT, "EISA FailSafe Timer time-out" }, + { ELOG_TYPE_CORRECTABLE_MEMLOG_DIS, "Correctable memory log disable" }, + { ELOG_TYPE_LOG_DISABLED, "Event log disabled for type" }, + { ELOG_TYPE_UNDEFINED_EVENT2, "UNDEFINED EVENT 2" }, + { ELOG_TYPE_SYS_LIMIT_EXCEED, "System limit exceeded" }, + { ELOG_TYPE_ASYNC_HW_TIMER_EXPIRED, "Asynchronous hardware timer expired and issued a system reset" }, + { ELOG_TYPE_SYS_CONFIG_INFO, "System configuration information" }, + { ELOG_TYPE_HDD_INFO, "Hard-disk information" }, + { ELOG_TYPE_SYS_RECONFIG, "System reconfigured" }, + { ELOG_TYPE_CPU_ERROR, "Uncorrectable CPU-complex error" }, + { ELOG_TYPE_LOG_CLEAR, "Log Area reset/cleared" }, + { ELOG_TYPE_BOOT, "System boot" }, + { ELOG_TYPE_OS_EVENT, "Operating system event" }, + { ELOG_TYPE_OS_BOOT, "Boot operating system" }, + { ELOG_TYPE_POWER_FAIL, "Power failure" }, + { ELOG_TYPE_SUS_POWER_FAIL, "Suspend power failure" }, + { ELOG_TYPE_PWROK_FAIL, "Power OK failure" }, + { ELOG_TYPE_SYS_PWROK_FAIL, "System power OK failure" }, + { ELOG_TYPE_POWER_ON, "Power on" }, + { ELOG_TYPE_POWER_BUTTON, "Power button pressed" }, + { ELOG_TYPE_POWER_BUTTON_OVERRIDE, "Power button override" }, + { ELOG_TYPE_RESET_BUTTON, "Reset button pressed" }, + { ELOG_TYPE_SYSTEM_RESET, "System reset" }, + { ELOG_TYPE_RTC_RESET, "Real Time Clock reset" }, + { ELOG_TYPE_TCO_RESET, "TCO timer reset" }, + { ELOG_TYPE_ACPI_ENTER, "Entered ACPI state" }, + { ELOG_TYPE_ACPI_WAKE, "ACPI wake event" }, + { ELOG_TYPE_WAKE_SOURCE, "ACPI wake source" }, + { ELOG_TYPE_CROS_DEVELOPER_MODE, "Entered ChromeOS developer mode" }, + { ELOG_TYPE_CROS_RECOVERY_MODE, "Entered ChromeOS recovery mode" }, + { ELOG_TYPE_MANAGEMENT_ENGINE, "Intel Management Engine event" }, + { ELOG_TYPE_MANAGEMENT_ENGINE_EXT, "Intel Management Engine extended event" }, + { ELOG_TYPE_LAST_POST_CODE, "Post code from last boot" }, + { ELOG_TYPE_POST_EXTRA, "Post code extra" }, + { ELOG_TYPE_EC_SHUTDOWN, "Embedded Controller shutdown" }, + { ELOG_TYPE_SLEEP, "Entered sleep mode", }, + { ELOG_TYPE_WAKE, "Wake event" }, + { ELOG_TYPE_FW_WAKE, "Firmware wake event" }, + { ELOG_TYPE_MEM_CACHE_UPDATE, "MRC cache update" }, + { ELOG_TYPE_THERM_TRIP, "Thermal trip occurred" }, + { ELOG_TYPE_CR50_UPDATE, "CR50 TPM update event" }, + { ELOG_TYPE_ACPI_DEEP_WAKE, "ACPI deep wake event" }, + { ELOG_TYPE_EC_DEVICE_EVENT, "Embedded controller device event" }, + { ELOG_TYPE_S0IX_ENTER, "Entered S0ix state" }, + { ELOG_TYPE_S0IX_EXIT, "Exited from S0ix state" }, + { ELOG_TYPE_EXTENDED_EVENT, "Extended event" }, + { ELOG_TYPE_CR50_NEED_RESET, "CR50 TPM configuration needs reset" }, + { ELOG_TYPE_INTRUDER_DETECTION, "Intrusion detection " } +}; + +static const struct elog_event_name elog_ec_event_to_name[] = { + { EC_EVENT_LID_CLOSED, "Lid closed" }, + { EC_EVENT_LID_OPEN, "Lid open" }, + { EC_EVENT_POWER_BUTTON, "Power button pressed" }, + { EC_EVENT_AC_CONNECTED, "AC power supply connected" }, + { EC_EVENT_AC_DISCONNECTED, "AC power supply disconnected" }, + { EC_EVENT_BATTERY_LOW, "Battery low" }, + { EC_EVENT_BATTERY_CRITICAL, "Battery critical" }, + { EC_EVENT_BATTERY, "Battery event" }, + { EC_EVENT_THERMAL_THRESHOLD, "Thermal threshold reached" }, + { EC_EVENT_DEVICE_EVENT, "Device event" }, + { EC_EVENT_THERMAL, "Thermal event" }, + { EC_EVENT_USB_CHARGER, "USB charger" }, + { EC_EVENT_KEY_PRESSED, "Key pressed" }, + { EC_EVENT_INTERFACE_READY, "Interface ready" }, + { EC_EVENT_KEYBOARD_RECOVERY, "Keyboard recovery" }, + { EC_EVENT_THERMAL_SHUTDOWN, "Thermal shutdown" }, + { EC_EVENT_BATTERY_SHUTDOWN, "Battery shutdown" }, + { EC_EVENT_FAN_ERROR, "Fan error" }, + { EC_EVENT_THROTTLE_STOP, "Throttling stopeed" }, + { EC_EVENT_HANG_DETECT, "Hang detected" }, + { EC_EVENT_HANG_REBOOT, "Reboot hang" }, + { EC_EVENT_PD_MCU, "PD processor" }, + { EC_EVENT_BATTERY_STATUS, "Battery status" }, + { EC_EVENT_PANIC, "Panic" }, + { EC_EVENT_KEYBOARD_FASTBOOT, "Keyboard fastboot" }, + { EC_EVENT_RTC, "Real Time Clock" }, + { EC_EVENT_MKBP, "Matrix Keyboard Protocol" }, + { EC_EVENT_USB_MUX, "USB multiplexer" }, + { EC_EVENT_MODE_CHANGE, "Mode change" }, + { EC_EVENT_KEYBOARD_RECOVERY_HWREINIT, "Keyboard recovery hardware reinitialization" }, + { EC_EVENT_EXTENDED, "Extended event" } +}; + +static const struct elog_event_name elog_wake_event_to_name[] = { + { ELOG_WAKE_SOURCE_PCIE, "PCI Express" }, + { ELOG_WAKE_SOURCE_PME, "PME" }, + { ELOG_WAKE_SOURCE_PME_INTERNAL, "Internal PME" }, + { ELOG_WAKE_SOURCE_RTC, "Real Time Clock" }, + { ELOG_WAKE_SOURCE_GPIO, "GPIO" }, + { ELOG_WAKE_SOURCE_SMBUS, "SMBus" }, + { ELOG_WAKE_SOURCE_PWRBTN, "Power Button" }, + { ELOG_WAKE_SOURCE_PME_HDA, "HD Audio PME" }, + { ELOG_WAKE_SOURCE_PME_GBE, "Gigabit Ethernet PME" }, + { ELOG_WAKE_SOURCE_PME_EMMC, "Embedded MMC PME" }, + { ELOG_WAKE_SOURCE_PME_SDCARD, "SD card PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE1, "PCI Express 1 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE2, "PCI Express 2 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE3, "PCI Express 3 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE4, "PCI Express 4 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE5, "PCI Express 5 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE6, "PCI Express 6 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE7, "PCI Express 7 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE8, "PCI Express 8 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE9, "PCI Express 9 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE10, "PCI Express 10 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE11, "PCI Express 11 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE12, "PCI Express 12 PME" }, + { ELOG_WAKE_SOURCE_PME_SATA, "SATA PME" }, + { ELOG_WAKE_SOURCE_PME_CSE, "CSE PME" }, + { ELOG_WAKE_SOURCE_PME_CSE2, "CSE 2 PME" }, + { ELOG_WAKE_SOURCE_PME_CSE3, "CSE 3 PME" }, + { ELOG_WAKE_SOURCE_PME_XHCI, "xHCI PME" }, + { ELOG_WAKE_SOURCE_PME_XDCI, "xDCI PME" }, + { ELOG_WAKE_SOURCE_PME_XHCI_USB_2, "xHCI USB2 PME" }, + { ELOG_WAKE_SOURCE_PME_XHCI_USB_3, "xHCI USB2 PME" }, + { ELOG_WAKE_SOURCE_PME_WIFI, "WiFi PME" } +}; + +static const struct elog_event_name elog_ec_device_event_to_name[] = { + { ELOG_EC_DEVICE_EVENT_TRACKPAD, "Trackpad" }, + { ELOG_EC_DEVICE_EVENT_DSP, "DSP" }, + { ELOG_EC_DEVICE_EVENT_WIFI, "WiFi" } +}; + +static const struct elog_event_name mrc_upd_slots[] = { + { ELOG_MEM_CACHE_UPDATE_SLOT_NORMAL, "NORMAL" }, + { ELOG_MEM_CACHE_UPDATE_SLOT_RECOVERY, "RECOVERY" }, + { ELOG_MEM_CACHE_UPDATE_SLOT_VARIABLE, "VARIABLE" } +}; + +static const char *const me_bios_paths[] = { + "ME normal BIOS path", + "ME S3 wake BIOS path", + "ME error BIOS path", + "ME recovery BIOS path", + "ME disable BIOS path", + "ME firmware update BIOS path", +}; + +#endif /* ELOG_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/40343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b8f92f4aaf0e91244fcdec5a4da0ff843bbacda Gerrit-Change-Number: 40343 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: commonlib/elog: move the event definitions to commonlib
by Michał Żygowski (Code Review) 07 Aug '23

07 Aug '23

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40416 ) Change subject: commonlib/elog: move the event definitions to commonlib ...................................................................... commonlib/elog: move the event definitions to commonlib Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I791ede6f2d88ba4686d11b34686fedc6c3401f07 --- A src/commonlib/include/commonlib/elog.h M src/drivers/elog/elog.c D src/drivers/elog/elog_internal.h M src/include/elog.h 4 files changed, 261 insertions(+), 238 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/40416/1 diff --git a/src/commonlib/include/commonlib/elog.h b/src/commonlib/include/commonlib/elog.h new file mode 100644 index 0000000..9c10beb --- /dev/null +++ b/src/commonlib/include/commonlib/elog.h @@ -0,0 +1,260 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef COMMONLIB_ELOG_H_ +#define COMMONLIB_ELOG_H_ + +/* ELOG header */ +struct elog_header { + uint32_t magic; + uint8_t version; + uint8_t header_size; + uint8_t reserved[2]; +} __packed; + +/* ELOG related constants */ +#define ELOG_SIGNATURE 0x474f4c45 /* 'ELOG' */ +#define ELOG_VERSION 1 +#define ELOG_MIN_AVAILABLE_ENTRIES 2 /* Shrink when this many can't fit */ +#define ELOG_SHRINK_PERCENTAGE 25 /* Percent of total area to remove */ + +/* SMBIOS event log header */ +struct event_header { + uint8_t type; + uint8_t length; + uint8_t year; + uint8_t month; + uint8_t day; + uint8_t hour; + uint8_t minute; + uint8_t second; +} __packed; + +/* SMBIOS Type 15 related constants */ +#define ELOG_HEADER_TYPE_OEM 0x88 + +#define MAX_EVENT_SIZE 0x7F + +/* End of log */ +#define ELOG_TYPE_EOL 0xFF + +/* + * Standard SMBIOS event log types below 0x80 + */ +#define ELOG_TYPE_UNDEFINED_EVENT 0x00 +#define ELOG_TYPE_SINGLE_BIT_ECC_MEM_ERR 0x01 +#define ELOG_TYPE_MULTI_BIT_ECC_MEM_ERR 0x02 +#define ELOG_TYPE_MEM_PARITY_ERR 0x03 +#define ELOG_TYPE_BUS_TIMEOUT 0x04 +#define ELOG_TYPE_IO_CHECK 0x05 +#define ELOG_TYPE_SW_NMI 0x06 +#define ELOG_TYPE_POST_MEM_RESIZE 0x07 +#define ELOG_TYPE_POST_ERR 0x08 +#define ELOG_TYPE_PCI_PERR 0x09 +#define ELOG_TYPE_PCI_SERR 0x0A +#define ELOG_TYPE_CPU_FAIL 0x0B +#define ELOG_TYPE_EISA_TIMEOUT 0x0C +#define ELOG_TYPE_CORRECTABLE_MEMLOG_DIS 0x0D +#define ELOG_TYPE_LOG_DISABLED 0x0E +#define ELOG_TYPE_UNDEFINED_EVENT2 0x0F +#define ELOG_TYPE_SYS_LIMIT_EXCEED 0x10 +#define ELOG_TYPE_ASYNC_HW_TIMER_EXPIRED 0x11 +#define ELOG_TYPE_SYS_CONFIG_INFO 0x12 +#define ELOG_TYPE_HDD_INFO 0x13 +#define ELOG_TYPE_SYS_RECONFIG 0x14 +#define ELOG_TYPE_CPU_ERROR 0x15 +#define ELOG_TYPE_LOG_CLEAR 0x16 +#define ELOG_TYPE_BOOT 0x17 + +/* + * Extended defined OEM event types start at 0x80 + */ + +/* OS/kernel events */ +#define ELOG_TYPE_OS_EVENT 0x81 + +/* Last event from coreboot */ +#define ELOG_TYPE_OS_BOOT 0x90 + +/* Embedded controller event */ +#define ELOG_TYPE_EC_EVENT 0x91 +#define EC_EVENT_LID_CLOSED 0x01 +#define EC_EVENT_LID_OPEN 0x02 +#define EC_EVENT_POWER_BUTTON 0x03 +#define EC_EVENT_AC_CONNECTED 0x04 +#define EC_EVENT_AC_DISCONNECTED 0x05 +#define EC_EVENT_BATTERY_LOW 0x06 +#define EC_EVENT_BATTERY_CRITICAL 0x07 +#define EC_EVENT_BATTERY 0x08 +#define EC_EVENT_THERMAL_THRESHOLD 0x09 +#define EC_EVENT_DEVICE_EVENT 0x0a +#define EC_EVENT_THERMAL 0x0b +#define EC_EVENT_USB_CHARGER 0x0c +#define EC_EVENT_KEY_PRESSED 0x0d +#define EC_EVENT_INTERFACE_READY 0x0e +#define EC_EVENT_KEYBOARD_RECOVERY 0x0f +#define EC_EVENT_THERMAL_SHUTDOWN 0x10 +#define EC_EVENT_BATTERY_SHUTDOWN 0x11 +#define EC_EVENT_FAN_ERROR 0x12 +#define EC_EVENT_THROTTLE_STOP 0x13 +#define EC_EVENT_HANG_DETECT 0x14 +#define EC_EVENT_HANG_REBOOT 0x15 +#define EC_EVENT_PD_MCU 0x16 +#define EC_EVENT_BATTERY_STATUS 0x17 +#define EC_EVENT_PANIC 0x18 +#define EC_EVENT_KEYBOARD_FASTBOOT 0x19 +#define EC_EVENT_RTC 0x1a +#define EC_EVENT_MKBP 0x1b +#define EC_EVENT_USB_MUX 0x1c +#define EC_EVENT_MODE_CHANGE 0x1d +#define EC_EVENT_KEYBOARD_RECOVERY_HWREINIT 0x1e +#define EC_EVENT_EXTENDED 0x1f + +/* Power */ +#define ELOG_TYPE_POWER_FAIL 0x92 +#define ELOG_TYPE_SUS_POWER_FAIL 0x93 +#define ELOG_TYPE_PWROK_FAIL 0x94 +#define ELOG_TYPE_SYS_PWROK_FAIL 0x95 +#define ELOG_TYPE_POWER_ON 0x96 +#define ELOG_TYPE_POWER_BUTTON 0x97 +#define ELOG_TYPE_POWER_BUTTON_OVERRIDE 0x98 + +/* Reset */ +#define ELOG_TYPE_RESET_BUTTON 0x99 +#define ELOG_TYPE_SYSTEM_RESET 0x9a +#define ELOG_TYPE_RTC_RESET 0x9b +#define ELOG_TYPE_TCO_RESET 0x9c + +/* Sleep/Wake */ +#define ELOG_TYPE_ACPI_ENTER 0x9d +/* + * Deep Sx wake variant is provided below - 0xad + * Sleep/"wake pending" event log provided below - 0xb1 - 0x01/0x02 + */ + +#define ELOG_TYPE_ACPI_WAKE 0x9e +#define ELOG_TYPE_WAKE_SOURCE 0x9f +#define ELOG_WAKE_SOURCE_PCIE 0x00 +#define ELOG_WAKE_SOURCE_PME 0x01 +#define ELOG_WAKE_SOURCE_PME_INTERNAL 0x02 +#define ELOG_WAKE_SOURCE_RTC 0x03 +#define ELOG_WAKE_SOURCE_GPIO 0x04 +#define ELOG_WAKE_SOURCE_SMBUS 0x05 +#define ELOG_WAKE_SOURCE_PWRBTN 0x06 +#define ELOG_WAKE_SOURCE_PME_HDA 0x07 +#define ELOG_WAKE_SOURCE_PME_GBE 0x08 +#define ELOG_WAKE_SOURCE_PME_EMMC 0x09 +#define ELOG_WAKE_SOURCE_PME_SDCARD 0x0a +#define ELOG_WAKE_SOURCE_PME_PCIE1 0x0b +#define ELOG_WAKE_SOURCE_PME_PCIE2 0x0c +#define ELOG_WAKE_SOURCE_PME_PCIE3 0x0d +#define ELOG_WAKE_SOURCE_PME_PCIE4 0x0e +#define ELOG_WAKE_SOURCE_PME_PCIE5 0x0f +#define ELOG_WAKE_SOURCE_PME_PCIE6 0x10 +#define ELOG_WAKE_SOURCE_PME_PCIE7 0x11 +#define ELOG_WAKE_SOURCE_PME_PCIE8 0x12 +#define ELOG_WAKE_SOURCE_PME_PCIE9 0x13 +#define ELOG_WAKE_SOURCE_PME_PCIE10 0x14 +#define ELOG_WAKE_SOURCE_PME_PCIE11 0x15 +#define ELOG_WAKE_SOURCE_PME_PCIE12 0x16 +#define ELOG_WAKE_SOURCE_PME_SATA 0x17 +#define ELOG_WAKE_SOURCE_PME_CSE 0x18 +#define ELOG_WAKE_SOURCE_PME_CSE2 0x19 +#define ELOG_WAKE_SOURCE_PME_CSE3 0x1a +#define ELOG_WAKE_SOURCE_PME_XHCI 0x1b +#define ELOG_WAKE_SOURCE_PME_XDCI 0x1c +#define ELOG_WAKE_SOURCE_PME_XHCI_USB_2 0x1d +#define ELOG_WAKE_SOURCE_PME_XHCI_USB_3 0x1e +#define ELOG_WAKE_SOURCE_PME_WIFI 0x1f + +struct elog_event_data_wake { + uint8_t source; + uint32_t instance; +} __packed; + +/* Chrome OS related events */ +#define ELOG_TYPE_CROS_DEVELOPER_MODE 0xa0 +#define ELOG_TYPE_CROS_RECOVERY_MODE 0xa1 +#define ELOG_CROS_RECOVERY_MODE_BUTTON 0x02 + +/* Management Engine Events */ +#define ELOG_TYPE_MANAGEMENT_ENGINE 0xa2 +#define ELOG_TYPE_MANAGEMENT_ENGINE_EXT 0xa4 + +struct elog_event_data_me_extended { + uint8_t current_working_state; + uint8_t operation_state; + uint8_t operation_mode; + uint8_t error_code; + uint8_t progress_code; + uint8_t current_pmevent; + uint8_t current_state; +} __packed; + +/* Last post code from previous boot */ +#define ELOG_TYPE_LAST_POST_CODE 0xa3 +#define ELOG_TYPE_POST_EXTRA 0xa6 + +/* EC Shutdown Reason */ +#define ELOG_TYPE_EC_SHUTDOWN 0xa5 + +/* + * ARM/generic versions of sleep/wake - These came from another firmware + * apparently, but not all the firmware sources were updated so that the + * elog namespace was coherent. + */ +#define ELOG_TYPE_SLEEP 0xa7 +#define ELOG_TYPE_WAKE 0xa8 +#define ELOG_TYPE_FW_WAKE 0xa9 + +/* Memory Cache Update */ +#define ELOG_TYPE_MEM_CACHE_UPDATE 0xaa +#define ELOG_MEM_CACHE_UPDATE_SLOT_NORMAL 0 +#define ELOG_MEM_CACHE_UPDATE_SLOT_RECOVERY 1 +#define ELOG_MEM_CACHE_UPDATE_SLOT_VARIABLE 2 +#define ELOG_MEM_CACHE_UPDATE_STATUS_SUCCESS 0 +#define ELOG_MEM_CACHE_UPDATE_STATUS_FAIL 1 + +struct elog_event_mem_cache_update { + uint8_t slot; + uint8_t status; +} __packed; + +/* CPU Thermal Trip */ +#define ELOG_TYPE_THERM_TRIP 0xab + +/* Cr50 */ +#define ELOG_TYPE_CR50_UPDATE 0xac + +/* Deep Sx wake variant */ +#define ELOG_TYPE_ACPI_DEEP_WAKE 0xad + +/* EC Device Event */ +#define ELOG_TYPE_EC_DEVICE_EVENT 0xae +#define ELOG_EC_DEVICE_EVENT_TRACKPAD 0x01 +#define ELOG_EC_DEVICE_EVENT_DSP 0x02 +#define ELOG_EC_DEVICE_EVENT_WIFI 0x03 + +/* S0ix sleep/wake */ +#define ELOG_TYPE_S0IX_ENTER 0xaf +#define ELOG_TYPE_S0IX_EXIT 0xb0 + +/* Extended events */ +#define ELOG_TYPE_EXTENDED_EVENT 0xb1 +#define ELOG_SLEEP_PENDING_PM1_WAKE 0x01 +#define ELOG_SLEEP_PENDING_GPE0_WAKE 0x02 + +/* Cr50 reset to enable TPM */ +#define ELOG_TYPE_CR50_NEED_RESET 0xb2 + +/* Intruder detection */ +#define ELOG_TYPE_INTRUDER_DETECTION 0xb3 +#define ELOG_CASE_OPENED 0x01 +#define ELOG_CASE_CLOSED 0x02 + +struct elog_event_extended_event { + uint8_t event_type; + uint32_t event_complement; +} __packed; + +#endif /* COMMONLIB_ELOG_H_ */ diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index c353d59..2313ff1 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -20,8 +20,6 @@ #include <stdint.h> #include <string.h> #include <elog.h> -#include "elog_internal.h" - #if CONFIG(ELOG_DEBUG) #define elog_debug(STR...) printk(BIOS_DEBUG, STR) diff --git a/src/drivers/elog/elog_internal.h b/src/drivers/elog/elog_internal.h deleted file mode 100644 index 3c58ee2..0000000 --- a/src/drivers/elog/elog_internal.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#ifndef ELOG_INTERNAL_H_ -#define ELOG_INTERNAL_H_ - -/* ELOG header */ -struct elog_header { - u32 magic; - u8 version; - u8 header_size; - u8 reserved[2]; -} __packed; - -/* ELOG related constants */ -#define ELOG_SIGNATURE 0x474f4c45 /* 'ELOG' */ -#define ELOG_VERSION 1 -#define ELOG_MIN_AVAILABLE_ENTRIES 2 /* Shrink when this many can't fit */ -#define ELOG_SHRINK_PERCENTAGE 25 /* Percent of total area to remove */ - -/* SMBIOS event log header */ -struct event_header { - u8 type; - u8 length; - u8 year; - u8 month; - u8 day; - u8 hour; - u8 minute; - u8 second; -} __packed; - -/* SMBIOS Type 15 related constants */ -#define ELOG_HEADER_TYPE_OEM 0x88 - -#endif /* ELOG_INTERNAL_H_ */ diff --git a/src/include/elog.h b/src/include/elog.h index 5a7632d..de642ae 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -4,206 +4,7 @@ #ifndef ELOG_H_ #define ELOG_H_ -#define MAX_EVENT_SIZE 0x7F - -/* End of log */ -#define ELOG_TYPE_EOL 0xFF - -/* - * Standard SMBIOS event log types below 0x80 - */ -#define ELOG_TYPE_UNDEFINED_EVENT 0x00 -#define ELOG_TYPE_SINGLE_BIT_ECC_MEM_ERR 0x01 -#define ELOG_TYPE_MULTI_BIT_ECC_MEM_ERR 0x02 -#define ELOG_TYPE_MEM_PARITY_ERR 0x03 -#define ELOG_TYPE_BUS_TIMEOUT 0x04 -#define ELOG_TYPE_IO_CHECK 0x05 -#define ELOG_TYPE_SW_NMI 0x06 -#define ELOG_TYPE_POST_MEM_RESIZE 0x07 -#define ELOG_TYPE_POST_ERR 0x08 -#define ELOG_TYPE_PCI_PERR 0x09 -#define ELOG_TYPE_PCI_SERR 0x0A -#define ELOG_TYPE_CPU_FAIL 0x0B -#define ELOG_TYPE_EISA_TIMEOUT 0x0C -#define ELOG_TYPE_CORRECTABLE_MEMLOG_DIS 0x0D -#define ELOG_TYPE_LOG_DISABLED 0x0E -#define ELOG_TYPE_UNDEFINED_EVENT2 0x0F -#define ELOG_TYPE_SYS_LIMIT_EXCEED 0x10 -#define ELOG_TYPE_ASYNC_HW_TIMER_EXPIRED 0x11 -#define ELOG_TYPE_SYS_CONFIG_INFO 0x12 -#define ELOG_TYPE_HDD_INFO 0x13 -#define ELOG_TYPE_SYS_RECONFIG 0x14 -#define ELOG_TYPE_CPU_ERROR 0x15 -#define ELOG_TYPE_LOG_CLEAR 0x16 -#define ELOG_TYPE_BOOT 0x17 - -/* - * Extended defined OEM event types start at 0x80 - */ - -/* OS/kernel events */ -#define ELOG_TYPE_OS_EVENT 0x81 - -/* Last event from coreboot */ -#define ELOG_TYPE_OS_BOOT 0x90 - -/* Embedded controller event */ -#define ELOG_TYPE_EC_EVENT 0x91 - -/* Power */ -#define ELOG_TYPE_POWER_FAIL 0x92 -#define ELOG_TYPE_SUS_POWER_FAIL 0x93 -#define ELOG_TYPE_PWROK_FAIL 0x94 -#define ELOG_TYPE_SYS_PWROK_FAIL 0x95 -#define ELOG_TYPE_POWER_ON 0x96 -#define ELOG_TYPE_POWER_BUTTON 0x97 -#define ELOG_TYPE_POWER_BUTTON_OVERRIDE 0x98 - -/* Reset */ -#define ELOG_TYPE_RESET_BUTTON 0x99 -#define ELOG_TYPE_SYSTEM_RESET 0x9a -#define ELOG_TYPE_RTC_RESET 0x9b -#define ELOG_TYPE_TCO_RESET 0x9c - -/* Sleep/Wake */ -#define ELOG_TYPE_ACPI_ENTER 0x9d -/* - * Deep Sx wake variant is provided below - 0xad - * Sleep/"wake pending" event log provided below - 0xb1 - 0x01/0x02 - */ - -#define ELOG_TYPE_ACPI_WAKE 0x9e -#define ELOG_TYPE_WAKE_SOURCE 0x9f -#define ELOG_WAKE_SOURCE_PCIE 0x00 -#define ELOG_WAKE_SOURCE_PME 0x01 -#define ELOG_WAKE_SOURCE_PME_INTERNAL 0x02 -#define ELOG_WAKE_SOURCE_RTC 0x03 -#define ELOG_WAKE_SOURCE_GPIO 0x04 -#define ELOG_WAKE_SOURCE_SMBUS 0x05 -#define ELOG_WAKE_SOURCE_PWRBTN 0x06 -#define ELOG_WAKE_SOURCE_PME_HDA 0x07 -#define ELOG_WAKE_SOURCE_PME_GBE 0x08 -#define ELOG_WAKE_SOURCE_PME_EMMC 0x09 -#define ELOG_WAKE_SOURCE_PME_SDCARD 0x0a -#define ELOG_WAKE_SOURCE_PME_PCIE1 0x0b -#define ELOG_WAKE_SOURCE_PME_PCIE2 0x0c -#define ELOG_WAKE_SOURCE_PME_PCIE3 0x0d -#define ELOG_WAKE_SOURCE_PME_PCIE4 0x0e -#define ELOG_WAKE_SOURCE_PME_PCIE5 0x0f -#define ELOG_WAKE_SOURCE_PME_PCIE6 0x10 -#define ELOG_WAKE_SOURCE_PME_PCIE7 0x11 -#define ELOG_WAKE_SOURCE_PME_PCIE8 0x12 -#define ELOG_WAKE_SOURCE_PME_PCIE9 0x13 -#define ELOG_WAKE_SOURCE_PME_PCIE10 0x14 -#define ELOG_WAKE_SOURCE_PME_PCIE11 0x15 -#define ELOG_WAKE_SOURCE_PME_PCIE12 0x16 -#define ELOG_WAKE_SOURCE_PME_SATA 0x17 -#define ELOG_WAKE_SOURCE_PME_CSE 0x18 -#define ELOG_WAKE_SOURCE_PME_CSE2 0x19 -#define ELOG_WAKE_SOURCE_PME_CSE3 0x1a -#define ELOG_WAKE_SOURCE_PME_XHCI 0x1b -#define ELOG_WAKE_SOURCE_PME_XDCI 0x1c -#define ELOG_WAKE_SOURCE_PME_XHCI_USB_2 0x1d -#define ELOG_WAKE_SOURCE_PME_XHCI_USB_3 0x1e -#define ELOG_WAKE_SOURCE_PME_WIFI 0x1f -#define ELOG_WAKE_SOURCE_PME_PCIE13 0x20 -#define ELOG_WAKE_SOURCE_PME_PCIE14 0x21 -#define ELOG_WAKE_SOURCE_PME_PCIE15 0x22 -#define ELOG_WAKE_SOURCE_PME_PCIE16 0x23 -#define ELOG_WAKE_SOURCE_PME_PCIE17 0x24 -#define ELOG_WAKE_SOURCE_PME_PCIE18 0x25 -#define ELOG_WAKE_SOURCE_PME_PCIE19 0x26 -#define ELOG_WAKE_SOURCE_PME_PCIE20 0x27 -#define ELOG_WAKE_SOURCE_PME_PCIE21 0x28 -#define ELOG_WAKE_SOURCE_PME_PCIE22 0x29 -#define ELOG_WAKE_SOURCE_PME_PCIE23 0x2a -#define ELOG_WAKE_SOURCE_PME_PCIE24 0x2b - -struct elog_event_data_wake { - u8 source; - u32 instance; -} __packed; - -/* Chrome OS related events */ -#define ELOG_TYPE_CROS_DEVELOPER_MODE 0xa0 -#define ELOG_TYPE_CROS_RECOVERY_MODE 0xa1 -#define ELOG_CROS_RECOVERY_MODE_BUTTON 0x02 - -/* Management Engine Events */ -#define ELOG_TYPE_MANAGEMENT_ENGINE 0xa2 -#define ELOG_TYPE_MANAGEMENT_ENGINE_EXT 0xa4 -struct elog_event_data_me_extended { - u8 current_working_state; - u8 operation_state; - u8 operation_mode; - u8 error_code; - u8 progress_code; - u8 current_pmevent; - u8 current_state; -} __packed; - -/* Last post code from previous boot */ -#define ELOG_TYPE_LAST_POST_CODE 0xa3 -#define ELOG_TYPE_POST_EXTRA 0xa6 - -/* EC Shutdown Reason */ -#define ELOG_TYPE_EC_SHUTDOWN 0xa5 - -/* ARM/generic versions of sleep/wake - These came from another firmware - * apparently, but not all the firmware sources were updated so that the - * elog namespace was coherent. */ -#define ELOG_TYPE_SLEEP 0xa7 -#define ELOG_TYPE_WAKE 0xa8 -#define ELOG_TYPE_FW_WAKE 0xa9 - -/* Memory Cache Update */ -#define ELOG_TYPE_MEM_CACHE_UPDATE 0xaa -#define ELOG_MEM_CACHE_UPDATE_SLOT_NORMAL 0 -#define ELOG_MEM_CACHE_UPDATE_SLOT_RECOVERY 1 -#define ELOG_MEM_CACHE_UPDATE_SLOT_VARIABLE 2 -#define ELOG_MEM_CACHE_UPDATE_STATUS_SUCCESS 0 -#define ELOG_MEM_CACHE_UPDATE_STATUS_FAIL 1 -struct elog_event_mem_cache_update { - u8 slot; - u8 status; -} __packed; - -/* CPU Thermal Trip */ -#define ELOG_TYPE_THERM_TRIP 0xab - -/* Cr50 */ -#define ELOG_TYPE_CR50_UPDATE 0xac - -/* Deep Sx wake variant */ -#define ELOG_TYPE_ACPI_DEEP_WAKE 0xad - -/* EC Device Event */ -#define ELOG_TYPE_EC_DEVICE_EVENT 0xae -#define ELOG_EC_DEVICE_EVENT_TRACKPAD 0x01 -#define ELOG_EC_DEVICE_EVENT_DSP 0x02 -#define ELOG_EC_DEVICE_EVENT_WIFI 0x03 - -/* S0ix sleep/wake */ -#define ELOG_TYPE_S0IX_ENTER 0xaf -#define ELOG_TYPE_S0IX_EXIT 0xb0 - -/* Extended events */ -#define ELOG_TYPE_EXTENDED_EVENT 0xb1 -#define ELOG_SLEEP_PENDING_PM1_WAKE 0x01 -#define ELOG_SLEEP_PENDING_GPE0_WAKE 0x02 - -/* Cr50 reset to enable TPM */ -#define ELOG_TYPE_CR50_NEED_RESET 0xb2 - -/* Intruder detection */ -#define ELOG_TYPE_INTRUDER_DETECTION 0xb3 -#define ELOG_CASE_OPENED 0x01 -#define ELOG_CASE_CLOSED 0x02 - -struct elog_event_extended_event { - u8 event_type; - u32 event_complement; -} __packed; +#include <commonlib/elog.h> #if CONFIG(ELOG) /* Eventlog backing storage must be initialized before calling elog_init(). */ -- To view, visit https://review.coreboot.org/c/coreboot/+/40416 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I791ede6f2d88ba4686d11b34686fedc6c3401f07 Gerrit-Change-Number: 40416 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/tcss: Add common code support for TCSS
by Subrata Banik (Code Review) 07 Aug '23

07 Aug '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41010 ) Change subject: soc/intel/common/block/tcss: Add common code support for TCSS ...................................................................... soc/intel/common/block/tcss: Add common code support for TCSS For now only added CONFIG_TCSS_PCIE_SEGMENT Kconfig to allow dedicated PCI segment support for iTBT. SoC user can select CONFIG_TCSS_PCIE_SEGMENT from dedicated SoC Kconfig to include this support. Change-Id: I33c1e5612a6d4882377784294ca0bcef131f2c0a Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- A src/soc/intel/common/block/tcss/Kconfig 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/41010/1 diff --git a/src/soc/intel/common/block/tcss/Kconfig b/src/soc/intel/common/block/tcss/Kconfig new file mode 100644 index 0000000..0f7fe7c --- /dev/null +++ b/src/soc/intel/common/block/tcss/Kconfig @@ -0,0 +1,9 @@ +config SOC_INTEL_COMMON_BLOCK_TCSS + bool + help + Intel Processor common TCSS support + +config TCSS_PCIE_SEGMENT + bool + help + Indicate the extra PCIE segment is required for iTBT or not -- To view, visit https://review.coreboot.org/c/coreboot/+/41010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33c1e5612a6d4882377784294ca0bcef131f2c0a Gerrit-Change-Number: 41010 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Select CONFIG_TCSS_PCIE_SEGMENT for TGL
by Subrata Banik (Code Review) 07 Aug '23

07 Aug '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41013 ) Change subject: soc/intel/tigerlake: Select CONFIG_TCSS_PCIE_SEGMENT for TGL ...................................................................... soc/intel/tigerlake: Select CONFIG_TCSS_PCIE_SEGMENT for TGL This patch performs below operations 1. Include additional PCI segment by selecting TCSS_PCIE_SEGMENT from SoC 2. Clean up TGL SoC IRQ programming as TBT related programming is now moved into common code (src/soc/intel/common/block/acpi/acpi/pcisegment.asl) Change-Id: Ib94396bd2a06b661d4828357d7a4be973846c707 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/acpi/pci_irqs.asl M src/soc/intel/tigerlake/include/soc/irq.h 3 files changed, 1 insertion(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/41013/1 diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index a690acf..93f12f9 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -60,6 +60,7 @@ select UDK_2017_BINDING select DISPLAY_FSP_VERSION_INFO select HECI_DISABLE_USING_SMM + select TCSS_PCIE_SEGMENT config DCACHE_RAM_BASE default 0xfef00000 diff --git a/src/soc/intel/tigerlake/acpi/pci_irqs.asl b/src/soc/intel/tigerlake/acpi/pci_irqs.asl index 62520b1..7603362 100644 --- a/src/soc/intel/tigerlake/acpi/pci_irqs.asl +++ b/src/soc/intel/tigerlake/acpi/pci_irqs.asl @@ -73,11 +73,6 @@ Package(){0x000DFFFF, 1, 0, xDCI_IRQ }, /* D8: GNA */ Package(){0x0008FFFF, 0, 0, GNA_IRQ }, - /* D7: TBT PCIe */ - Package(){0x0007FFFF, 0, 0, TBT_PCIe0_IRQ }, - Package(){0x0007FFFF, 1, 0, TBT_PCIe1_IRQ }, - Package(){0x0007FFFF, 2, 0, TBT_PCIe2_IRQ }, - Package(){0x0007FFFF, 3, 0, TBT_PCIe3_IRQ }, /* D6: PEG60 */ Package(){0x0006FFFF, 0, 0, PEG_IRQ }, /* D5: IPU Device */ @@ -142,11 +137,6 @@ Package(){0x000DFFFF, 1, 0, 10 }, /* D8: GNA */ Package(){0x0008FFFF, 0, 0, 11 }, - /* D7: TBT PCIe */ - Package(){0x0007FFFF, 0, 0, 11 }, - Package(){0x0007FFFF, 1, 0, 10 }, - Package(){0x0007FFFF, 2, 0, 11 }, - Package(){0x0007FFFF, 3, 0, 11 }, /* D6: PEG60 */ Package(){0x0006FFFF, 0, 0, 11 }, /* D5: IPU Device */ diff --git a/src/soc/intel/tigerlake/include/soc/irq.h b/src/soc/intel/tigerlake/include/soc/irq.h index 01ee10b..1057f91 100644 --- a/src/soc/intel/tigerlake/include/soc/irq.h +++ b/src/soc/intel/tigerlake/include/soc/irq.h @@ -54,11 +54,6 @@ #define ISH_IRQ 16 -#define TBT_PCIe0_IRQ 16 -#define TBT_PCIe1_IRQ 17 -#define TBT_PCIe2_IRQ 18 -#define TBT_PCIe3_IRQ 19 - #define HECI_1_IRQ 16 #define HECI_2_IRQ 17 #define HECI_3_IRQ 16 -- To view, visit https://review.coreboot.org/c/coreboot/+/41013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib94396bd2a06b661d4828357d7a4be973846c707 Gerrit-Change-Number: 41013 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 4

Change in coreboot[master]: memrange: Add helper for stealing memory from the last range in the list
by Furquan Shaikh (Code Review) 07 Aug '23

07 Aug '23

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41418 ) Change subject: memrange: Add helper for stealing memory from the last range in the list ...................................................................... memrange: Add helper for stealing memory from the last range in the list This change adds a helper fucntion memranges_steal_last() that allows the caller to request memory to be stolen from the last range in the list. Memory is stolen from the start of the last range and matches the constraints (limit, align, tag, size) provided by the caller. The current helper functin memranges_steal() defaults to always returning stolen memory from the first available range in the list. Additionally, this change updates the internal function memranges_find_entry() to handle stealing from first and last entries as requested by the caller. Change-Id: I70c07e587597b44306857f0e52eb47b330ca3b1b Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/include/memrange.h M src/lib/memrange.c 2 files changed, 59 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/41418/1 diff --git a/src/include/memrange.h b/src/include/memrange.h index 2b8c00e..4b64e1a 100644 --- a/src/include/memrange.h +++ b/src/include/memrange.h @@ -160,7 +160,8 @@ struct range_entry *memranges_next_entry(struct memranges *ranges, const struct range_entry *r); -/* Steals memory from the available list in given ranges as per the constraints: +/* Steals memory from the first available entry in the list of given ranges as per the + * constraints: * limit = Upper bound for the memory range to steal (Inclusive). * size = Requested size for the stolen memory. * align = Required alignment(log 2) for the starting address of the stolen memory. @@ -172,4 +173,18 @@ bool memranges_steal(struct memranges *ranges, resource_t limit, resource_t size, unsigned char align, unsigned long tag, resource_t *stolen_base); + +/* Steals memory from the last available entry in the list of given ranges as per the + * constraints: + * limit = Upper bound for the memory range to steal (Inclusive). + * size = Requested size for the stolen memory. + * align = Required alignment(log 2) for the starting address of the stolen memory. + * tag = Use a range that matches the given tag. + * + * If the constraints can be satisfied, this function creates a hole in the memrange, + * writes the base address of that hole to stolen_base and returns true. Otherwise it returns + * false. */ +bool memranges_steal_last(struct memranges *ranges, resource_t limit, resource_t size, + unsigned char align, unsigned long tag, resource_t *stolen_base); + #endif /* MEMRANGE_H_ */ diff --git a/src/lib/memrange.c b/src/lib/memrange.c index 39f502c..4b13b00 100644 --- a/src/lib/memrange.c +++ b/src/lib/memrange.c @@ -376,17 +376,27 @@ return r->next; } +enum { + STEAL_FIRST_AVAILABLE, + STEAL_LAST_AVAILABLE, +} + /* Find a range entry that satisfies the given constraints to fit a hole that matches the - * required alignment, is big enough, does not exceed the limit and has a matching tag. */ + * required alignment, is big enough, does not exceed the limit and has a matching tag. + * Depending upon the value of "steal_from", this function either returns the first range entry + * that satisfies the constraints (STEAL_FIRST_AVAILABLE) or the last range entry that + * satisfies the constrains (STEAL_LAST_AVAILABLE). */ static const struct range_entry *memranges_find_entry(struct memranges *ranges, resource_t limit, resource_t size, - unsigned char align, unsigned long tag) + unsigned char align, unsigned long tag, + int steal_from) { const struct range_entry *r; + const struct range_entry *last_entry = NULL; resource_t base, end; if (size == 0) - return NULL; + return false; memranges_each_entry(r, ranges) { @@ -407,17 +417,27 @@ if (end > limit) break; - return r; + last_entry = r; + + /* + * If caller wants to steal from the first available range, then break and + * return the found entry. + */ + if (steal_from == STEAL_FIRST_AVAILABLE) + break; } - return NULL; + return last_entry; } -bool memranges_steal(struct memranges *ranges, resource_t limit, resource_t size, - unsigned char align, unsigned long tag, resource_t *stolen_base) +static bool __memranges_steal(struct memranges *ranges, resource_t limit, resource_t size, + unsigned char align, unsigned long tag, resource_t *stolen_base, + int steal_from) { resource_t base; - const struct range_entry *r = memranges_find_entry(ranges, limit, size, align, tag); + const struct range_entry *r; + + r = memranges_find_entry(ranges, limit, size, align, tag, steal_from); if (r == NULL) return false; @@ -428,4 +448,19 @@ *stolen_base = base; return true; + +} + +bool memranges_steal(struct memranges *ranges, resource_t limit, resource_t size, + unsigned char align, unsigned long tag, resource_t *stolen_base) +{ + return __memranges_steal(ranges, limit, size, align, tag, stolen_base, + STEAL_FIRST_AVAILABLE); +} + +bool memranges_steal_last(struct memranges *ranges, resource_t limit, resource_t size, + unsigned char align, unsigned long tag, resource_t *stolen_base) +{ + return __memranges_steal(ranges, limit, size, align, tag, stolen_base, + STEAL_LAST_AVAILABLE); } -- To view, visit https://review.coreboot.org/c/coreboot/+/41418 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70c07e587597b44306857f0e52eb47b330ca3b1b Gerrit-Change-Number: 41418 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

6 11

Change in coreboot[master]: device: Allocate memory in top-down fashion for child resources
by Furquan Shaikh (Code Review) 07 Aug '23

07 Aug '23

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41419 ) Change subject: device: Allocate memory in top-down fashion for child resources ...................................................................... device: Allocate memory in top-down fashion for child resources This change updates the resource allocator to allocate resources for children in a top-down fashion in the address space by using memranges_steal_last() to get the last range that can satisy the resource request. This is done to maintain consistency with the old resource allocator. There are some AMD chipsets in the tree that do not really work well with the dynamic resource assignment since their resources are not all defined correctly before the allocator runs. Change-Id: If631b0d1fed445723ef506a2c7671faee0326d37 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/device/device.c 1 file changed, 8 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/41419/1 diff --git a/src/device/device.c b/src/device/device.c index d3102bb..b3f3a6e 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -839,8 +839,14 @@ continue; } - if (memranges_steal(ranges, resource->limit, resource->size, resource->align, - type_match, &resource->base) == false) { + /* + * Steal memory from the last available range in the list so that the allocation + * happens in top-down fashion in the address space. This is done to maintain + * consistency with old resource allocator. + */ + if (memranges_steal_last(ranges, resource->limit, resource->size, + resource->align, type_match, + &resource->base) == false) { printk(BIOS_ERR, "ERROR: Resource didn't fit!!! "); printk(BIOS_SPEW, "%s %02lx * size: 0x%llx limit: %llx %s\n", dev_path(dev), resource->index, -- To view, visit https://review.coreboot.org/c/coreboot/+/41419 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If631b0d1fed445723ef506a2c7671faee0326d37 Gerrit-Change-Number: 41419 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: added a new fmap for the qemu-q35 emulation that contains only a read...
by Name of user not set (Code Review) 07 Aug '23

07 Aug '23

Name of user not set #1002959 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41689 ) Change subject: added a new fmap for the qemu-q35 emulation that contains only a read-only section ...................................................................... added a new fmap for the qemu-q35 emulation that contains only a read-only section Change-Id: Ie7c977ab3513be974e1e2ab39f6e05f068121df8 Signed-off-by: A. Bach <zeit(a)manchmal-nie.de> --- A src/mainboard/emulation/qemu-q35/vboot-ro-16M.fmd 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/41689/1 diff --git a/src/mainboard/emulation/qemu-q35/vboot-ro-16M.fmd b/src/mainboard/emulation/qemu-q35/vboot-ro-16M.fmd new file mode 100644 index 0000000..4d4fcd6 --- /dev/null +++ b/src/mainboard/emulation/qemu-q35/vboot-ro-16M.fmd @@ -0,0 +1,14 @@ +FLASH@0xff000000 0x1000000 { + SI_BIOS 0x1000000 { + RW_VPD(PRESERVE) 0x1000 + + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + RO_VPD(PRESERVE) 0x1000 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/41689 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7c977ab3513be974e1e2ab39f6e05f068121df8 Gerrit-Change-Number: 41689 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002959 Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: [RFC] util/sconfig: Add per-device configuration
by Nico Huber (Code Review) 07 Aug '23

07 Aug '23

Hello Furquan Shaikh, Patrick Georgi, Angel Pons, Arthur Heymans, Kyösti Mälkki, Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/41745 to review the following change. Change subject: [RFC] util/sconfig: Add per-device configuration ...................................................................... [RFC] util/sconfig: Add per-device configuration Similar to the `register` entries for chip drivers, allow to store a configuration struct per device. This should help the ever growing chips in two ways: First, it should overcome the psychological issue that nobody is going to use the `chip` mechanism for configuration unless a device is really on a separate chip. And second, by having a separate struct per device, we can directly query this struct from a common driver, even if not the whole chip is covered by common code. The current implementation borrows some logic from the `register` entries, but groups all key-value pairs in a `config` section, e.g.: device generic 0.0 on config drivers/vendor/model key = value paradox = same_value end end Similar to chip drivers, this example would require a `drivers/vendor/model/config.h` with a struct named `drivers_vendor_model_config` containing `key` and `paradox` fields, and definitions for `value` and `same_value`. Change-Id: I25f46e774bb6d26d0e6b77f9bd96d80581412655 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/include/device/device.h M util/sconfig/lex.yy.c_shipped M util/sconfig/main.c M util/sconfig/sconfig.h M util/sconfig/sconfig.l M util/sconfig/sconfig.tab.c_shipped M util/sconfig/sconfig.tab.h_shipped M util/sconfig/sconfig.y 8 files changed, 391 insertions(+), 310 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/41745/1 diff --git a/src/include/device/device.h b/src/include/device/device.h index 46efbfe..23abc72 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -139,6 +139,7 @@ struct device_operations *ops; struct chip_operations *chip_ops; const char *name; + const void *config; #if CONFIG(GENERATE_SMBIOS_TABLES) u8 smbios_slot_type; u8 smbios_slot_data_width; diff --git a/util/sconfig/lex.yy.c_shipped b/util/sconfig/lex.yy.c_shipped index 61928e6..e7059b7 100644 --- a/util/sconfig/lex.yy.c_shipped +++ b/util/sconfig/lex.yy.c_shipped @@ -349,8 +349,8 @@ (yy_hold_char) = *yy_cp; \ *yy_cp = '\0'; \ (yy_c_buf_p) = yy_cp; -#define YY_NUM_RULES 41 -#define YY_END_OF_BUFFER 42 +#define YY_NUM_RULES 42 +#define YY_END_OF_BUFFER 43 /* This struct is not used in this scanner, but its presence is necessary. */ struct yy_trans_info @@ -358,27 +358,27 @@ flex_int32_t yy_verify; flex_int32_t yy_nxt; }; -static const flex_int16_t yy_accept[173] = +static const flex_int16_t yy_accept[178] = { 0, - 0, 0, 42, 40, 1, 3, 40, 40, 40, 35, - 35, 33, 36, 40, 36, 36, 36, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, 1, 3, - 40, 0, 40, 40, 0, 2, 35, 36, 40, 40, - 40, 40, 36, 40, 40, 40, 40, 40, 40, 40, - 40, 27, 40, 40, 40, 40, 40, 40, 7, 40, - 40, 40, 40, 40, 40, 40, 39, 39, 40, 0, - 34, 40, 40, 17, 40, 40, 26, 31, 40, 40, - 40, 14, 40, 40, 25, 40, 23, 40, 40, 8, - 11, 13, 40, 40, 21, 40, 22, 40, 0, 37, + 0, 0, 43, 41, 1, 3, 41, 41, 41, 36, + 36, 34, 37, 41, 37, 37, 37, 41, 41, 41, + 41, 41, 41, 41, 41, 41, 41, 41, 1, 3, + 41, 0, 41, 41, 0, 2, 36, 37, 41, 41, + 41, 41, 41, 37, 41, 41, 41, 41, 41, 41, + 41, 41, 28, 41, 41, 41, 41, 41, 41, 8, + 41, 41, 41, 41, 41, 41, 41, 40, 40, 41, + 0, 35, 41, 41, 41, 18, 41, 41, 27, 32, + 41, 41, 41, 15, 41, 41, 26, 41, 24, 41, + 41, 9, 12, 14, 41, 41, 22, 41, 23, 41, - 4, 40, 40, 40, 24, 40, 40, 40, 40, 40, - 40, 20, 40, 40, 40, 38, 38, 40, 40, 40, - 40, 40, 40, 40, 15, 40, 40, 40, 40, 40, - 5, 18, 40, 9, 40, 12, 40, 40, 40, 40, - 40, 19, 29, 40, 40, 40, 40, 40, 40, 40, - 40, 6, 40, 40, 40, 40, 10, 40, 40, 40, - 28, 40, 40, 16, 40, 30, 40, 40, 40, 40, - 32, 0 + 0, 38, 4, 41, 41, 41, 41, 25, 41, 41, + 41, 41, 41, 41, 21, 41, 41, 41, 39, 39, + 41, 41, 41, 41, 41, 41, 41, 41, 16, 41, + 41, 41, 41, 6, 41, 5, 19, 41, 10, 41, + 13, 41, 41, 41, 41, 41, 20, 30, 41, 41, + 41, 41, 41, 41, 41, 41, 7, 41, 41, 41, + 41, 11, 41, 41, 41, 29, 41, 41, 17, 41, + 31, 41, 41, 41, 41, 33, 0 } ; static const YY_CHAR yy_ec[256] = @@ -421,118 +421,122 @@ 1, 1, 1, 1, 1, 1, 1, 1 } ; -static const flex_int16_t yy_base[180] = +static const flex_int16_t yy_base[185] = { 0, - 0, 0, 240, 0, 237, 241, 235, 37, 41, 38, - 200, 0, 44, 222, 54, 78, 60, 214, 209, 45, - 49, 48, 42, 52, 212, 62, 199, 0, 229, 241, - 93, 225, 98, 79, 226, 241, 0, 97, 104, 213, - 202, 191, 110, 198, 193, 203, 192, 193, 200, 200, - 194, 200, 185, 185, 195, 185, 187, 189, 0, 185, - 179, 185, 189, 181, 187, 186, 0, 241, 125, 198, - 0, 191, 171, 184, 174, 181, 0, 0, 172, 175, - 175, 0, 173, 163, 0, 167, 0, 171, 161, 0, - 0, 0, 164, 163, 0, 154, 0, 181, 180, 0, + 0, 0, 245, 0, 242, 246, 240, 37, 41, 38, + 205, 0, 44, 227, 54, 78, 60, 219, 214, 45, + 49, 48, 42, 52, 217, 62, 204, 0, 234, 246, + 93, 230, 98, 79, 231, 246, 0, 97, 104, 218, + 207, 203, 195, 110, 202, 197, 207, 196, 197, 204, + 204, 198, 204, 189, 189, 199, 189, 191, 193, 0, + 189, 183, 189, 193, 185, 191, 190, 0, 246, 125, + 202, 0, 195, 175, 182, 187, 177, 184, 0, 0, + 175, 178, 178, 0, 176, 166, 0, 170, 0, 174, + 164, 0, 0, 0, 167, 166, 0, 157, 0, 184, - 0, 165, 164, 157, 0, 149, 159, 147, 153, 158, - 159, 0, 142, 145, 135, 0, 241, 146, 150, 142, - 144, 140, 142, 147, 0, 131, 130, 130, 129, 126, - 0, 0, 141, 0, 125, 129, 115, 122, 126, 107, - 107, 0, 0, 114, 106, 105, 103, 114, 100, 101, - 94, 0, 105, 102, 99, 83, 0, 80, 83, 70, - 0, 60, 71, 0, 74, 0, 63, 55, 39, 29, - 0, 241, 40, 146, 148, 150, 152, 154, 156 + 183, 0, 0, 162, 167, 166, 159, 0, 151, 161, + 149, 155, 160, 161, 0, 144, 147, 137, 0, 246, + 151, 147, 151, 143, 145, 141, 143, 148, 0, 132, + 131, 131, 130, 0, 127, 0, 0, 142, 0, 126, + 143, 116, 123, 127, 108, 108, 0, 0, 115, 107, + 106, 104, 115, 101, 102, 95, 0, 106, 104, 108, + 89, 0, 85, 84, 76, 0, 68, 74, 0, 75, + 0, 70, 55, 39, 29, 0, 246, 40, 146, 148, + 150, 152, 154, 156 } ; -static const flex_int16_t yy_def[180] = +static const flex_int16_t yy_def[185] = { 0, - 172, 1, 172, 173, 172, 172, 173, 174, 175, 173, - 10, 173, 10, 173, 10, 10, 10, 173, 173, 173, - 173, 173, 173, 173, 173, 173, 173, 173, 172, 172, - 174, 176, 177, 175, 178, 172, 10, 10, 10, 173, - 173, 173, 10, 173, 173, 173, 173, 173, 173, 173, - 173, 173, 173, 173, 173, 173, 173, 173, 173, 173, - 173, 173, 173, 173, 173, 173, 173, 172, 177, 179, - 39, 173, 173, 173, 173, 173, 173, 173, 173, 173, - 173, 173, 173, 173, 173, 173, 173, 173, 173, 173, - 173, 173, 173, 173, 173, 173, 173, 173, 172, 173, + 177, 1, 177, 178, 177, 177, 178, 179, 180, 178, + 10, 178, 10, 178, 10, 10, 10, 178, 178, 178, + 178, 178, 178, 178, 178, 178, 178, 178, 177, 177, + 179, 181, 182, 180, 183, 177, 10, 10, 10, 178, + 178, 178, 178, 10, 178, 178, 178, 178, 178, 178, + 178, 178, 178, 178, 178, 178, 178, 178, 178, 178, + 178, 178, 178, 178, 178, 178, 178, 178, 177, 182, + 184, 39, 178, 178, 178, 178, 178, 178, 178, 178, + 178, 178, 178, 178, 178, 178, 178, 178, 178, 178, + 178, 178, 178, 178, 178, 178, 178, 178, 178, 178, - 173, 173, 173, 173, 173, 173, 173, 173, 173, 173, - 173, 173, 173, 173, 173, 173, 172, 173, 173, 173, - 173, 173, 173, 173, 173, 173, 173, 173, 173, 173, - 173, 173, 173, 173, 173, 173, 173, 173, 173, 173, - 173, 173, 173, 173, 173, 173, 173, 173, 173, 173, - 173, 173, 173, 173, 173, 173, 173, 173, 173, 173, - 173, 173, 173, 173, 173, 173, 173, 173, 173, 173, - 173, 0, 172, 172, 172, 172, 172, 172, 172 + 177, 178, 178, 178, 178, 178, 178, 178, 178, 178, + 178, 178, 178, 178, 178, 178, 178, 178, 178, 177, + 178, 178, 178, 178, 178, 178, 178, 178, 178, 178, + 178, 178, 178, 178, 178, 178, 178, 178, 178, 178, + 178, 178, 178, 178, 178, 178, 178, 178, 178, 178, + 178, 178, 178, 178, 178, 178, 178, 178, 178, 178, + 178, 178, 178, 178, 178, 178, 178, 178, 178, 178, + 178, 178, 178, 178, 178, 178, 0, 177, 177, 177, + 177, 177, 177, 177 } ; -static const flex_int16_t yy_nxt[280] = +static const flex_int16_t yy_nxt[285] = { 0, 4, 5, 6, 7, 8, 9, 10, 11, 10, 12, 13, 13, 14, 4, 4, 4, 13, 13, 15, 16, 17, 13, 18, 19, 20, 21, 22, 4, 23, 24, 4, 25, 26, 4, 27, 4, 4, 4, 32, 32, - 28, 33, 35, 36, 37, 37, 37, 171, 38, 38, - 38, 38, 38, 50, 38, 38, 38, 38, 38, 38, - 38, 38, 38, 58, 56, 54, 38, 38, 38, 59, - 60, 170, 51, 52, 57, 169, 53, 41, 55, 61, - 35, 36, 168, 42, 38, 38, 38, 46, 63, 167, - 166, 64, 47, 165, 32, 32, 65, 67, 43, 70, + 28, 33, 35, 36, 37, 37, 37, 176, 38, 38, + 38, 38, 38, 51, 38, 38, 38, 38, 38, 38, + 38, 38, 38, 59, 57, 55, 38, 38, 38, 60, + 61, 175, 52, 53, 58, 174, 54, 41, 56, 62, + 35, 36, 42, 43, 38, 38, 38, 47, 64, 173, + 172, 65, 48, 171, 32, 32, 66, 68, 44, 71, - 70, 164, 28, 38, 38, 38, 44, 163, 162, 45, - 71, 71, 71, 161, 71, 71, 38, 38, 38, 160, - 71, 71, 71, 71, 71, 71, 70, 70, 159, 98, - 158, 157, 156, 155, 154, 153, 152, 151, 150, 149, - 148, 147, 146, 145, 144, 75, 31, 31, 34, 34, - 32, 32, 69, 69, 35, 35, 70, 70, 143, 142, - 141, 140, 139, 138, 137, 136, 135, 134, 133, 132, - 131, 130, 129, 128, 127, 126, 125, 124, 123, 122, - 121, 120, 119, 118, 117, 116, 115, 114, 113, 112, - 111, 110, 109, 108, 107, 106, 105, 104, 103, 102, + 71, 170, 28, 38, 38, 38, 45, 169, 168, 46, + 72, 72, 72, 167, 72, 72, 38, 38, 38, 166, + 72, 72, 72, 72, 72, 72, 71, 71, 165, 100, + 164, 163, 162, 161, 160, 159, 158, 157, 156, 155, + 154, 153, 152, 151, 150, 77, 31, 31, 34, 34, + 32, 32, 70, 70, 35, 35, 71, 71, 149, 148, + 147, 146, 145, 144, 143, 142, 141, 140, 139, 138, + 137, 136, 135, 134, 133, 132, 131, 130, 129, 128, + 127, 126, 125, 124, 123, 122, 121, 120, 119, 118, + 117, 116, 115, 114, 113, 112, 111, 110, 109, 108, - 101, 100, 99, 97, 96, 95, 94, 93, 92, 91, - 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, - 80, 79, 78, 77, 76, 74, 73, 72, 36, 68, - 29, 66, 62, 49, 48, 40, 39, 30, 29, 172, - 3, 172, 172, 172, 172, 172, 172, 172, 172, 172, - 172, 172, 172, 172, 172, 172, 172, 172, 172, 172, - 172, 172, 172, 172, 172, 172, 172, 172, 172, 172, - 172, 172, 172, 172, 172, 172, 172, 172, 172 + 107, 106, 105, 104, 103, 102, 101, 99, 98, 97, + 96, 95, 94, 93, 92, 91, 90, 89, 88, 87, + 86, 85, 84, 83, 82, 81, 80, 79, 78, 76, + 75, 74, 73, 36, 69, 29, 67, 63, 50, 49, + 40, 39, 30, 29, 177, 3, 177, 177, 177, 177, + 177, 177, 177, 177, 177, 177, 177, 177, 177, 177, + 177, 177, 177, 177, 177, 177, 177, 177, 177, 177, + 177, 177, 177, 177, 177, 177, 177, 177, 177, 177, + 177, 177, 177, 177 } ; -static const flex_int16_t yy_chk[280] = +static const flex_int16_t yy_chk[285] = { 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 8, 8, - 173, 8, 9, 9, 10, 10, 10, 170, 10, 10, + 178, 8, 9, 9, 10, 10, 10, 175, 10, 10, 13, 13, 13, 20, 10, 10, 10, 10, 10, 10, 15, 15, 15, 23, 22, 21, 17, 17, 17, 23, - 24, 169, 20, 20, 22, 168, 20, 15, 21, 24, - 34, 34, 167, 15, 16, 16, 16, 17, 26, 165, - 163, 26, 17, 162, 31, 31, 26, 31, 16, 33, + 24, 174, 20, 20, 22, 173, 20, 15, 21, 24, + 34, 34, 15, 15, 16, 16, 16, 17, 26, 172, + 170, 26, 17, 168, 31, 31, 26, 31, 16, 33, - 33, 160, 33, 38, 38, 38, 16, 159, 158, 16, - 39, 39, 39, 156, 39, 39, 43, 43, 43, 155, - 39, 39, 39, 39, 39, 39, 69, 69, 154, 69, - 153, 151, 150, 149, 148, 147, 146, 145, 144, 141, - 140, 139, 138, 137, 136, 43, 174, 174, 175, 175, - 176, 176, 177, 177, 178, 178, 179, 179, 135, 133, - 130, 129, 128, 127, 126, 124, 123, 122, 121, 120, - 119, 118, 115, 114, 113, 111, 110, 109, 108, 107, - 106, 104, 103, 102, 99, 98, 96, 94, 93, 89, - 88, 86, 84, 83, 81, 80, 79, 76, 75, 74, + 33, 167, 33, 38, 38, 38, 16, 165, 164, 16, + 39, 39, 39, 163, 39, 39, 44, 44, 44, 161, + 39, 39, 39, 39, 39, 39, 70, 70, 160, 70, + 159, 158, 156, 155, 154, 153, 152, 151, 150, 149, + 146, 145, 144, 143, 142, 44, 179, 179, 180, 180, + 181, 181, 182, 182, 183, 183, 184, 184, 141, 140, + 138, 135, 133, 132, 131, 130, 128, 127, 126, 125, + 124, 123, 122, 121, 118, 117, 116, 114, 113, 112, + 111, 110, 109, 107, 106, 105, 104, 101, 100, 98, + 96, 95, 91, 90, 88, 86, 85, 83, 82, 81, - 73, 72, 70, 66, 65, 64, 63, 62, 61, 60, - 58, 57, 56, 55, 54, 53, 52, 51, 50, 49, - 48, 47, 46, 45, 44, 42, 41, 40, 35, 32, - 29, 27, 25, 19, 18, 14, 11, 7, 5, 3, - 172, 172, 172, 172, 172, 172, 172, 172, 172, 172, - 172, 172, 172, 172, 172, 172, 172, 172, 172, 172, - 172, 172, 172, 172, 172, 172, 172, 172, 172, 172, - 172, 172, 172, 172, 172, 172, 172, 172, 172 + 78, 77, 76, 75, 74, 73, 71, 67, 66, 65, + 64, 63, 62, 61, 59, 58, 57, 56, 55, 54, + 53, 52, 51, 50, 49, 48, 47, 46, 45, 43, + 42, 41, 40, 35, 32, 29, 27, 25, 19, 18, + 14, 11, 7, 5, 3, 177, 177, 177, 177, 177, + 177, 177, 177, 177, 177, 177, 177, 177, 177, 177, + 177, 177, 177, 177, 177, 177, 177, 177, 177, 177, + 177, 177, 177, 177, 177, 177, 177, 177, 177, 177, + 177, 177, 177, 177 } ; static yy_state_type yy_last_accepting_state; @@ -549,21 +553,8 @@ #define YY_MORE_ADJ 0 #define YY_RESTORE_YY_MORE_OFFSET char *yytext; -/* - * sconfig, coreboot device tree compiler - * - * Copyright (C) 2010 coresystems GmbH - * written by Patrick Georgi <patrick(a)georgi-clan.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* sconfig, coreboot device tree compiler */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include "sconfig.tab.h" @@ -810,13 +801,13 @@ while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 173 ) + if ( yy_current_state >= 178 ) yy_c = yy_meta[yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + yy_c]; ++yy_cp; } - while ( yy_base[yy_current_state] != 241 ); + while ( yy_base[yy_current_state] != 246 ); yy_find_action: yy_act = yy_accept[yy_current_state]; @@ -864,119 +855,119 @@ YY_BREAK case 6: YY_RULE_SETUP -{return(REGISTER);} +{return(CONFIG);} YY_BREAK case 7: YY_RULE_SETUP -{yylval.number=1; return(BOOL);} +{return(REGISTER);} YY_BREAK case 8: YY_RULE_SETUP -{yylval.number=0; return(BOOL);} +{yylval.number=1; return(BOOL);} YY_BREAK case 9: YY_RULE_SETUP -{yylval.number=3; return(STATUS);} +{yylval.number=0; return(BOOL);} YY_BREAK case 10: YY_RULE_SETUP -{yylval.number=5; return(STATUS);} +{yylval.number=3; return(STATUS);} YY_BREAK case 11: YY_RULE_SETUP -{yylval.number=PCI; return(BUS);} +{yylval.number=5; return(STATUS);} YY_BREAK case 12: YY_RULE_SETUP -{yylval.number=IOAPIC; return(BUS);} +{yylval.number=PCI; return(BUS);} YY_BREAK case 13: YY_RULE_SETUP -{yylval.number=PNP; return(BUS);} +{yylval.number=IOAPIC; return(BUS);} YY_BREAK case 14: YY_RULE_SETUP -{yylval.number=I2C; return(BUS);} +{yylval.number=PNP; return(BUS);} YY_BREAK case 15: YY_RULE_SETUP -{yylval.number=APIC; return(BUS);} +{yylval.number=I2C; return(BUS);} YY_BREAK case 16: YY_RULE_SETUP -{yylval.number=CPU_CLUSTER; return(BUS);} +{yylval.number=APIC; return(BUS);} YY_BREAK case 17: YY_RULE_SETUP -{yylval.number=CPU; return(BUS);} +{yylval.number=CPU_CLUSTER; return(BUS);} YY_BREAK case 18: YY_RULE_SETUP -{yylval.number=DOMAIN; return(BUS);} +{yylval.number=CPU; return(BUS);} YY_BREAK case 19: YY_RULE_SETUP -{yylval.number=GENERIC; return(BUS);} +{yylval.number=DOMAIN; return(BUS);} YY_BREAK case 20: YY_RULE_SETUP -{yylval.number=MMIO; return(BUS);} +{yylval.number=GENERIC; return(BUS);} YY_BREAK case 21: YY_RULE_SETUP -{yylval.number=SPI; return(BUS);} +{yylval.number=MMIO; return(BUS);} YY_BREAK case 22: YY_RULE_SETUP -{yylval.number=USB; return(BUS);} +{yylval.number=SPI; return(BUS);} YY_BREAK case 23: YY_RULE_SETUP -{yylval.number=LPC; return(BUS);} +{yylval.number=USB; return(BUS);} YY_BREAK case 24: YY_RULE_SETUP -{yylval.number=ESPI; return(BUS);} +{yylval.number=LPC; return(BUS);} YY_BREAK case 25: YY_RULE_SETUP -{yylval.number=IRQ; return(RESOURCE);} +{yylval.number=ESPI; return(BUS);} YY_BREAK case 26: YY_RULE_SETUP -{yylval.number=DRQ; return(RESOURCE);} +{yylval.number=IRQ; return(RESOURCE);} YY_BREAK case 27: YY_RULE_SETUP -{yylval.number=IO; return(RESOURCE);} +{yylval.number=DRQ; return(RESOURCE);} YY_BREAK case 28: YY_RULE_SETUP -{return(IOAPIC_IRQ);} +{yylval.number=IO; return(RESOURCE);} YY_BREAK case 29: YY_RULE_SETUP -{return(INHERIT);} +{return(IOAPIC_IRQ);} YY_BREAK case 30: YY_RULE_SETUP -{return(SUBSYSTEMID);} +{return(INHERIT);} YY_BREAK case 31: YY_RULE_SETUP -{return(END);} +{return(SUBSYSTEMID);} YY_BREAK case 32: YY_RULE_SETUP -{return(SLOT_DESC);} +{return(END);} YY_BREAK case 33: YY_RULE_SETUP -{return(EQUALS);} +{return(SLOT_DESC);} YY_BREAK case 34: YY_RULE_SETUP -{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} +{return(EQUALS);} YY_BREAK case 35: YY_RULE_SETUP @@ -988,12 +979,11 @@ YY_BREAK case 37: YY_RULE_SETUP -{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(PCIINT);} +{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} YY_BREAK case 38: -/* rule 38 can match eol */ YY_RULE_SETUP -{yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} +{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(PCIINT);} YY_BREAK case 39: /* rule 39 can match eol */ @@ -1001,10 +991,15 @@ {yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} YY_BREAK case 40: +/* rule 40 can match eol */ +YY_RULE_SETUP +{yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} + YY_BREAK +case 41: YY_RULE_SETUP {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(STRING);} YY_BREAK -case 41: +case 42: YY_RULE_SETUP ECHO; YY_BREAK @@ -1304,7 +1299,7 @@ while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 173 ) + if ( yy_current_state >= 178 ) yy_c = yy_meta[yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + yy_c]; @@ -1332,11 +1327,11 @@ while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 173 ) + if ( yy_current_state >= 178 ) yy_c = yy_meta[yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + yy_c]; - yy_is_jam = (yy_current_state == 172); + yy_is_jam = (yy_current_state == 177); return yy_is_jam ? 0 : yy_current_state; } diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 0d8f7f8..0e033d9 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -528,6 +528,12 @@ new_resource(bus->dev, type, index, base); } +void set_config_path(struct bus *bus, char *path) +{ + bus->dev->config_path = path; + bus->dev->config_path_underscore = translate_name(path, UNSLASH); +} + static void add_reg(struct reg **const head, char *const name, char *const val) { struct reg *const r = S_ALLOC(sizeof(struct reg)); @@ -540,7 +546,7 @@ for (cur = *head; cur != NULL; prev = cur, cur = cur->next) { const int sort = strcmp(r->key, cur->key); if (sort == 0) { - printf("ERROR: duplicate 'register' key.\n"); + printf("ERROR: duplicate key '%s'.\n", name); exit(1); } if (sort < 0) @@ -553,6 +559,11 @@ *head = r; } +void add_setting(struct bus *bus, char *name, char *val) +{ + add_reg(&bus->dev->settings, name, val); +} + void add_register(struct chip_instance *chip_instance, char *name, char *val) { add_reg(&chip_instance->reg, name, val); @@ -644,6 +655,9 @@ ptr->name = name; fprintf(fil, "STORAGE struct device %s;\n", ptr->name); + if (ptr->config_path) + fprintf(fil, "STORAGE struct %s_config %s_config;\n", + ptr->config_path_underscore, ptr->name); if (ptr->res) fprintf(fil, "STORAGE struct resource %s_res[];\n", ptr->name); @@ -659,6 +673,22 @@ ptr->name); } +static void emit_config(FILE *fil, struct device *ptr) +{ + struct reg *r; + + if (ptr->config_path == NULL) + return; + + fprintf(fil, "STORAGE struct %s_config %s_config = {\n", + ptr->config_path_underscore, ptr->name); + + for (r = ptr->settings; r != NULL; r = r->next) + fprintf(fil, "\t.%s = %s,\n", r->key, r->value); + + fprintf(fil, "};\n"); +} + static void emit_resources(FILE *fil, struct device *ptr) { if (ptr->res == NULL) @@ -748,6 +778,8 @@ fprintf(fil, "\t.ops = &default_dev_ops_root,\n"); else fprintf(fil, "\t.ops = NULL,\n"); + if (ptr->config_path) + fprintf(fil, "\t.config = &%s_config,\n", ptr->name); fprintf(fil, "#endif\n"); fprintf(fil, "\t.bus = &%s_links[%d],\n", ptr->parent->dev->name, ptr->parent->id); @@ -826,6 +858,7 @@ } fprintf(fil, "};\n"); + emit_config(fil, ptr); emit_resources(fil, ptr); if (has_children) @@ -1301,6 +1334,12 @@ } } +static void emit_config_headers(FILE *file, FILE *head, struct device *dev, struct device *next) +{ + if (dev->config_path) + fprintf(file, "#include \"%s/config.h\"\n", dev->config_path); +} + int main(int argc, char **argv) { if ((argc < MANDATORY_ARG_COUNT) || (argc > TOTAL_ARG_COUNT)) @@ -1346,6 +1385,8 @@ fprintf(autogen, "#include <device/device.h>\n"); fprintf(autogen, "#include <device/pci.h>\n\n"); + walk_device_tree(autogen, autohead, &base_root_dev, emit_config_headers); + fprintf(autogen, "\n"); emit_chips(autogen); diff --git a/util/sconfig/sconfig.h b/util/sconfig/sconfig.h index a960b7f..bd97d240 100644 --- a/util/sconfig/sconfig.h +++ b/util/sconfig/sconfig.h @@ -125,6 +125,11 @@ /* Pointer to chip instance for this device. */ struct chip_instance *chip_instance; + /* Path of config and settings. */ + char *config_path; + char *config_path_underscore; + struct reg *settings; + /* Pointer to list of buses under this device. */ struct bus *bus; /* Pointer to last bus under this device. */ @@ -150,6 +155,9 @@ const int bustype, const char *devnum, int status); +void set_config_path(struct bus *bus, char *path); +void add_setting(struct bus *bus, char *name, char *val); + void add_resource(struct bus *bus, int type, int index, int base); void add_pci_subsystem_ids(struct bus *bus, int vendor, int device, diff --git a/util/sconfig/sconfig.l b/util/sconfig/sconfig.l index 5ac5057..f0b1efd 100755 --- a/util/sconfig/sconfig.l +++ b/util/sconfig/sconfig.l @@ -13,6 +13,7 @@ \r?\n {linenum++;} chip {return(CHIP);} device {return(DEVICE);} +config {return(CONFIG);} register {return(REGISTER);} on {yylval.number=1; return(BOOL);} off {yylval.number=0; return(BOOL);} diff --git a/util/sconfig/sconfig.tab.c_shipped b/util/sconfig/sconfig.tab.c_shipped index 2bae43b..b0d79bd 100644 --- a/util/sconfig/sconfig.tab.c_shipped +++ b/util/sconfig/sconfig.tab.c_shipped @@ -111,8 +111,8 @@ /* Use api.header.include to #include this header instead of duplicating it here. */ -#ifndef YY_YY_HOME_ME_REPOS_COREBOOTORG_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED -# define YY_YY_HOME_ME_REPOS_COREBOOTORG_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED +#ifndef YY_YY_HOME_ICON_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED +# define YY_YY_HOME_ICON_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED /* Debug traces. */ #ifndef YYDEBUG # define YYDEBUG 0 @@ -128,39 +128,40 @@ { CHIP = 258, DEVICE = 259, - REGISTER = 260, - BOOL = 261, - STATUS = 262, - MANDATORY = 263, - BUS = 264, - RESOURCE = 265, - END = 266, - EQUALS = 267, - HEX = 268, - STRING = 269, - PCI = 270, - PNP = 271, - I2C = 272, - APIC = 273, - CPU_CLUSTER = 274, - CPU = 275, - DOMAIN = 276, - IRQ = 277, - DRQ = 278, - SLOT_DESC = 279, - IO = 280, - NUMBER = 281, - SUBSYSTEMID = 282, - INHERIT = 283, - IOAPIC_IRQ = 284, - IOAPIC = 285, - PCIINT = 286, - GENERIC = 287, - SPI = 288, - USB = 289, - MMIO = 290, - LPC = 291, - ESPI = 292 + CONFIG = 260, + REGISTER = 261, + BOOL = 262, + STATUS = 263, + MANDATORY = 264, + BUS = 265, + RESOURCE = 266, + END = 267, + EQUALS = 268, + HEX = 269, + STRING = 270, + PCI = 271, + PNP = 272, + I2C = 273, + APIC = 274, + CPU_CLUSTER = 275, + CPU = 276, + DOMAIN = 277, + IRQ = 278, + DRQ = 279, + SLOT_DESC = 280, + IO = 281, + NUMBER = 282, + SUBSYSTEMID = 283, + INHERIT = 284, + IOAPIC_IRQ = 285, + IOAPIC = 286, + PCIINT = 287, + GENERIC = 288, + SPI = 289, + USB = 290, + MMIO = 291, + LPC = 292, + ESPI = 293 }; #endif @@ -186,7 +187,7 @@ int yyparse (void); -#endif /* !YY_YY_HOME_ME_REPOS_COREBOOTORG_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED */ +#endif /* !YY_YY_HOME_ICON_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED */ @@ -492,19 +493,19 @@ /* YYFINAL -- State number of the termination state. */ #define YYFINAL 3 /* YYLAST -- Last index in YYTABLE. */ -#define YYLAST 45 +#define YYLAST 55 /* YYNTOKENS -- Number of terminals. */ -#define YYNTOKENS 38 +#define YYNTOKENS 39 /* YYNNTS -- Number of nonterminals. */ -#define YYNNTS 15 +#define YYNNTS 19 /* YYNRULES -- Number of rules. */ -#define YYNRULES 29 +#define YYNRULES 35 /* YYNSTATES -- Number of states. */ -#define YYNSTATES 50 +#define YYNSTATES 61 #define YYUNDEFTOK 2 -#define YYMAXUTOK 292 +#define YYMAXUTOK 293 /* YYTRANSLATE(TOKEN-NUM) -- Symbol number corresponding to TOKEN-NUM @@ -545,16 +546,17 @@ 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, - 35, 36, 37 + 35, 36, 37, 38 }; #if YYDEBUG /* YYRLINE[YYN] -- Source line where rule number YYN was defined. */ static const yytype_int8 yyrline[] = { - 0, 36, 36, 36, 38, 38, 38, 38, 40, 40, - 40, 40, 40, 40, 40, 40, 42, 42, 51, 51, - 59, 59, 61, 64, 67, 70, 73, 76, 79, 82 + 0, 23, 23, 23, 25, 25, 25, 25, 27, 27, + 27, 27, 27, 27, 27, 27, 29, 29, 31, 31, + 40, 40, 48, 48, 50, 50, 53, 56, 59, 62, + 65, 68, 71, 74, 77, 80 }; #endif @@ -563,14 +565,15 @@ First, the terminals, then, starting at YYNTOKENS, nonterminals. */ static const char *const yytname[] = { - "$end", "error", "$undefined", "CHIP", "DEVICE", "REGISTER", "BOOL", - "STATUS", "MANDATORY", "BUS", "RESOURCE", "END", "EQUALS", "HEX", + "$end", "error", "$undefined", "CHIP", "DEVICE", "CONFIG", "REGISTER", + "BOOL", "STATUS", "MANDATORY", "BUS", "RESOURCE", "END", "EQUALS", "HEX", "STRING", "PCI", "PNP", "I2C", "APIC", "CPU_CLUSTER", "CPU", "DOMAIN", "IRQ", "DRQ", "SLOT_DESC", "IO", "NUMBER", "SUBSYSTEMID", "INHERIT", "IOAPIC_IRQ", "IOAPIC", "PCIINT", "GENERIC", "SPI", "USB", "MMIO", "LPC", "ESPI", "$accept", "devtree", "$@1", "chipchildren", "devicechildren", - "chip", "@2", "device", "@3", "status", "resource", "registers", - "subsystemid", "ioapic_irq", "smbios_slot_desc", YY_NULLPTR + "settings", "chip", "@2", "device", "@3", "status", "config", "$@4", + "setting", "resource", "registers", "subsystemid", "ioapic_irq", + "smbios_slot_desc", YY_NULLPTR }; #endif @@ -582,11 +585,11 @@ 0, 256, 257, 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, - 285, 286, 287, 288, 289, 290, 291, 292 + 285, 286, 287, 288, 289, 290, 291, 292, 293 }; # endif -#define YYPACT_NINF (-10) +#define YYPACT_NINF (-16) #define yypact_value_is_default(Yyn) \ ((Yyn) == YYPACT_NINF) @@ -600,11 +603,13 @@ STATE-NUM. */ static const yytype_int8 yypact[] = { - -10, 11, 10, -10, 0, -10, -10, -10, 1, 6, - 2, -10, -10, -10, -10, -9, 8, 3, 4, -10, - -10, -10, -10, -10, -3, -4, -10, 9, -1, 5, - -10, -10, -10, -10, -10, -10, -10, 15, 14, 7, - -2, 12, 16, 13, 17, -10, 18, -10, -10, -10 + -16, 6, 7, -16, 2, -16, -16, -16, 1, 9, + 3, -16, -16, -16, -16, -15, 10, 8, 5, -16, + -16, -16, -16, 19, 11, -16, -16, -3, 13, 4, + -16, 14, 12, 15, -16, -16, -16, -16, -16, -16, + -16, 17, -1, -16, 20, 21, 16, 0, 22, -16, + -16, 18, 23, 24, 25, -16, -16, 26, -16, -16, + -16 }; /* YYDEFACT[STATE-NUM] -- Default reduction number in state STATE-NUM. @@ -612,25 +617,27 @@ means the default is an error. */ static const yytype_int8 yydefact[] = { - 2, 0, 0, 1, 0, 3, 16, 7, 0, 0, - 0, 17, 5, 4, 6, 0, 0, 0, 0, 20, - 21, 18, 23, 15, 0, 0, 19, 0, 0, 0, - 9, 8, 10, 14, 11, 12, 13, 0, 0, 0, - 0, 0, 29, 24, 0, 22, 28, 25, 26, 27 + 2, 0, 0, 1, 0, 3, 18, 7, 0, 0, + 0, 19, 5, 4, 6, 0, 0, 0, 0, 22, + 23, 20, 29, 26, 0, 15, 24, 0, 0, 0, + 21, 0, 0, 0, 9, 8, 10, 14, 11, 12, + 13, 0, 0, 17, 0, 0, 0, 0, 0, 25, + 16, 0, 35, 30, 0, 27, 28, 34, 31, 32, + 33 }; /* YYPGOTO[NTERM-NUM]. */ static const yytype_int8 yypgoto[] = { - -10, -10, -10, -10, -10, -5, -10, 20, -10, -10, - -10, 21, -10, -10, -10 + -16, -16, -16, -16, -16, -16, -6, -16, 27, -16, + -16, -16, -16, -8, -16, 28, -16, -16, -16 }; /* YYDEFGOTO[NTERM-NUM]. */ static const yytype_int8 yydefgoto[] = { - -1, 1, 2, 8, 24, 5, 7, 13, 23, 21, - 32, 14, 34, 35, 36 + -1, 1, 2, 8, 27, 42, 5, 7, 13, 23, + 21, 25, 28, 43, 36, 14, 38, 39, 40 }; /* YYTABLE[YYPACT[STATE-NUM]] -- What to do in state STATE-NUM. If @@ -638,47 +645,53 @@ number is the opposite. If YYTABLE_NINF, syntax error. */ static const yytype_int8 yytable[] = { - 4, 9, 10, 12, 4, 9, 10, 25, 26, 19, - 20, 3, 11, 4, 6, 15, 16, 17, 22, 30, - 18, 27, 37, 38, 28, 39, 29, 41, 42, 44, - 46, 40, 49, 43, 0, 0, 0, 0, 45, 0, - 0, 47, 0, 48, 31, 33 + 4, 9, 12, 10, 4, 9, 3, 10, 29, 30, + 4, 49, 17, 11, 41, 19, 20, 6, 16, 15, + 22, 34, 31, 18, 24, 32, 26, 33, 41, 45, + 48, 44, 54, 51, 50, 0, 52, 55, 57, 46, + 0, 60, 47, 53, 0, 56, 0, 0, 0, 0, + 0, 0, 59, 58, 35, 37 }; static const yytype_int8 yycheck[] = { - 3, 4, 5, 8, 3, 4, 5, 10, 11, 6, - 7, 0, 11, 3, 14, 9, 14, 26, 14, 24, - 12, 24, 26, 14, 27, 26, 29, 12, 14, 31, - 14, 26, 14, 26, -1, -1, -1, -1, 26, -1, - -1, 28, -1, 26, 24, 24 + 3, 4, 8, 6, 3, 4, 0, 6, 11, 12, + 3, 12, 27, 12, 15, 7, 8, 15, 15, 10, + 15, 27, 25, 13, 5, 28, 15, 30, 15, 15, + 13, 27, 32, 13, 42, -1, 15, 15, 15, 27, + -1, 15, 27, 27, -1, 27, -1, -1, -1, -1, + -1, -1, 27, 29, 27, 27 }; /* YYSTOS[STATE-NUM] -- The (internal number of the) accessing symbol of state STATE-NUM. */ static const yytype_int8 yystos[] = { - 0, 39, 40, 0, 3, 43, 14, 44, 41, 4, - 5, 11, 43, 45, 49, 9, 14, 26, 12, 6, - 7, 47, 14, 46, 42, 10, 11, 24, 27, 29, - 43, 45, 48, 49, 50, 51, 52, 26, 14, 26, - 26, 12, 14, 26, 31, 26, 14, 28, 26, 14 + 0, 40, 41, 0, 3, 45, 15, 46, 42, 4, + 6, 12, 45, 47, 54, 10, 15, 27, 13, 7, + 8, 49, 15, 48, 5, 50, 15, 43, 51, 11, + 12, 25, 28, 30, 45, 47, 53, 54, 55, 56, + 57, 15, 44, 52, 27, 15, 27, 27, 13, 12, + 52, 13, 15, 27, 32, 15, 27, 15, 29, 27, + 15 }; /* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */ static const yytype_int8 yyr1[] = { - 0, 38, 40, 39, 41, 41, 41, 41, 42, 42, - 42, 42, 42, 42, 42, 42, 44, 43, 46, 45, - 47, 47, 48, 49, 50, 50, 51, 52, 52, 52 + 0, 39, 41, 40, 42, 42, 42, 42, 43, 43, + 43, 43, 43, 43, 43, 43, 44, 44, 46, 45, + 48, 47, 49, 49, 51, 50, 50, 52, 53, 54, + 55, 55, 56, 57, 57, 57 }; /* YYR2[YYN] -- Number of symbols on the right hand side of rule YYN. */ static const yytype_int8 yyr2[] = { 0, 2, 0, 2, 2, 2, 2, 0, 2, 2, - 2, 2, 2, 2, 2, 0, 0, 5, 0, 7, - 1, 1, 4, 4, 3, 4, 4, 5, 4, 3 + 2, 2, 2, 2, 2, 0, 2, 1, 0, 5, + 0, 8, 1, 1, 0, 5, 0, 3, 4, 4, + 3, 4, 4, 5, 4, 3 }; @@ -1377,7 +1390,7 @@ { cur_parent = root_parent; } break; - case 16: + case 18: { (yyval.chip_instance) = new_chip_instance((yyvsp[0].string)); chip_enqueue_tail(cur_chip_instance); @@ -1385,54 +1398,64 @@ } break; - case 17: + case 19: { cur_chip_instance = chip_dequeue_tail(); } break; - case 18: + case 20: { (yyval.dev) = new_device(cur_parent, cur_chip_instance, (yyvsp[-2].number), (yyvsp[-1].string), (yyvsp[0].number)); cur_parent = (yyval.dev)->last_bus; } break; - case 19: - { - cur_parent = (yyvsp[-2].dev)->parent; + case 21: + { + cur_parent = (yyvsp[-3].dev)->parent; } break; - case 22: - { add_resource(cur_parent, (yyvsp[-3].number), strtol((yyvsp[-2].string), NULL, 0), strtol((yyvsp[0].string), NULL, 0)); } - break; - - case 23: - { add_register(cur_chip_instance, (yyvsp[-2].string), (yyvsp[0].string)); } - break; - case 24: - { add_pci_subsystem_ids(cur_parent, strtol((yyvsp[-1].string), NULL, 16), strtol((yyvsp[0].string), NULL, 16), 0); } - break; - - case 25: - { add_pci_subsystem_ids(cur_parent, strtol((yyvsp[-2].string), NULL, 16), strtol((yyvsp[-1].string), NULL, 16), 1); } - break; - - case 26: - { add_ioapic_info(cur_parent, strtol((yyvsp[-2].string), NULL, 16), (yyvsp[-1].string), strtol((yyvsp[0].string), NULL, 16)); } + { + set_config_path(cur_parent, (yyvsp[0].string)); +} break; case 27: - { add_slot_desc(cur_parent, (yyvsp[-3].string), (yyvsp[-2].string), (yyvsp[-1].string), (yyvsp[0].string)); } + { add_setting(cur_parent, (yyvsp[-2].string), (yyvsp[0].string)); } break; case 28: - { add_slot_desc(cur_parent, (yyvsp[-2].string), (yyvsp[-1].string), (yyvsp[0].string), NULL); } + { add_resource(cur_parent, (yyvsp[-3].number), strtol((yyvsp[-2].string), NULL, 0), strtol((yyvsp[0].string), NULL, 0)); } break; case 29: + { add_register(cur_chip_instance, (yyvsp[-2].string), (yyvsp[0].string)); } + break; + + case 30: + { add_pci_subsystem_ids(cur_parent, strtol((yyvsp[-1].string), NULL, 16), strtol((yyvsp[0].string), NULL, 16), 0); } + break; + + case 31: + { add_pci_subsystem_ids(cur_parent, strtol((yyvsp[-2].string), NULL, 16), strtol((yyvsp[-1].string), NULL, 16), 1); } + break; + + case 32: + { add_ioapic_info(cur_parent, strtol((yyvsp[-2].string), NULL, 16), (yyvsp[-1].string), strtol((yyvsp[0].string), NULL, 16)); } + break; + + case 33: + { add_slot_desc(cur_parent, (yyvsp[-3].string), (yyvsp[-2].string), (yyvsp[-1].string), (yyvsp[0].string)); } + break; + + case 34: + { add_slot_desc(cur_parent, (yyvsp[-2].string), (yyvsp[-1].string), (yyvsp[0].string), NULL); } + break; + + case 35: { add_slot_desc(cur_parent, (yyvsp[-1].string), (yyvsp[0].string), NULL, NULL); } break; diff --git a/util/sconfig/sconfig.tab.h_shipped b/util/sconfig/sconfig.tab.h_shipped index 5fa9d19..cb68de9 100644 --- a/util/sconfig/sconfig.tab.h_shipped +++ b/util/sconfig/sconfig.tab.h_shipped @@ -34,8 +34,8 @@ /* Undocumented macros, especially those whose name start with YY_, are private implementation details. Do not rely on them. */ -#ifndef YY_YY_HOME_ME_REPOS_COREBOOTORG_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED -# define YY_YY_HOME_ME_REPOS_COREBOOTORG_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED +#ifndef YY_YY_HOME_ICON_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED +# define YY_YY_HOME_ICON_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED /* Debug traces. */ #ifndef YYDEBUG # define YYDEBUG 0 @@ -51,39 +51,40 @@ { CHIP = 258, DEVICE = 259, - REGISTER = 260, - BOOL = 261, - STATUS = 262, - MANDATORY = 263, - BUS = 264, - RESOURCE = 265, - END = 266, - EQUALS = 267, - HEX = 268, - STRING = 269, - PCI = 270, - PNP = 271, - I2C = 272, - APIC = 273, - CPU_CLUSTER = 274, - CPU = 275, - DOMAIN = 276, - IRQ = 277, - DRQ = 278, - SLOT_DESC = 279, - IO = 280, - NUMBER = 281, - SUBSYSTEMID = 282, - INHERIT = 283, - IOAPIC_IRQ = 284, - IOAPIC = 285, - PCIINT = 286, - GENERIC = 287, - SPI = 288, - USB = 289, - MMIO = 290, - LPC = 291, - ESPI = 292 + CONFIG = 260, + REGISTER = 261, + BOOL = 262, + STATUS = 263, + MANDATORY = 264, + BUS = 265, + RESOURCE = 266, + END = 267, + EQUALS = 268, + HEX = 269, + STRING = 270, + PCI = 271, + PNP = 272, + I2C = 273, + APIC = 274, + CPU_CLUSTER = 275, + CPU = 276, + DOMAIN = 277, + IRQ = 278, + DRQ = 279, + SLOT_DESC = 280, + IO = 281, + NUMBER = 282, + SUBSYSTEMID = 283, + INHERIT = 284, + IOAPIC_IRQ = 285, + IOAPIC = 286, + PCIINT = 287, + GENERIC = 288, + SPI = 289, + USB = 290, + MMIO = 291, + LPC = 292, + ESPI = 293 }; #endif @@ -109,4 +110,4 @@ int yyparse (void); -#endif /* !YY_YY_HOME_ME_REPOS_COREBOOTORG_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED */ +#endif /* !YY_YY_HOME_ICON_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED */ diff --git a/util/sconfig/sconfig.y b/util/sconfig/sconfig.y index 161cf81..defa96f 100755 --- a/util/sconfig/sconfig.y +++ b/util/sconfig/sconfig.y @@ -18,7 +18,7 @@ int number; } -%token CHIP DEVICE REGISTER BOOL STATUS MANDATORY BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC CPU_CLUSTER CPU DOMAIN IRQ DRQ SLOT_DESC IO NUMBER SUBSYSTEMID INHERIT IOAPIC_IRQ IOAPIC PCIINT GENERIC SPI USB MMIO LPC ESPI +%token CHIP DEVICE CONFIG REGISTER BOOL STATUS MANDATORY BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC CPU_CLUSTER CPU DOMAIN IRQ DRQ SLOT_DESC IO NUMBER SUBSYSTEMID INHERIT IOAPIC_IRQ IOAPIC PCIINT GENERIC SPI USB MMIO LPC ESPI %% devtree: { cur_parent = root_parent; } chip; @@ -26,6 +26,8 @@ devicechildren: devicechildren device | devicechildren chip | devicechildren resource | devicechildren subsystemid | devicechildren ioapic_irq | devicechildren smbios_slot_desc | devicechildren registers | /* empty */ ; +settings: settings setting | setting; + chip: CHIP STRING /* == path */ { $<chip_instance>$ = new_chip_instance($<string>2); chip_enqueue_tail(cur_chip_instance); @@ -39,12 +41,21 @@ $<dev>$ = new_device(cur_parent, cur_chip_instance, $<number>2, $<string>3, $<number>4); cur_parent = $<dev>$->last_bus; } - devicechildren END { + config devicechildren END { cur_parent = $<dev>5->parent; }; status: BOOL | STATUS ; +config: CONFIG STRING /* == path */ { + set_config_path(cur_parent, $<string>2); +} + settings END | /* empty */ +; + +setting: STRING /* == identifier */ EQUALS STRING /* == value */ + { add_setting(cur_parent, $<string>1, $<string>3); } ; + resource: RESOURCE NUMBER /* == resnum */ EQUALS NUMBER /* == resval */ { add_resource(cur_parent, $<number>1, strtol($<string>2, NULL, 0), strtol($<string>4, NULL, 0)); } ; -- To view, visit https://review.coreboot.org/c/coreboot/+/41745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25f46e774bb6d26d0e6b77f9bd96d80581412655 Gerrit-Change-Number: 41745 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 8

Change in coreboot[master]: nb/intel/sandybridge/gma.c: Fix lock bits setting
by Evgeny Zinoviev (Code Review) 07 Aug '23

07 Aug '23

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42447 ) Change subject: nb/intel/sandybridge/gma.c: Fix lock bits setting ...................................................................... nb/intel/sandybridge/gma.c: Fix lock bits setting PM lock bits are set too early at the moment. Set them after enabling PM interrupts. Change-Id: I3a16e1ce1236597faad42f3812b2b8d2b5417efd Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M src/northbridge/intel/sandybridge/gma.c 1 file changed, 23 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/42447/1 diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index fee7513..8fe2de8 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -42,7 +42,7 @@ { 0xa23c, 0x0817fe19 }, { 0xa240, 0x00000000 }, { 0xa244, 0x00000000 }, - { 0xa248, 0x8000421e }, + { 0xa248, 0x0000421e }, { 0 }, }; @@ -65,7 +65,7 @@ { 0xa23c, 0x002a002b }, { 0xa240, 0x00000000 }, { 0xa244, 0x00000000 }, - { 0xa248, 0x8000421e }, + { 0xa248, 0x0000421e }, { 0 }, }; @@ -373,23 +373,20 @@ } /* 3: Gear ratio map */ - gtt_write(0xa004, 0x00000010); + gtt_write(0xa004, 0x00000000); /* 4: GFXPAUSE */ gtt_write(0xa000, 0x00070020); - /* 5: Dynamic EU trip control */ - gtt_write(0xa080, 0x00000004); - - /* 6: ECO bits */ + /* 5: ECO bits */ reg32 = gtt_read(0xa180); - reg32 |= (1 << 26) | (1 << 31); + reg32 |= (1 << 26); /* (bit 20=1 for SNB step D1+ / IVB A0+) */ if (bridge_silicon_revision() >= SNB_STEP_D1) reg32 |= (1 << 20); gtt_write(0xa180, reg32); - /* 6a: for SnB step D2+ only */ + /* 5a: for SnB step D2+ only */ if (((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) && (bridge_silicon_revision() >= SNB_STEP_D2)) { reg32 = gtt_read(0x9400); @@ -408,14 +405,14 @@ reg32 |= (1 << 16); gtt_write(0x907c, reg32); - /* 6b: Clocking reset controls */ + /* 5b: Clocking reset controls */ gtt_write(0x9424, 0x00000001); } else { - /* 6b: Clocking reset controls */ + /* 5b: Clocking reset controls */ gtt_write(0x9424, 0x00000000); } - /* 7 */ + /* 6 */ if (gtt_poll(0x138124, (1 << 31), (0 << 31))) { gtt_write(0x138128, 0x00000029); /* Mailbox Data */ gtt_write(0x138124, 0x80000004); /* Mailbox Cmd for RC6 VID */ @@ -424,7 +421,7 @@ gtt_poll(0x138124, (1 << 31), (0 << 31)); } - /* 8 */ + /* 7 */ gtt_write(0xa090, 0x00000000); /* RC Control */ gtt_write(0xa098, 0x03e80000); /* RC1e Wake Rate Limit */ gtt_write(0xa09c, 0x0028001e); /* RC6/6p Wake Rate Limit */ @@ -432,19 +429,19 @@ gtt_write(0xa0a8, 0x0001e848); /* RC Evaluation Interval */ gtt_write(0xa0ac, 0x00000019); /* RC Idle Hysteresis */ - /* 9 */ + /* 8 */ gtt_write(0x2054, 0x0000000a); /* Render Idle Max Count */ gtt_write(0x12054,0x0000000a); /* Video Idle Max Count */ gtt_write(0x22054,0x0000000a); /* Blitter Idle Max Count */ - /* 10 */ + /* 9 */ gtt_write(0xa0b0, 0x00000000); /* Unblock Ack to Busy */ gtt_write(0xa0b4, 0x000003e8); /* RC1e Threshold */ gtt_write(0xa0b8, 0x0000c350); /* RC6 Threshold */ gtt_write(0xa0bc, 0x000186a0); /* RC6p Threshold */ gtt_write(0xa0c0, 0x0000fa00); /* RC6pp Threshold */ - /* 11 */ + /* 10 */ gtt_write(0xa010, 0x000f4240); /* RP Down Timeout */ gtt_write(0xa014, 0x12060000); /* RP Interrupt Limits */ gtt_write(0xa02c, 0x00015f90); /* RP Up Threshold */ @@ -454,7 +451,7 @@ gtt_write(0xa070, 0x0000000a); /* RP Idle Hysteresis */ /* - * 11a: Enable Render Standby (RC6) + * 10a: Enable Render Standby (RC6) * * IvyBridge should also support DeepRenderStandby. * @@ -463,7 +460,7 @@ */ gtt_write(0xa090, 0x88040000); /* HW RC Control */ - /* 12: Normal Frequency Request */ + /* 11: Normal Frequency Request */ /* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 */ /* only the lower 7 bits are used and shifted left by 25 */ reg32 = MCHBAR32(0x5998); @@ -472,12 +469,18 @@ reg32 <<= 25; gtt_write(0xa008, reg32); - /* 13: RP Control */ + /* 12: RP Control */ gtt_write(0xa024, 0x00000592); - /* 14: Enable PM Interrupts */ + /* 13: Enable PM Interrupts */ gtt_write(0x4402c, 0x03000076); + /* 14: PM Lock Settings */ + gtt_write(0xa248, gtt_read(0xa248) | (1 << 31)); + gtt_write(0xa004, gtt_read(0xa004) | (1 << 4)); + gtt_write(0xa080, gtt_read(0xa080) | (1 << 2)); + gtt_write(0xa180, gtt_read(0xa180) | (1 << 31)); + /* Clear 0x6c024 [8:6] */ reg32 = gtt_read(0x6c024); reg32 &= ~0x000001c0; -- To view, visit https://review.coreboot.org/c/coreboot/+/42447 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a16e1ce1236597faad42f3812b2b8d2b5417efd Gerrit-Change-Number: 42447 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/lapic_def.h: Drop unused macros
by Angel Pons (Code Review) 07 Aug '23

07 Aug '23

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42454 ) Change subject: cpu/x86/lapic_def.h: Drop unused macros ...................................................................... cpu/x86/lapic_def.h: Drop unused macros These macros are unused and rather confusing to use. Get rid of them. Change-Id: I435411e46361dc62a40965b7fb77421a4212724a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/include/cpu/x86/lapic_def.h 1 file changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/42454/1 diff --git a/src/include/cpu/x86/lapic_def.h b/src/include/cpu/x86/lapic_def.h index 9da89ee..934c86c 100644 --- a/src/include/cpu/x86/lapic_def.h +++ b/src/include/cpu/x86/lapic_def.h @@ -52,14 +52,11 @@ #define LAPIC_DM_EXTINT 0x00700 #define LAPIC_VECTOR_MASK 0x000FF #define LAPIC_ICR2 0x310 -#define GET_LAPIC_DEST_FIELD(x) (((x)>>24)&0xFF) #define SET_LAPIC_DEST_FIELD(x) ((x)<<24) #define LAPIC_LVTT 0x320 #define LAPIC_LVTPC 0x340 #define LAPIC_LVT0 0x350 #define LAPIC_LVT_TIMER_BASE_MASK (0x3<<18) -#define GET_LAPIC_TIMER_BASE(x) (((x)>>18)&0x3) -#define SET_LAPIC_TIMER_BASE(x) (((x)<<18)) #define LAPIC_TIMER_BASE_CLKIN 0x0 #define LAPIC_TIMER_BASE_TMBASE 0x1 #define LAPIC_TIMER_BASE_DIV 0x2 @@ -74,8 +71,6 @@ #define LAPIC_DELIVERY_MODE_FIXED (0<<8) #define LAPIC_DELIVERY_MODE_NMI (4<<8) #define LAPIC_DELIVERY_MODE_EXTINT (7<<8) -#define GET_LAPIC_DELIVERY_MODE(x) (((x)>>8)&0x7) -#define SET_LAPIC_DELIVERY_MODE(x, y) (((x)&~0x700)|((y)<<8)) #define LAPIC_MODE_FIXED 0x0 #define LAPIC_MODE_NMI 0x4 #define LAPIC_MODE_EXINT 0x7 -- To view, visit https://review.coreboot.org/c/coreboot/+/42454 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I435411e46361dc62a40965b7fb77421a4212724a Gerrit-Change-Number: 42454 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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