coreboot-gerrit February 2022

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Change in coreboot[master]: sb/intel/bd82x6x: Use common AHCI library
by Angel Pons (Code Review) 07 Aug '23

07 Aug '23

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47100 ) Change subject: sb/intel/bd82x6x: Use common AHCI library ...................................................................... sb/intel/bd82x6x: Use common AHCI library Behaviour before after this patch should be equivalent. Change-Id: Ib1679197c77c5b32c231fd51dd7465a3ebb1d7bd Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/sata.c 1 file changed, 34 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/47100/1 diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 875f3f7..87aa841 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -8,6 +8,7 @@ #include <device/pci_ids.h> #include <option.h> #include <acpi/acpi_sata.h> +#include <southbridge/intel/common/ahci.h> #include <types.h> #include "chip.h" @@ -113,8 +114,6 @@ /* AHCI */ if (sata_mode == 0) { - u8 *abar; - printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE); @@ -130,32 +129,42 @@ pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183); /* Initialize AHCI memory-mapped space */ - abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); - printk(BIOS_DEBUG, "ABAR: %p\n", abar); - /* CAP (HBA Capabilities) : enable power management */ - reg32 = read32(abar + 0x00); - reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS - reg32 &= ~0x00020060; // clear SXS+EMS+PMS - /* Set ISS, if available */ + const uintptr_t ahci_bar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); + printk(BIOS_DEBUG, "AHCI BAR: %p\n", (void *)ahci_bar); + + union ahci_reg_cap ahci_cap = { + .raw = ahci_read32(ahci_bar, AHCI_REG_CAP), + }; + + ahci_cap.external_sata = 0; /* Should be configurable */ + ahci_cap.enclosure_management = 0; + ahci_cap.port_multiplier = 0; + + ahci_cap.partial_state = 1; + ahci_cap.slumber_state = 1; + ahci_cap.aggressive_link_pm = 1; + ahci_cap.staggered_spinup = 1; + + /* If configured, override ISS */ if (config->sata_interface_speed_support) - { - reg32 &= ~0x00f00000; - reg32 |= (config->sata_interface_speed_support & 0x03) - << 20; - } - write32(abar + 0x00, reg32); - /* PI (Ports implemented) */ - write32(abar + 0x0c, config->sata_port_map); - (void) read32(abar + 0x0c); /* Read back 1 */ - (void) read32(abar + 0x0c); /* Read back 2 */ - /* CAP2 (HBA Capabilities Extended)*/ - reg32 = read32(abar + 0x24); - reg32 &= ~0x00000002; - write32(abar + 0x24, reg32); + ahci_cap.interface_speed = config->sata_interface_speed_support; + + ahci_write32(ahci_bar, AHCI_REG_CAP, ahci_cap.raw); + + ahci_write_ports_implemented(ahci_bar, config->sata_port_map); + + union ahci_reg_cap_2 ahci_cap_2 = { + .raw = ahci_read32(ahci_bar, AHCI_REG_CAP_2), + }; + + ahci_cap_2.nvm_hci_present = 0; + + ahci_write32(ahci_bar, AHCI_REG_CAP_2, ahci_cap_2.raw); + /* VSP (Vendor Specific Register */ - reg32 = read32(abar + 0xa0); + reg32 = ahci_read32(ahci_bar, 0xa0); reg32 &= ~0x00000005; - write32(abar + 0xa0, reg32); + ahci_write32(ahci_bar, 0xa0, reg32); } else { /* IDE */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1679197c77c5b32c231fd51dd7465a3ebb1d7bd Gerrit-Change-Number: 47100 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/bd82x6x/sata.c: Simplify RMW operations
by Angel Pons (Code Review) 07 Aug '23

07 Aug '23

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47106 ) Change subject: sb/intel/bd82x6x/sata.c: Simplify RMW operations ...................................................................... sb/intel/bd82x6x/sata.c: Simplify RMW operations Introduce the `sir_unset_and_set_mask` helper and simplify a PCI register update to not use an intermediate variable. Change-Id: Ibb33aef755bba1ae48e6029fcab0687d9faf62b4 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/sata.c 1 file changed, 13 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/47106/1 diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 2b46cfa..a83dd63 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -28,6 +28,14 @@ pci_write_config32(dev, SATA_SIRD, value); } +static inline void sir_unset_and_set_mask(struct device *dev, int idx, u32 unset, u32 set) +{ + pci_write_config32(dev, SATA_SIRI, idx); + + const u32 value = pci_read_config32(dev, SATA_SIRD) & ~unset; + pci_write_config32(dev, SATA_SIRD, value | set); +} + static void sata_read_resources(struct device *dev) { struct resource *res; @@ -90,7 +98,6 @@ static void sata_init(struct device *dev) { u32 reg32; - u16 reg16; /* Get the chip configuration */ config_t *config = dev->chip_info; u8 sata_mode; @@ -120,10 +127,8 @@ pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE); /* for AHCI, Port Enable is managed in memory mapped space */ - reg16 = pci_read_config16(dev, 0x92); - reg16 &= ~0x3f; /* 6 ports SKU + ORM */ - reg16 |= 0x8000 | config->sata_port_map; - pci_write_config16(dev, 0x92, reg16); + /* Port enable + OOB retry mode */ + pci_update_config16(dev, 0x92, ~0x3f, config->sata_port_map | 0x8000); /* SATA Initialization register */ pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183); @@ -204,19 +209,10 @@ /* Additional Programming Requirements */ sir_write(dev, 0x04, 0x00001600); sir_write(dev, 0x28, 0xa0000033); - reg32 = sir_read(dev, 0x54); - reg32 &= 0xff000000; - reg32 |= 0x5555aa; - sir_write(dev, 0x54, reg32); + sir_unset_and_set_mask(dev, 0x54, 0xffffff, 0x5555aa); sir_write(dev, 0x64, 0xcccc8484); - reg32 = sir_read(dev, 0x68); - reg32 &= 0xffff0000; - reg32 |= 0xcccc; - sir_write(dev, 0x68, reg32); - reg32 = sir_read(dev, 0x78); - reg32 &= 0x0000ffff; - reg32 |= 0x88880000; - sir_write(dev, 0x78, reg32); + sir_unset_and_set_mask(dev, 0x68, 0xffff, 0xcccc); + sir_unset_and_set_mask(dev, 0x78, 0xffff0000, 0x88880000); sir_write(dev, 0x84, 0x001c7000); sir_write(dev, 0x88, 0x88338822); sir_write(dev, 0xa0, 0x001c7000); -- To view, visit https://review.coreboot.org/c/coreboot/+/47106 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb33aef755bba1ae48e6029fcab0687d9faf62b4 Gerrit-Change-Number: 47106 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/ibexpeak: Use common AHCI library
by Angel Pons (Code Review) 07 Aug '23

07 Aug '23

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47865 ) Change subject: sb/intel/ibexpeak: Use common AHCI library ...................................................................... sb/intel/ibexpeak: Use common AHCI library Behaviour before after this patch should be equivalent. Change-Id: I9b636f093dfaa5954667fe0198e6602e8c1e4943 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/ibexpeak/sata.c 1 file changed, 37 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/47865/1 diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 2c6b0ca..20458f5 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -8,6 +8,7 @@ #include <device/pci_ids.h> #include <option.h> #include <acpi/acpi_sata.h> +#include <southbridge/intel/common/ahci.h> #include <types.h> #include "chip.h" @@ -53,9 +54,6 @@ PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); if (sata_mode == 0) { - /* AHCI */ - u32 *abar; - printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); /* Set Interrupt Line */ @@ -80,31 +78,43 @@ pci_write_config32(dev, 0x98, 0x00590200); /* Initialize AHCI memory-mapped space */ - abar = (u32 *)(uintptr_t)pci_read_config32(dev, PCI_BASE_ADDRESS_5); - printk(BIOS_DEBUG, "ABAR: %p\n", abar); - /* CAP (HBA Capabilities) : enable power management */ - reg32 = read32(abar + 0x00); - reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS - reg32 &= ~0x00020060; // clear SXS+EMS+PMS - /* Set ISS, if available */ - if (config->sata_interface_speed_support) { - reg32 &= ~0x00f00000; - reg32 |= (config->sata_interface_speed_support & 0x03) - << 20; - } - write32(abar + 0x00, reg32); - /* PI (Ports implemented) */ - write32(abar + 0x03, config->sata_port_map); - (void)read32(abar + 0x03); /* Read back 1 */ - (void)read32(abar + 0x03); /* Read back 2 */ - /* CAP2 (HBA Capabilities Extended) */ - reg32 = read32(abar + 0x09); - reg32 &= ~0x00000002; - write32(abar + 0x09, reg32); - /* VSP (Vendor Specific Register */ - reg32 = read32(abar + 0x28); + const uintptr_t ahci_bar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); + printk(BIOS_DEBUG, "AHCI BAR: %p\n", (void *)ahci_bar); + + union ahci_reg_cap ahci_cap = { + .raw = ahci_read32(ahci_bar, AHCI_REG_CAP), + }; + + ahci_cap.external_sata = 0; /* TODO: Make this configurable? */ + ahci_cap.enclosure_management = 0; + ahci_cap.port_multiplier = 0; + + ahci_cap.partial_state = 1; + ahci_cap.slumber_state = 1; + ahci_cap.aggressive_link_pm = 1; + ahci_cap.staggered_spinup = 1; + + /* If configured, override ISS */ + if (config->sata_interface_speed_support) + ahci_cap.interface_speed = config->sata_interface_speed_support; + + ahci_write32(ahci_bar, AHCI_REG_CAP, ahci_cap.raw); + + ahci_write_ports_implemented(ahci_bar, config->sata_port_map); + + union ahci_reg_cap_2 ahci_cap_2 = { + .raw = ahci_read32(ahci_bar, AHCI_REG_CAP_2), + }; + + ahci_cap_2.nvm_hci_present = 0; + + ahci_write32(ahci_bar, AHCI_REG_CAP_2, ahci_cap_2.raw); + + /* VSP (Vendor Specific Register) */ + reg32 = ahci_read32(ahci_bar, 0xa0); reg32 &= ~0x00000005; - write32(abar + 0x28, reg32); + ahci_write32(ahci_bar, 0xa0, reg32); + } else { /* IDE */ printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/47865 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b636f093dfaa5954667fe0198e6602e8c1e4943 Gerrit-Change-Number: 47865 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/ibexpeak: Simplify SATA RMW operations
by Angel Pons (Code Review) 07 Aug '23

07 Aug '23

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47888 ) Change subject: sb/intel/ibexpeak: Simplify SATA RMW operations ...................................................................... sb/intel/ibexpeak: Simplify SATA RMW operations Change-Id: I115cb45b7573c8c9057ad0b7951cd0b3a79a1200 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/ibexpeak/sata.c 1 file changed, 4 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/47888/1 diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 20458f5..2072730 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -31,7 +31,6 @@ static void sata_init(struct device *dev) { u32 reg32; - u16 reg16; /* Get the chip configuration */ config_t *config = dev->chip_info; u8 sata_mode; @@ -65,10 +64,8 @@ pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE); /* for AHCI, Port Enable is managed in memory mapped space */ - reg16 = pci_read_config16(dev, 0x92); - reg16 &= ~0x3f; /* 6 ports SKU + ORM */ - reg16 |= 0x8100 | config->sata_port_map; - pci_write_config16(dev, 0x92, reg16); + /* 6 ports SKU + ORM */ + pci_update_config16(dev, 0x92, ~0x3f, 0x8100 | config->sata_port_map); /* SATA Initialization register */ pci_write_config32(dev, 0x94, @@ -123,9 +120,7 @@ pci_write_config32(dev, 0x24, 0x00000000); /* And without AHCI BAR no memory decoding */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~PCI_COMMAND_MEMORY; - pci_write_config16(dev, PCI_COMMAND, reg16); + pci_and_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MEMORY); /* Native mode capable on both primary and secondary (0xa) * or'ed with enabled (0x50) = 0xf @@ -141,10 +136,7 @@ pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE); /* Port enable */ - reg16 = pci_read_config16(dev, 0x92); - reg16 &= ~0x3f; - reg16 |= config->sata_port_map; - pci_write_config16(dev, 0x92, reg16); + pci_update_config16(dev, 0x92, ~0x3f, config->sata_port_map); /* SATA Initialization register */ pci_write_config32(dev, 0x94, -- To view, visit https://review.coreboot.org/c/coreboot/+/47888 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I115cb45b7573c8c9057ad0b7951cd0b3a79a1200 Gerrit-Change-Number: 47888 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: HACK: Enable PCIe refclk 100M
by Qizhong Cheng (Code Review) 07 Aug '23

07 Aug '23

Qizhong Cheng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48138 ) Change subject: HACK: Enable PCIe refclk 100M ...................................................................... HACK: Enable PCIe refclk 100M Don't pull into TOT. Thanks. A temporary patch for PCIe compliance test. Set GPIO65 pinmux for PCIe function which is clkreq#. Signed-off-by: mtk20626 <qizhong.cheng(a)mediatek.com> Change-Id: Ic4898a2b10c026a6d79b0f364c6a48e3f21c56ad --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/include/soc/pcie.h A src/soc/mediatek/mt8192/pcie.c 3 files changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/48138/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 37aa5f1..fca5b83 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -57,6 +57,7 @@ ramstage-y += spm.c ramstage-y += sspm.c ramstage-y += ufs.c +ramstage-y += pcie.c ramstage-y += ../common/mtlib.c ramstage-y += ../common/timer.c ramstage-y += ../common/uart.c diff --git a/src/soc/mediatek/mt8192/include/soc/pcie.h b/src/soc/mediatek/mt8192/include/soc/pcie.h new file mode 100644 index 0000000..dd8f7ab --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/pcie.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_PCIE_H +#define SOC_MEDIATEK_MT8192_PCIE_H + +void mtk_pcie_prepare(void); + +#endif diff --git a/src/soc/mediatek/mt8192/pcie.c b/src/soc/mediatek/mt8192/pcie.c new file mode 100644 index 0000000..d3e4213 --- /dev/null +++ b/src/soc/mediatek/mt8192/pcie.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/pcie.h> + +#define REG_PCIE_CLKREQ_EN (void *)(GPIO_BASE + 0x380) + +void mtk_pcie_prepare(void) +{ + u32 vaule; + + /* set PCIe clkreq# for refclk 100M */ + vaule = read32(REG_PCIE_CLKREQ_EN); + write32(REG_PCIE_CLKREQ_EN, vaule | 0x33); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/48138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4898a2b10c026a6d79b0f364c6a48e3f21c56ad Gerrit-Change-Number: 48138 Gerrit-PatchSet: 1 Gerrit-Owner: Qizhong Cheng <qizhong.cheng(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/kontron/mal10: Use explicit includes
by Felix Singer (Code Review) 07 Aug '23

07 Aug '23

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48145 ) Change subject: mb/kontron/mal10: Use explicit includes ...................................................................... mb/kontron/mal10: Use explicit includes Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Change-Id: I7b913da9ff085db7e6512d8714bfd2e5331e00bd --- M src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c M src/mainboard/kontron/mal10/include/variant/gpio.h M src/mainboard/kontron/mal10/variants/mal10/gpio.c 3 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/48145/1 diff --git a/src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c b/src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c index 674b209..0419f9d 100644 --- a/src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c +++ b/src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <carrier/gpio.h> +#include <gpio.h> static const struct pad_config gpio_table[] = { PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_0, DN_20K, DEEP, IGNORE, SAME), diff --git a/src/mainboard/kontron/mal10/include/variant/gpio.h b/src/mainboard/kontron/mal10/include/variant/gpio.h index ea942ca..ec53e4a 100644 --- a/src/mainboard/kontron/mal10/include/variant/gpio.h +++ b/src/mainboard/kontron/mal10/include/variant/gpio.h @@ -3,8 +3,6 @@ #ifndef MAL_10_CFG_GPIO_H #define MAL_10_CFG_GPIO_H -#include <gpio.h> - void variant_early_gpio_configure(void); #endif /* MAL_10_CFG_GPIO_H */ diff --git a/src/mainboard/kontron/mal10/variants/mal10/gpio.c b/src/mainboard/kontron/mal10/variants/mal10/gpio.c index 3986776..e81ba6b 100644 --- a/src/mainboard/kontron/mal10/variants/mal10/gpio.c +++ b/src/mainboard/kontron/mal10/variants/mal10/gpio.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <gpio.h> #include <variant/gpio.h> static const struct pad_config gpio_table[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/48145 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b913da9ff085db7e6512d8714bfd2e5331e00bd Gerrit-Change-Number: 48145 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/apollolake: Enable 2x refresh rate to mitigate RH vulnerabi...
by Marx Wang (Code Review) 07 Aug '23

07 Aug '23

Marx Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48510 ) Change subject: soc/intel/apollolake: Enable 2x refresh rate to mitigate RH vulnerability ...................................................................... soc/intel/apollolake: Enable 2x refresh rate to mitigate RH vulnerability We must enable 2x refresh rate in order to mitigate Row Hammer vulnerability. BUG=N/A TEST=run suspend_stress_test with memory check for 2500 cycles. Change-Id: I0235fc7906626f28f14367c283433e5b066cc89a --- M src/soc/intel/apollolake/meminit.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/48510/1 diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c index 8601571..9815a40 100644 --- a/src/soc/intel/apollolake/meminit.c +++ b/src/soc/intel/apollolake/meminit.c @@ -68,7 +68,7 @@ cfg->SliceHashMask = 0x9; cfg->InterleavedMode = 2; cfg->ChannelsSlicesEnable = 0; - cfg->MinRefRate2xEnable = 0; + cfg->MinRefRate2xEnable = 1; cfg->DualRankSupportEnable = 1; /* Don't enforce a memory size limit. */ cfg->MemorySizeLimit = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/48510 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0235fc7906626f28f14367c283433e5b066cc89a Gerrit-Change-Number: 48510 Gerrit-PatchSet: 1 Gerrit-Owner: Marx Wang <marx.wang(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [TEST] soc/intel/jasperlake: Add debug prints for Slope and Offset
by Sumeet R Pawnikar (Code Review) 07 Aug '23

07 Aug '23

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48661 ) Change subject: [TEST] soc/intel/jasperlake: Add debug prints for Slope and Offset ...................................................................... [TEST] soc/intel/jasperlake: Add debug prints for Slope and Offset Add debug prints for Imon Slope and Offset values for FiVR. Change-Id: I04bf6df711a3cd28b68e0f80bf94ff1f6a6e95a6 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/soc/intel/jasperlake/fsp_params.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/48661/1 diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index c03e9dd..855cfd9 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -183,6 +183,9 @@ params->ImonSlope[0] = config->ImonSlope; params->ImonOffset[0] = config->ImonOffset; + printk(BIOS_DEBUG, "DEBUG: Imon Slope=%d\n", config->ImonSlope); + printk(BIOS_DEBUG, "DEBUG: Imon Offset=%d\n", config->ImonOffset); + /* SDCard related configuration */ dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); params->ScsSdCardEnabled = is_dev_enabled(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/48661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04bf6df711a3cd28b68e0f80bf94ff1f6a6e95a6 Gerrit-Change-Number: 48661 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: HACK: Enable PCIe refclk 100M alone
by Qizhong Cheng (Code Review) 07 Aug '23

07 Aug '23

Qizhong Cheng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48724 ) Change subject: HACK: Enable PCIe refclk 100M alone ...................................................................... HACK: Enable PCIe refclk 100M alone Don't pull into TOT. Thanks. b/170703028 This patch is just to open the refclk of pcie during the coreboot stage for PCIe hardware compliance testing. If Alvis wants to continue to test pcie hardware, please cherry-pick the patch. Set GPIO65 pinmux for PCIe function which is clkreq#. Signed-off-by: mtk20626 <qizhong.cheng(a)mediatek.com> Change-Id: Ie0f73eda4259028efe1eacc7d6e3ed4c15bfb75f --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/include/soc/pcie.h A src/soc/mediatek/mt8192/pcie.c 3 files changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/48724/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 833dc2b..5e71df1 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -59,6 +59,7 @@ ramstage-y += soc.c ramstage-y += spm.c ramstage-y += sspm.c +ramstage-y += pcie.c ramstage-y += ../common/timer.c ramstage-y += ../common/uart.c ramstage-y += ufs.c diff --git a/src/soc/mediatek/mt8192/include/soc/pcie.h b/src/soc/mediatek/mt8192/include/soc/pcie.h new file mode 100644 index 0000000..dd8f7ab --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/pcie.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_PCIE_H +#define SOC_MEDIATEK_MT8192_PCIE_H + +void mtk_pcie_prepare(void); + +#endif diff --git a/src/soc/mediatek/mt8192/pcie.c b/src/soc/mediatek/mt8192/pcie.c new file mode 100644 index 0000000..c41687b --- /dev/null +++ b/src/soc/mediatek/mt8192/pcie.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/pcie.h> + +#define REG_PCIE_CLKREQ_EN (void *)(GPIO_BASE + 0x380) + +void mtk_pcie_prepare(void) +{ + u32 ret; + + /* set PCIe clkreq# for refclk 100M */ + ret = read32(REG_PCIE_CLKREQ_EN); + write32(REG_PCIE_CLKREQ_EN, ret | 0x33); + setbits32(REG_PCIE_CLKREQ_EN, 0x33); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/48724 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0f73eda4259028efe1eacc7d6e3ed4c15bfb75f Gerrit-Change-Number: 48724 Gerrit-PatchSet: 1 Gerrit-Owner: Qizhong Cheng <qizhong.cheng(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: superio/nuvoton/nct6793d: Add initial support
by Name of user not set (Code Review) 07 Aug '23

07 Aug '23

happycorsair(a)yandex.ru has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48790 ) Change subject: superio/nuvoton/nct6793d: Add initial support ...................................................................... superio/nuvoton/nct6793d: Add initial support Add initial support for Nuvoton NCT6793D superio chip. Right now it's just a proper renamed copy of NCT6791D code. It's used in ASUS PRIME H310* motherboards (trying to make them run coreboot). Signed-off-by: happycorsair <happycorsair(a)yandex.ru> Change-Id: I5484c4a30f60c77004bc0787ba584f50cd173f3c --- M src/superio/nuvoton/Makefile.inc A src/superio/nuvoton/nct6793d/Kconfig A src/superio/nuvoton/nct6793d/Makefile.inc A src/superio/nuvoton/nct6793d/nct6793d.h A src/superio/nuvoton/nct6793d/superio.c 5 files changed, 162 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/48790/1 diff --git a/src/superio/nuvoton/Makefile.inc b/src/superio/nuvoton/Makefile.inc index e9ac2e3..aae29ef 100644 --- a/src/superio/nuvoton/Makefile.inc +++ b/src/superio/nuvoton/Makefile.inc @@ -11,4 +11,5 @@ subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6776) += nct6776 subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6779D) += nct6779d subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6791D) += nct6791d +subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6793D) += nct6793d subdirs-$(CONFIG_SUPERIO_NUVOTON_NPCD378) += npcd378 diff --git a/src/superio/nuvoton/nct6793d/Kconfig b/src/superio/nuvoton/nct6793d/Kconfig new file mode 100644 index 0000000..245396d --- /dev/null +++ b/src/superio/nuvoton/nct6793d/Kconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config SUPERIO_NUVOTON_NCT6793D + bool + select SUPERIO_NUVOTON_COMMON_PRE_RAM diff --git a/src/superio/nuvoton/nct6793d/Makefile.inc b/src/superio/nuvoton/nct6793d/Makefile.inc new file mode 100644 index 0000000..a69daad --- /dev/null +++ b/src/superio/nuvoton/nct6793d/Makefile.inc @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6793D) += superio.c +ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6793D) += ../../common/ssdt.c +ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6793D) += ../../common/generic.c diff --git a/src/superio/nuvoton/nct6793d/nct6793d.h b/src/superio/nuvoton/nct6793d/nct6793d.h new file mode 100644 index 0000000..a56d41d --- /dev/null +++ b/src/superio/nuvoton/nct6793d/nct6793d.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef SUPERIO_NUVOTON_NCT6793D_H +#define SUPERIO_NUVOTON_NCT6793D_H + +/* Logical Device Numbers (LDN). */ +#define NCT6793D_PP 0x01 /* Parallel port */ +#define NCT6793D_SP1 0x02 /* UART A */ +#define NCT6793D_SP2 0x03 /* UART B, IR */ +#define NCT6793D_KBC 0x05 /* Keyboard Controller */ +#define NCT6793D_CIR 0x06 /* Consumer IR */ +#define NCT6793D_GPIO678 0x07 /* GPIO 6, 7 & 8 */ +#define NCT6793D_WDT1_WDTMEM_GPIO01 0x08 /* WDT1, WDT_MEM, GPIO 0 & 1 */ +#define NCT6793D_GPIO2345 0x09 /* GPIO 2, 3, 4 & 5 */ +#define NCT6793D_ACPI 0x0A /* ACPI */ +#define NCT6793D_HWM_FPLED 0x0B /* HW Monitor, Front Panel LED */ +#define NCT6793D_BCLK_WDT2_WDTMEM 0x0D /* BCLK, WDT2, WDT_MEM */ +#define NCT6793D_CIRWUP 0x0E /* CIR Wake-Up */ +#define NCT6793D_GPIO_PP_OD 0x0F /* GPIO Push-Pull/Open-Drain */ +#define NCT6793D_PORT80 0x14 /* Port 80 UART */ +#define NCT6793D_DS 0x16 /* Deep Sleep */ + +/* Virtual LDNs */ +#define NCT6793D_WDT1 ((0 << 8) | NCT6793D_WDT1_WDTMEM_GPIO01) +#define NCT6793D_WDTMEM ((4 << 8) | NCT6793D_WDT1_WDTMEM_GPIO01) +#define NCT6793D_GPIOBASE ((3 << 8) | NCT6793D_WDT1_WDTMEM_GPIO01) +#define NCT6793D_GPIO0 ((1 << 8) | NCT6793D_WDT1_WDTMEM_GPIO01) +#define NCT6793D_GPIO1 ((7 << 8) | NCT6793D_WDT1_WDTMEM_GPIO01) +#define NCT6793D_GPIO2 ((0 << 8) | NCT6793D_GPIO2345) +#define NCT6793D_GPIO3 ((1 << 8) | NCT6793D_GPIO2345) +#define NCT6793D_GPIO4 ((2 << 8) | NCT6793D_GPIO2345) +#define NCT6793D_GPIO5 ((3 << 8) | NCT6793D_GPIO2345) +#define NCT6793D_GPIO6 ((0 << 8) | NCT6793D_GPIO678) +#define NCT6793D_GPIO7 ((1 << 8) | NCT6793D_GPIO678) +#define NCT6793D_GPIO8 ((2 << 8) | NCT6793D_GPIO678) +#define NCT6793D_DS5 ((0 << 8) | NCT6793D_DS) +#define NCT6793D_DS3 ((1 << 8) | NCT6793D_DS) +#define NCT6793D_PCHDSW ((3 << 8) | NCT6793D_DS) +#define NCT6793D_DSWWOPT ((4 << 8) | NCT6793D_DS) +#define NCT6793D_DS3OPT ((5 << 8) | NCT6793D_DS) +#define NCT6793D_DSDSS ((6 << 8) | NCT6793D_DS) +#define NCT6793D_DSPU ((7 << 8) | NCT6793D_DS) + +#endif /* SUPERIO_NUVOTON_NCT6793D_H */ diff --git a/src/superio/nuvoton/nct6793d/superio.c b/src/superio/nuvoton/nct6793d/superio.c new file mode 100644 index 0000000..c4359d5 --- /dev/null +++ b/src/superio/nuvoton/nct6793d/superio.c @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/device.h> +#include <device/pnp.h> +#include <pc80/keyboard.h> +#include <superio/conf_mode.h> +#include <superio/common/ssdt.h> +#include <acpi/acpi.h> +#include "nct6793d.h" + +static void nct6793d_init(struct device *dev) +{ + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + case NCT6793D_KBC: + pc_keyboard_init(NO_AUX_DEVICE); + break; + } +} + +#if CONFIG(HAVE_ACPI_TABLES) +/* Provide ACPI HIDs for generic Super I/O SSDT */ +static const char *nct6793d_acpi_hid(const struct device *dev) +{ + if ((dev->path.type != DEVICE_PATH_PNP) || + (dev->path.pnp.port == 0) || + ((dev->path.pnp.device & 0xff) > NCT6793D_DS)) + return NULL; + + switch (dev->path.pnp.device & 0xff) { + case NCT6793D_SP1: /* fallthrough */ + case NCT6793D_SP2: + return ACPI_HID_COM; + case NCT6793D_KBC: + return ACPI_HID_KEYBOARD; + default: + return ACPI_HID_PNP; + } +} +#endif + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = nct6793d_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_fill_ssdt = superio_common_fill_ssdt_generator, + .acpi_name = superio_common_ldn_acpi_name, + .acpi_hid = nct6793d_acpi_hid, +#endif +}; + +static struct pnp_info pnp_dev_info[] = { + { NULL, NCT6793D_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, + 0x0ff8, }, + { NULL, NCT6793D_SP1, PNP_IO0 | PNP_IRQ0, + 0x0ff8, }, + { NULL, NCT6793D_SP2, PNP_IO0 | PNP_IRQ0, + 0x0ff8, }, + { NULL, NCT6793D_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, + 0x0fff, 0x0fff, }, + { NULL, NCT6793D_CIR, PNP_IO0 | PNP_IRQ0, + 0x0ff8, }, + { NULL, NCT6793D_ACPI}, + { NULL, NCT6793D_HWM_FPLED, PNP_IO0 | PNP_IO1 | PNP_IRQ0, + 0x0ffe, 0x0ffe, }, + { NULL, NCT6793D_BCLK_WDT2_WDTMEM}, + { NULL, NCT6793D_CIRWUP, PNP_IO0 | PNP_IRQ0, + 0x0ff8, }, + { NULL, NCT6793D_GPIO_PP_OD}, + { NULL, NCT6793D_PORT80}, + { NULL, NCT6793D_WDT1}, + { NULL, NCT6793D_WDTMEM}, + { NULL, NCT6793D_GPIOBASE, PNP_IO0, + 0x0ff8, }, + { NULL, NCT6793D_GPIO0}, + { NULL, NCT6793D_GPIO1}, + { NULL, NCT6793D_GPIO2}, + { NULL, NCT6793D_GPIO3}, + { NULL, NCT6793D_GPIO4}, + { NULL, NCT6793D_GPIO5}, + { NULL, NCT6793D_GPIO6}, + { NULL, NCT6793D_GPIO7}, + { NULL, NCT6793D_GPIO8}, + { NULL, NCT6793D_DS5}, + { NULL, NCT6793D_DS3}, + { NULL, NCT6793D_PCHDSW}, + { NULL, NCT6793D_DSWWOPT}, + { NULL, NCT6793D_DS3OPT}, + { NULL, NCT6793D_DSDSS}, + { NULL, NCT6793D_DSPU}, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_nuvoton_nct6793d_ops = { + CHIP_NAME("NUVOTON NCT6793D Super I/O") + .enable_dev = enable_dev, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/48790 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5484c4a30f60c77004bc0787ba584f50cd173f3c Gerrit-Change-Number: 48790 Gerrit-PatchSet: 1 Gerrit-Owner: happycorsair(a)yandex.ru Gerrit-MessageType: newchange

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