coreboot-gerrit December 2022

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[master]: cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm
by Arthur Heymans (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Stefan Ott, Angel Pons, Werner Zeh, Alexander Couzens. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69297 ) Change subject: cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm ...................................................................... Patch Set 18: (2 comments) File src/northbridge/intel/gm45/northbridge.c: https://review.coreboot.org/c/coreboot/+/69297/comment/d88f6812_12df67c5 PS18, Line 264: __pci_0_00_0 > Shall this better be 'pcidev_on_root(0, 0);'? It's not the same. pcidev_on_root finds a dev at runtime while this is a direct reference to it. If it's missing it won't compile. File src/southbridge/intel/i82801ix/lpc.c: https://review.coreboot.org/c/coreboot/+/69297/comment/dbdd0cc5_104b5fd1 PS18, Line 143: __pci_0_1f_0 > pcidev_on_root(0x1f, 0)? See other comment. -- To view, visit https://review.coreboot.org/c/coreboot/+/69297 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a9b1e684a7927259adae9b1d42a67e907722109 Gerrit-Change-Number: 69297 Gerrit-PatchSet: 18 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Thu, 01 Dec 2022 14:27:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: soc/intel/common: provide a list of D-states to enter LPM
by Kapil Porwal (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Tarun Tuli, Eran Mitrani. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70166 ) Change subject: soc/intel/common: provide a list of D-states to enter LPM ...................................................................... Patch Set 3: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/70166/comment/a1df7c9d_c1e9cf54 PS3, Line 7: soc/intel/common and alderlake Patchset: PS3: Thanks for moving it to common code. File src/soc/intel/alderlake/acpi.c: https://review.coreboot.org/c/coreboot/+/70166/comment/c0e604a1_1801f7ab PS3, Line 233: void soc_lpi_get_constraints(void *unused) : { : acpi_generate_lpi_constraint_table(); : } Can't we remove this method itself? File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/70166/comment/3b6fe2b0_7e5b99b1 PS3, Line 443: return NULL; set size to 0 as we are returning NULL. https://review.coreboot.org/c/coreboot/+/70166/comment/27d4cf02_a6556caa PS3, Line 486: Need to handle a case when `num_entries` is 0 here. -- To view, visit https://review.coreboot.org/c/coreboot/+/70166 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45eded3868a4987cb5eb0676c50378ac52ec3752 Gerrit-Change-Number: 70166 Gerrit-PatchSet: 3 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Comment-Date: Thu, 01 Dec 2022 14:06:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/siemens/mc_ehl2: Disable GSPI2 controller
by Felix Held (Code Review) 01 Dec '22

01 Dec '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69972 ) Change subject: mb/siemens/mc_ehl2: Disable GSPI2 controller ...................................................................... mb/siemens/mc_ehl2: Disable GSPI2 controller GSPI2 interface is not used on this mainboard and can be disabled. It will in addition remove the warning of a leftover static device in the log. Change-Id: I6e7462312953d50385ca7bb2f2e0abb8fc3a5886 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69972 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb 1 file changed, 18 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Werner Zeh: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index 74d0f26..c922e9e 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -142,8 +142,6 @@ device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 12.0 on end # GSPI2 - device pci 14.0 on end # USB3.1 xHCI device pci 15.0 on end # I2C0 -- To view, visit https://review.coreboot.org/c/coreboot/+/69972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e7462312953d50385ca7bb2f2e0abb8fc3a5886 Gerrit-Change-Number: 69972 Gerrit-PatchSet: 3 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/amd/chausie: change AMD_FWM_POSITION_INDEX for non-chromeos case
by Felix Held (Code Review) 01 Dec '22

01 Dec '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/70133 ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/amd/chausie: change AMD_FWM_POSITION_INDEX for non-chromeos case ...................................................................... mb/amd/chausie: change AMD_FWM_POSITION_INDEX for non-chromeos case Commit 2c102232e8f7 ("mb/amd/chausie,google/skyrim: increase RW_MRC_CACHE size to 120 kByte") increased the MRC cache size, but with the change the default AMD_FWM_POSITION_INDEX which is 5 for the 16MByte flash size, the amdfw part won't be placed on the expected position, since the cbfs header is in that exact location and cbfstool places the amdfw part right after that. Change the AMD_FWM_POSITION_INDEX to 4 for the non-chromeos builds to work around this. TEST=Non-chromeos chausie build now boots and doesn't fail any more before releasing the x86 cores from reset Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I89fe1d0672139e04070f05c6c8fa8955edcfc7ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/70133 Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/amd/chausie/Kconfig 1 file changed, 25 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Fred Reitberger: Looks good to me, approved diff --git a/src/mainboard/amd/chausie/Kconfig b/src/mainboard/amd/chausie/Kconfig index da0e0c4..ad4d530 100644 --- a/src/mainboard/amd/chausie/Kconfig +++ b/src/mainboard/amd/chausie/Kconfig @@ -29,6 +29,7 @@ config AMD_FWM_POSITION_INDEX int default 3 if CHROMEOS + default 4 help TODO: might need to be adapted for better placement of files in cbfs -- To view, visit https://review.coreboot.org/c/coreboot/+/70133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89fe1d0672139e04070f05c6c8fa8955edcfc7ee Gerrit-Change-Number: 70133 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/nissa/pujjo: Add new audio sku configure
by Felix Held (Code Review) 01 Dec '22

01 Dec '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/70131 ) Change subject: mb/google/nissa/pujjo: Add new audio sku configure ...................................................................... mb/google/nissa/pujjo: Add new audio sku configure Add new audio sku configure for Pujjo board. BUG=b:260538412 TEST=Boot to OS on pujjo and check that audio are configured based on fw_config. Signed-off-by: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Change-Id: Ia9ddc683945002a0b19efd67006e1983b2eb9f2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/70131 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Reka Norman <rekanorman(a)chromium.org> Reviewed-by: Kangheui Won <khwon(a)chromium.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/pujjo/overridetree.cb 1 file changed, 24 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Kangheui Won: Looks good to me, approved Reka Norman: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/pujjo/overridetree.cb b/src/mainboard/google/brya/variants/pujjo/overridetree.cb index e3d8acc..acba86e 100644 --- a/src/mainboard/google/brya/variants/pujjo/overridetree.cb +++ b/src/mainboard/google/brya/variants/pujjo/overridetree.cb @@ -24,6 +24,7 @@ field AUDIO 12 14 option ALC1019_ALC5682IVS 0 option MAX98357_ALC5682I 1 + option MAX98357_ALC5682IVS 2 end field EXT_VR 15 option EXT_VR_PRESENT 0 @@ -480,6 +481,7 @@ register "property_list[0].integer" = "1" device i2c 1a on probe AUDIO ALC1019_ALC5682IVS + probe AUDIO MAX98357_ALC5682IVS end end chip drivers/generic/alc1015 @@ -516,6 +518,7 @@ register "sdmode_delay" = "5" device generic 0 on probe AUDIO MAX98357_ALC5682I + probe AUDIO MAX98357_ALC5682IVS end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/70131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9ddc683945002a0b19efd67006e1983b2eb9f2d Gerrit-Change-Number: 70131 Gerrit-PatchSet: 3 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-CC: Jynn Chen <jynn.chen(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin3 Yang <Kevin3.Yang(a)lcfuturecenter.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/meteorlake: Add timestamp for cse_fw_sync
by Dinesh Gehlot (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Tarun Tuli, Paul Menzel, Kapil Porwal. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Kapil Porwal, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70172 to look at the new patch set (#9). Change subject: soc/intel/meteorlake: Add timestamp for cse_fw_sync ...................................................................... soc/intel/meteorlake: Add timestamp for cse_fw_sync The patch adds timestamp around cse_fw_sync(). BUG=none TEST=Verified on rex, cbmem -t: 948:starting CSE firmware sync 1,340,551 (50,657) 949:finished CSE firmware sync 1,379,348 (38,797) Port of commit b647e35119c1 (“soc/intel/alderlake: Add timestamp for cse_fw_sync”) Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: I6cfbf84018e312fbf9482f0fba05b444603cd4b9 --- M src/soc/intel/meteorlake/romstage/romstage.c 1 file changed, 25 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/70172/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/70172 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cfbf84018e312fbf9482f0fba05b444603cd4b9 Gerrit-Change-Number: 70172 Gerrit-PatchSet: 9 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/meteorlake: Add timestamp for cse_fw_sync
by Dinesh Gehlot (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Tarun Tuli, Paul Menzel, Kapil Porwal. Dinesh Gehlot has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70172 ) Change subject: soc/intel/meteorlake: Add timestamp for cse_fw_sync ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/70172/comment/39ca1f7f_d5953536 PS6, Line 19: > Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 7c6dd796f26f ("soc/intel/meteorlake: Implement report_cache_info() function")' Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/70172 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cfbf84018e312fbf9482f0fba05b444603cd4b9 Gerrit-Change-Number: 70172 Gerrit-PatchSet: 8 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 01 Dec 2022 13:57:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Add timestamp for cse_fw_sync
by Dinesh Gehlot (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Tarun Tuli, Paul Menzel, Kapil Porwal. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Kapil Porwal, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70172 to look at the new patch set (#8). Change subject: soc/intel/meteorlake: Add timestamp for cse_fw_sync ...................................................................... soc/intel/meteorlake: Add timestamp for cse_fw_sync The patch adds timestamp around cse_fw_sync(). BUG=none TEST=Verified on rex, cbmem -t: 948:starting CSE firmware sync 1,340,551 (50,657) 949:finished CSE firmware sync 1,379,348 (38,797) Port of commit b647e35119c1 (“soc/intel/alderlake: Add timestamp for cse_fw_sync”) Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: I6cfbf84018e312fbf9482f0fba05b444603cd4b9 --- M src/soc/intel/meteorlake/romstage/romstage.c 1 file changed, 26 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/70172/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/70172 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cfbf84018e312fbf9482f0fba05b444603cd4b9 Gerrit-Change-Number: 70172 Gerrit-PatchSet: 8 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/amd/*: Enable override of MAINBOARD_BLOBS_DIR
by Fred Reitberger (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Martin Roth, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69410 ) Change subject: soc/amd/*: Enable override of MAINBOARD_BLOBS_DIR ...................................................................... Patch Set 3: (3 comments) File src/soc/amd/common/Kconfig.common: https://review.coreboot.org/c/coreboot/+/69410/comment/380fab31_c9fdada0 PS2, Line 19: > Nit: get rid of 2nd blank line. Done File src/soc/amd/common/Makefile.inc: https://review.coreboot.org/c/coreboot/+/69410/comment/2d2d7377_6d950309 PS2, Line 2: ifeq ($(CONFIG_SOC_AMD_COMMON),y) > Somewhat unrelated to this patch, but I think this could be extended around most of this file. See follow-up patch https://review.coreboot.org/c/coreboot/+/69410/comment/6f1fae28_83475bf7 PS2, Line 49: $(patsubst > There's a macro for this already. […] Done - thanks for pointing out that macro! -- To view, visit https://review.coreboot.org/c/coreboot/+/69410 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0702fdb97fbc2c73d97994ab4d5161ff0f467518 Gerrit-Change-Number: 69410 Gerrit-PatchSet: 3 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 01 Dec 2022 13:52:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Add timestamp for cse_fw_sync
by Dinesh Gehlot (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Tarun Tuli, Paul Menzel, Kapil Porwal. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Kapil Porwal, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70172 to look at the new patch set (#7). Change subject: soc/intel/meteorlake: Add timestamp for cse_fw_sync ...................................................................... soc/intel/meteorlake: Add timestamp for cse_fw_sync The patch adds timestamp around cse_fw_sync(). BUG=none TEST=Verified on rex, cbmem -t: 948:starting CSE firmware sync 1,340,551 (50,657) 949:finished CSE firmware sync 1,379,348 (38,797) Port of commit b647e35119c1 (“soc/intel/alderlake: Add timestamp for cse_fw_sync”) Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: I6cfbf84018e312fbf9482f0fba05b444603cd4b9 --- M src/soc/intel/meteorlake/romstage/romstage.c 1 file changed, 26 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/70172/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/70172 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cfbf84018e312fbf9482f0fba05b444603cd4b9 Gerrit-Change-Number: 70172 Gerrit-PatchSet: 7 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit December 2022