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Change subject: mb/system76/tgl-h: Convert oryp8 to a variant
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Patch Set 5: Code-Review+2
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Change subject: mb/google/rex: Use OV13B10 sensor for Proto 1 SKUs
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Patch Set 1:
(1 comment)
File src/mainboard/google/rex/variants/rex0/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/70226/comment/0eacb6bc_82f2a674
PS1, Line 268: register "ssdb.lanes_used" = "2"
> Just to confirm, all the config and sequencing/etc is identical on the DB10?
looking at the linux OVB10 driver, I felt so. but we can always get this tested.
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Change subject: soc/amd/*: Enable override of MAINBOARD_BLOBS_DIR
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Change subject: soc/amd/common/Makefile.inc: Extend if case coverage
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Change subject: mb/google/rex: Use OV13B10 sensor for Proto 1 SKUs
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Patch Set 1:
(1 comment)
File src/mainboard/google/rex/variants/rex0/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/70226/comment/134197aa_533d9d26
PS1, Line 268: register "ssdb.lanes_used" = "2"
Just to confirm, all the config and sequencing/etc is identical on the DB10?
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Change subject: mb/google/rex: Cnfigure `SLP_S0_GATE_R` aka GPP_H14 PIN low
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Patch Set 3:
(1 comment)
Patchset:
PS3:
> I think we should wait Intel verify this, weird.
I agree that and looking at Brya, this PIN is set to high but if you follow the schematics log, I felt that this PIN should be set to low as SKL_S0_L is the decision maker for the OR gate based on the S0ix flow.
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