coreboot-gerrit January 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: arch/x86/acpi: Replace Add(a,b,c) with ASL 2.0 syntax
by Felix Singer (Code Review) 02 Jan '22

02 Jan '22

Attention is currently required from: Lance Zhao, Nico Huber, Tim Wawrzynczak. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60645 ) Change subject: arch/x86/acpi: Replace Add(a,b,c) with ASL 2.0 syntax ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Old and new syntax was mixed before these patches. That is nothing new. Not speaking of the different spellings of the instructions, like LAnd, Land or land. Yes, ASL is case-insensitive and it's the same syntax, but it's a mess. So not many people care about that. > Please note in the commit messages if the resulting byte code changes. Not doable for such an amount of patches. -- To view, visit https://review.coreboot.org/c/coreboot/+/60645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2a0b13522761e7113d1dc5b78d0dfd19a6cfd94 Gerrit-Change-Number: 60645 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Lance Zhao Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Sun, 02 Jan 2022 13:17:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/starlabs/labtop: Store serial number in CMOS
by Sean Rhodes (Code Review) 02 Jan '22

02 Jan '22

Sean Rhodes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/59979 ) Change subject: mb/starlabs/labtop: Store serial number in CMOS ...................................................................... Abandoned Use VPD instead -- To view, visit https://review.coreboot.org/c/coreboot/+/59979 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70c35c8f99f7e3ac8e45e742156dca741a6c6933 Gerrit-Change-Number: 59979 Gerrit-PatchSet: 12 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: abandon

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Change in coreboot[master]: mb/starlabs/labtop: Enable I2C4
by Sean Rhodes (Code Review) 02 Jan '22

02 Jan '22

Attention is currently required from: Paul Menzel. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60264 ) Change subject: mb/starlabs/labtop: Enable I2C4 ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/60264/comment/dbc08656_79d5f64a PS2, Line 7: mb/starlabs/labtop: Enable I2C4 > It works fine without this Done https://review.coreboot.org/c/coreboot/+/60264/comment/90e43673_6ab2a3ee PS2, Line 12: > How did you test UART2 is working? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/60264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c2c4f67672ba5667ebdae9ecc01054449dd3dfd Gerrit-Change-Number: 60264 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sun, 02 Jan 2022 13:14:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <admin(a)starlabs.systems> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: ec/starlabs/merlin: Unify EC and CMOS names
by Sean Rhodes (Code Review) 02 Jan '22

02 Jan '22

Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60709 ) Change subject: ec/starlabs/merlin: Unify EC and CMOS names ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/60709 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0fab6b9dcd805f7b8c9bf8f14b0a799d8f396c8 Gerrit-Change-Number: 60709 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 02 Jan 2022 13:12:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: starlabs: Convert EC_GPE_SCI to Kconfig
by Sean Rhodes (Code Review) 02 Jan '22

02 Jan '22

Attention is currently required from: Paul Menzel, Angel Pons. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60229 ) Change subject: starlabs: Convert EC_GPE_SCI to Kconfig ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/60229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d47ebe76394fe1bcb217e0c6211db1566f82189 Gerrit-Change-Number: 60229 Gerrit-PatchSet: 10 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sun, 02 Jan 2022 13:12:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0/notify.c: Group per-phase data
by Subrata Banik (Code Review) 02 Jan '22

02 Jan '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60639 ) Change subject: drivers/intel/fsp2_0/notify.c: Group per-phase data ...................................................................... drivers/intel/fsp2_0/notify.c: Group per-phase data Group all data specific to each notify phase in a struct to avoid redundant code. Change-Id: Ib4ab3d87edfcd5426ce35c168cbb780ade87290e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60639 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/drivers/intel/fsp2_0/notify.c 1 file changed, 48 insertions(+), 20 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c index b3563c0..cdace31 100644 --- a/src/drivers/intel/fsp2_0/notify.c +++ b/src/drivers/intel/fsp2_0/notify.c @@ -6,9 +6,52 @@ #include <fsp/util.h> #include <mode_switch.h> #include <timestamp.h> +#include <types.h> + +struct fsp_notify_phase_data { + enum fsp_notify_phase notify_phase; + uint8_t post_code_before; + uint8_t post_code_after; + enum timestamp_id timestamp_before; + enum timestamp_id timestamp_after; +}; + +static const struct fsp_notify_phase_data notify_data[] = { + { + .notify_phase = AFTER_PCI_ENUM, + .post_code_before = POST_FSP_NOTIFY_BEFORE_ENUMERATE, + .post_code_after = POST_FSP_NOTIFY_AFTER_ENUMERATE, + .timestamp_before = TS_FSP_BEFORE_ENUMERATE, + .timestamp_after = TS_FSP_AFTER_ENUMERATE, + }, + { + .notify_phase = READY_TO_BOOT, + .post_code_before = POST_FSP_NOTIFY_BEFORE_FINALIZE, + .post_code_after = POST_FSP_NOTIFY_AFTER_FINALIZE, + .timestamp_before = TS_FSP_BEFORE_FINALIZE, + .timestamp_after = TS_FSP_AFTER_FINALIZE, + }, + { + .notify_phase = END_OF_FIRMWARE, + .post_code_before = POST_FSP_NOTIFY_BEFORE_END_OF_FIRMWARE, + .post_code_after = POST_FSP_NOTIFY_AFTER_END_OF_FIRMWARE, + .timestamp_before = TS_FSP_BEFORE_END_OF_FIRMWARE, + .timestamp_after = TS_FSP_AFTER_END_OF_FIRMWARE, + }, +}; + +static const struct fsp_notify_phase_data *get_notify_phase_data(enum fsp_notify_phase phase) +{ + for (size_t i = 0; i < ARRAY_SIZE(notify_data); i++) { + if (notify_data[i].notify_phase == phase) + return &notify_data[i]; + } + die("Unknown FSP notify phase %u\n", phase); +} static void fsp_notify(enum fsp_notify_phase phase) { + const struct fsp_notify_phase_data *data = get_notify_phase_data(phase); struct fsp_notify_params notify_params = { .phase = phase }; fsp_notify_fn fspnotify; uint32_t ret; @@ -20,32 +63,17 @@ fsps_hdr.notify_phase_entry_offset); fsp_before_debug_notify(fspnotify, &notify_params); - if (phase == AFTER_PCI_ENUM) { - timestamp_add_now(TS_FSP_BEFORE_ENUMERATE); - post_code(POST_FSP_NOTIFY_BEFORE_ENUMERATE); - } else if (phase == READY_TO_BOOT) { - timestamp_add_now(TS_FSP_BEFORE_FINALIZE); - post_code(POST_FSP_NOTIFY_BEFORE_FINALIZE); - } else if (phase == END_OF_FIRMWARE) { - timestamp_add_now(TS_FSP_BEFORE_END_OF_FIRMWARE); - post_code(POST_FSP_NOTIFY_BEFORE_END_OF_FIRMWARE); - } + timestamp_add_now(data->timestamp_before); + post_code(data->post_code_before); if (ENV_X86_64 && CONFIG(PLATFORM_USES_FSP2_X86_32)) ret = protected_mode_call_1arg(fspnotify, (uintptr_t)&notify_params); else ret = fspnotify(&notify_params); - if (phase == AFTER_PCI_ENUM) { - timestamp_add_now(TS_FSP_AFTER_ENUMERATE); - post_code(POST_FSP_NOTIFY_AFTER_ENUMERATE); - } else if (phase == READY_TO_BOOT) { - timestamp_add_now(TS_FSP_AFTER_FINALIZE); - post_code(POST_FSP_NOTIFY_AFTER_FINALIZE); - } else if (phase == END_OF_FIRMWARE) { - timestamp_add_now(TS_FSP_AFTER_END_OF_FIRMWARE); - post_code(POST_FSP_NOTIFY_AFTER_END_OF_FIRMWARE); - } + timestamp_add_now(data->timestamp_after); + post_code(data->post_code_after); + fsp_debug_after_notify(ret); /* Handle any errors returned by FspNotify */ -- To view, visit https://review.coreboot.org/c/coreboot/+/60639 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4ab3d87edfcd5426ce35c168cbb780ade87290e Gerrit-Change-Number: 60639 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/intel/fsp2_0/notify.c: Clean up some cosmetics
by Subrata Banik (Code Review) 02 Jan '22

02 Jan '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60638 ) Change subject: drivers/intel/fsp2_0/notify.c: Clean up some cosmetics ...................................................................... drivers/intel/fsp2_0/notify.c: Clean up some cosmetics Sort includes alphabetically, drop spaces after type casts and unbreak some long lines that are less than 96 characters long. Tested with BUILD_TIMELESS=1, Prodrive Hermes remains identical. Change-Id: I2dafd677abbdd892745fea1bf4414f6e0d5549bb Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60638 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/drivers/intel/fsp2_0/notify.c 1 file changed, 8 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c index 9a0f23a..b3563c0 100644 --- a/src/drivers/intel/fsp2_0/notify.c +++ b/src/drivers/intel/fsp2_0/notify.c @@ -4,19 +4,19 @@ #include <console/console.h> #include <cpu/x86/mtrr.h> #include <fsp/util.h> -#include <timestamp.h> #include <mode_switch.h> +#include <timestamp.h> static void fsp_notify(enum fsp_notify_phase phase) { - uint32_t ret; - fsp_notify_fn fspnotify; struct fsp_notify_params notify_params = { .phase = phase }; + fsp_notify_fn fspnotify; + uint32_t ret; if (!fsps_hdr.notify_phase_entry_offset) die("Notify_phase_entry_offset is zero!\n"); - fspnotify = (void *) (uintptr_t)(fsps_hdr.image_base + + fspnotify = (void *)(uintptr_t)(fsps_hdr.image_base + fsps_hdr.notify_phase_entry_offset); fsp_before_debug_notify(fspnotify, &notify_params); @@ -68,14 +68,10 @@ fsp_notify(END_OF_FIRMWARE); } -BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fsp_notify_dummy, - (void *) AFTER_PCI_ENUM); -BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, fsp_notify_dummy, - (void *) READY_TO_BOOT); -BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, fsp_notify_dummy, - (void *) READY_TO_BOOT); +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fsp_notify_dummy, (void *)AFTER_PCI_ENUM); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, fsp_notify_dummy, (void *)READY_TO_BOOT); +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, fsp_notify_dummy, (void *)READY_TO_BOOT); -__weak void platform_fsp_notify_status( - enum fsp_notify_phase phase) +__weak void platform_fsp_notify_status(enum fsp_notify_phase phase) { } -- To view, visit https://review.coreboot.org/c/coreboot/+/60638 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2dafd677abbdd892745fea1bf4414f6e0d5549bb Gerrit-Change-Number: 60638 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/intel/fsp2_0: Print return value when dying
by Subrata Banik (Code Review) 02 Jan '22

02 Jan '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60637 ) Change subject: drivers/intel/fsp2_0: Print return value when dying ...................................................................... drivers/intel/fsp2_0: Print return value when dying When coreboot goes to die because FSP returned an error, log the return value in the message printed by `die()` or `die_with_post_code()`. Change-Id: I6b9ea60534a20429f15132007c1f5770760481af Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60637 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/intel/fsp2_0/notify.c M src/drivers/intel/fsp2_0/temp_ram_exit.c 3 files changed, 5 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index c1a7377..3c1a088 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -309,9 +309,8 @@ /* Handle any errors returned by FspMemoryInit */ fsp_handle_reset(status); if (status != FSP_SUCCESS) { - printk(BIOS_CRIT, "FspMemoryInit returned 0x%08x\n", status); die_with_post_code(POST_RAM_FAILURE, - "FspMemoryInit returned an error!\n"); + "FspMemoryInit returned with error 0x%08x!\n", status); } do_fsp_post_memory_init(s3wake, fsp_version); diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c index 311ce46..9a0f23a 100644 --- a/src/drivers/intel/fsp2_0/notify.c +++ b/src/drivers/intel/fsp2_0/notify.c @@ -50,10 +50,8 @@ /* Handle any errors returned by FspNotify */ fsp_handle_reset(ret); - if (ret != FSP_SUCCESS) { - printk(BIOS_SPEW, "FspNotify returned 0x%08x\n", ret); - die("FspNotify returned an error!\n"); - } + if (ret != FSP_SUCCESS) + die("FspNotify returned with error 0x%08x!\n", ret); /* Allow the platform to run something after FspNotify */ platform_fsp_notify_status(phase); diff --git a/src/drivers/intel/fsp2_0/temp_ram_exit.c b/src/drivers/intel/fsp2_0/temp_ram_exit.c index 5d7cbd4..2192543 100644 --- a/src/drivers/intel/fsp2_0/temp_ram_exit.c +++ b/src/drivers/intel/fsp2_0/temp_ram_exit.c @@ -29,10 +29,8 @@ printk(BIOS_DEBUG, "Calling TempRamExit: %p\n", temp_ram_exit); status = temp_ram_exit(NULL); - if (status != FSP_SUCCESS) { - printk(BIOS_CRIT, "TempRamExit returned 0x%08x\n", status); - die("TempRamExit returned an error!\n"); - } + if (status != FSP_SUCCESS) + die("TempRamExit returned with error 0x%08x!\n", status); cbfs_unmap(mapping); } -- To view, visit https://review.coreboot.org/c/coreboot/+/60637 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b9ea60534a20429f15132007c1f5770760481af Gerrit-Change-Number: 60637 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/{adl,ehl,tgl}: Rename spi_protection_mode to mfg_mode
by Subrata Banik (Code Review) 02 Jan '22

02 Jan '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60407 ) Change subject: soc/intel/{adl,ehl,tgl}: Rename spi_protection_mode to mfg_mode ...................................................................... soc/intel/{adl,ehl,tgl}: Rename spi_protection_mode to mfg_mode Since TGL `spi_protection_mode` bit replaces the previous `manufacturing mode` without changing the offset and purpose of this bit. This patch renames to `manufacturing mode` aka `mfg_mode` to maintain the parity with other PCHs as part of IA-common code. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I6d00f72ce7b3951120778733066c351986ccf343 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60407 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> --- M src/soc/intel/alderlake/include/soc/me.h M src/soc/intel/alderlake/me.c M src/soc/intel/elkhartlake/include/soc/me.h M src/soc/intel/elkhartlake/me.c M src/soc/intel/tigerlake/include/soc/me.h M src/soc/intel/tigerlake/me.c 6 files changed, 8 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved EricR Lai: Looks good to me, approved diff --git a/src/soc/intel/alderlake/include/soc/me.h b/src/soc/intel/alderlake/include/soc/me.h index 993a3bc..8eea095 100644 --- a/src/soc/intel/alderlake/include/soc/me.h +++ b/src/soc/intel/alderlake/include/soc/me.h @@ -10,7 +10,7 @@ u32 data; struct { u32 working_state: 4; - u32 spi_protection_mode: 1; + u32 mfg_mode: 1; u32 fpt_bad: 1; u32 operation_state: 3; u32 fw_init_complete: 1; diff --git a/src/soc/intel/alderlake/me.c b/src/soc/intel/alderlake/me.c index da1a299..ea94902 100644 --- a/src/soc/intel/alderlake/me.c +++ b/src/soc/intel/alderlake/me.c @@ -121,14 +121,14 @@ * production system to indicate ME Manufacturing mode is disabled. */ printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", - ((hfsts1.fields.spi_protection_mode == 0) && + ((hfsts1.fields.mfg_mode == 0) && (hfsts6.fields.fpf_soc_lock == 1)) ? "NO" : "YES"); /* * The SPI Protection Mode bit reflects SPI descriptor * locked(0) or unlocked(1). */ printk(BIOS_DEBUG, "ME: SPI Protection Mode Enabled : %s\n", - hfsts1.fields.spi_protection_mode ? "NO" : "YES"); + hfsts1.fields.mfg_mode ? "NO" : "YES"); printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", hfsts1.fields.fpt_bad ? "BAD" : "OK"); printk(BIOS_DEBUG, "ME: Bringup Loader Failure : %s\n", diff --git a/src/soc/intel/elkhartlake/include/soc/me.h b/src/soc/intel/elkhartlake/include/soc/me.h index 8d1021f..d845629 100644 --- a/src/soc/intel/elkhartlake/include/soc/me.h +++ b/src/soc/intel/elkhartlake/include/soc/me.h @@ -8,7 +8,7 @@ uint32_t data; struct { uint32_t working_state: 4; - uint32_t spi_protection_mode: 1; + uint32_t mfg_mode: 1; uint32_t fpt_bad: 1; uint32_t operation_state: 3; uint32_t fw_init_complete: 1; diff --git a/src/soc/intel/elkhartlake/me.c b/src/soc/intel/elkhartlake/me.c index 5087781..cb70d50 100644 --- a/src/soc/intel/elkhartlake/me.c +++ b/src/soc/intel/elkhartlake/me.c @@ -32,7 +32,7 @@ printk(BIOS_DEBUG, "ME: HFSTS6 : 0x%08X\n", hfsts6.data); printk(BIOS_DEBUG, "ME: SPI Protection Mode : %s\n", - hfsts1.fields.spi_protection_mode ? "YES" : "NO"); + hfsts1.fields.mfg_mode ? "YES" : "NO"); printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", hfsts1.fields.fpt_bad ? "BAD" : "OK"); printk(BIOS_DEBUG, "ME: Bringup Loader Failure : %s\n", diff --git a/src/soc/intel/tigerlake/include/soc/me.h b/src/soc/intel/tigerlake/include/soc/me.h index 674ac7e..ed25444 100644 --- a/src/soc/intel/tigerlake/include/soc/me.h +++ b/src/soc/intel/tigerlake/include/soc/me.h @@ -8,7 +8,7 @@ u32 data; struct { u32 working_state: 4; - u32 spi_protection_mode: 1; + u32 mfg_mode: 1; u32 fpt_bad: 1; u32 operation_state: 3; u32 fw_init_complete: 1; diff --git a/src/soc/intel/tigerlake/me.c b/src/soc/intel/tigerlake/me.c index da1a299..ea94902 100644 --- a/src/soc/intel/tigerlake/me.c +++ b/src/soc/intel/tigerlake/me.c @@ -121,14 +121,14 @@ * production system to indicate ME Manufacturing mode is disabled. */ printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", - ((hfsts1.fields.spi_protection_mode == 0) && + ((hfsts1.fields.mfg_mode == 0) && (hfsts6.fields.fpf_soc_lock == 1)) ? "NO" : "YES"); /* * The SPI Protection Mode bit reflects SPI descriptor * locked(0) or unlocked(1). */ printk(BIOS_DEBUG, "ME: SPI Protection Mode Enabled : %s\n", - hfsts1.fields.spi_protection_mode ? "NO" : "YES"); + hfsts1.fields.mfg_mode ? "NO" : "YES"); printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", hfsts1.fields.fpt_bad ? "BAD" : "OK"); printk(BIOS_DEBUG, "ME: Bringup Loader Failure : %s\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/60407 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d00f72ce7b3951120778733066c351986ccf343 Gerrit-Change-Number: 60407 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: ec/starlabs/merlin: Apply EC settings when suspending
by Sean Rhodes (Code Review) 02 Jan '22

02 Jan '22

Attention is currently required from: Andy Pont. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60165 ) Change subject: ec/starlabs/merlin: Apply EC settings when suspending ...................................................................... Patch Set 11: (3 comments) File src/ec/starlabs/merlin/acpi/suspend.asl: https://review.coreboot.org/c/coreboot/+/60165/comment/9f17857b_80161bb8 PS2, Line 16: \_SB.PCI0.LPCB.EC.KLSE = 0x00 > `WDMS (\_SB.PC00.LPCB.H_EC.KLBS, \_SB.PC00.LPCB. […] Done File src/ec/starlabs/merlin/acpi/suspend.asl: https://review.coreboot.org/c/coreboot/+/60165/comment/aff87b75_2085defc PS6, Line 9: /* Store current EC settings */ > Suggest amending the comment to /* Store current EC settings in CMOS */ to remove any ambiguity abou […] Done https://review.coreboot.org/c/coreboot/+/60165/comment/c1c7d184_3f8c3d1d PS6, Line 10: \_SB.PCI0.LPCB.TPLS = \_SB.PCI0.LPCB.EC.TPLA > It would make the code more obvious if the names of the ECRAM and corresponding CMOS entries were gi […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/60165 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I998d5509cd5e95736468f88663a1423217cf6ddf Gerrit-Change-Number: 60165 Gerrit-PatchSet: 11 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Comment-Date: Sun, 02 Jan 2022 12:21:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <admin(a)starlabs.systems> Comment-In-Reply-To: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-MessageType: comment

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