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Change subject: mb/google/corsola: Enable SD card reader
......................................................................
Patch Set 4: Code-Review+1
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60780/comment/3258d72a_d808d5e6
PS3, Line 7: Set GPIO to enable SD card bridge IC
> Enable SD card reader
Done
https://review.coreboot.org/c/coreboot/+/60780/comment/f2874f9e_8b86a747
PS3, Line 9: SD card is supported on kingler board, so we set EN_PP3300_SDBRDG_X
: as output mode and value as 1 to enable SD card bridge IC.
> what about: […]
Done
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Change subject: mb/google/herobrine: Initialize `pins` to fix the compilation issue
......................................................................
Patch Set 2: Code-Review+2
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Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/60780
to look at the new patch set (#4).
Change subject: mb/google/corsola: Enable SD card reader
......................................................................
mb/google/corsola: Enable SD card reader
The Kingler board has a SD card reader connected via USB and
can be enabled by setting GPIO EN_PP3300_SDBRDG_X to output
mode and activated.
BUG=b:211385131
TEST=boot kernel using SD card.
Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com>
Change-Id: I903731ea4906328b2f0f5a7c6c06bd9c964d24ec
---
M src/mainboard/google/corsola/Kconfig
M src/mainboard/google/corsola/gpio.h
M src/mainboard/google/corsola/mainboard.c
3 files changed, 9 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/60780/4
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Change subject: soc/intel/alderlake: Add soc_get_cpu_rp_vw_idx() function
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> ping 😊
I had planned to review that last night itself but somehow i missed that, hope its not too late 😊
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Change subject: soc/intel/tigerlake: Add soc_get_cpu_rp_vw_idx() function
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> Where can we get this vw idx map?
If I'm not wrong, we have referred the same from ref platform code of FSP.
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Change subject: soc/intel/alderlake: Hook up FSP-S CPU PCIe UPDs
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
> Interesting, I did in romstage, FSP-S need do it again? […]
Pcie UPDs are split between FSP-M and FSP-S, so we might need to program those accordingly :(
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Change subject: soc/intel/common/block/pcie/rtd3: Update ACPI methods for CPU PCIe RPs
......................................................................
Patch Set 4: Code-Review+1
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60183/comment/a78b99cc_7f51b003
PS4, Line 10:
next line may be?
https://review.coreboot.org/c/coreboot/+/60183/comment/71f4f54f_b77d94f6
PS4, Line 12:
can you please also highlight here that you have dropped unused argument from pcie_rtd3_acpi_method_status() or you consider to submit that in a separate CL?
File src/soc/intel/common/block/pcie/rtd3/rtd3.c:
https://review.coreboot.org/c/coreboot/+/60183/comment/de0b2161_aea0e598
PS4, Line 269: /* Read port number of root port that this device is attached to. */
: pcie_rp = pci_read_config8(parent, PCH_PCIE_CFG_LCAP_PN);
: if (pcie_rp == 0 || pcie_rp > CONFIG_MAX_ROOT_PORTS) {
: printk(BIOS_ERR, "%s: Invalid root port number: %u\n", __func__, pcie_rp);
: return;
: }
: /* Port number is 1-based, PMC IPC method expects 0-based. */
: pcie_rp--;
suggestion: can you please consider creating a static helper function that return the pch pci_rp number?
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