coreboot-gerrit January 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/common/cse: Add config to disable CSE at pre-boot
by Angel Pons (Code Review) 05 Jan '22

05 Jan '22

Attention is currently required from: Felix Singer, Nico Huber, Subrata Banik, Tim Wawrzynczak, Patrick Rudolph, EricR Lai. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60721 ) Change subject: soc/intel/common/cse: Add config to disable CSE at pre-boot ...................................................................... Patch Set 2: Code-Review+1 (1 comment) File src/soc/intel/common/block/cse/Kconfig: https://review.coreboot.org/c/coreboot/+/60721/comment/faf9bbd4_ab97cdce PS2, Line 13: This config decides the state of CSE/Heci1 device at the end of boot. > @Felix, I will wait for your alignment prior to addressing the open comments in this CL. How about renaming this to `DISABLE_HECI_AT_PRE_BOOT`? -- To view, visit https://review.coreboot.org/c/coreboot/+/60721 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e127816c506df3ac0cf973b69021d02d05bef4a Gerrit-Change-Number: 60721 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Wed, 05 Jan 2022 12:36:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/sarien/Kconfig: Remove blank line at beginning
by Angel Pons (Code Review) 05 Jan '22

05 Jan '22

Attention is currently required from: Felix Singer, Paul Menzel. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60767 ) Change subject: mb/google/sarien/Kconfig: Remove blank line at beginning ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0410be48f360bdd00e4ed7599cbee405915344b9 Gerrit-Change-Number: 60767 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 05 Jan 2022 12:35:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/sarien: Add VBT extracted from Chrome OS
by Angel Pons (Code Review) 05 Jan '22

05 Jan '22

Attention is currently required from: Felix Singer, Matt DeVillier, Paul Menzel. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60735 ) Change subject: mb/google/sarien: Add VBT extracted from Chrome OS ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60735 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibab8a7b0b3f721ca434ac38b51528b81e66f3bb7 Gerrit-Change-Number: 60735 Gerrit-PatchSet: 4 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 05 Jan 2022 12:34:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F
by build bot (Jenkins) (Code Review) 05 Jan '22

05 Jan '22

Attention is currently required from: Christian Walter, Arthur Heymans, Michael Niewöhner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37441 ) Change subject: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F ...................................................................... Patch Set 72: (9 comments) File src/mainboard/supermicro/x11-lga1151v2-series/Kconfig: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-137348): https://review.coreboot.org/c/coreboot/+/37441/comment/224da36c_94fa6822 PS72, Line 12: select SUPERIO_ASPEED_AST2400 'SUPERIO' may be misspelled - perhaps ''? Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-137348): https://review.coreboot.org/c/coreboot/+/37441/comment/f5be7343_54fb8180 PS72, Line 13: select SUPERIO_ASPEED_COMMON_PRE_RAM 'SUPERIO' may be misspelled - perhaps ''? Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-137348): https://review.coreboot.org/c/coreboot/+/37441/comment/038ce7b3_9153e1dd PS72, Line 14: select SUPERIO_ASPEED_HAS_UART_DELAY_WORKAROUND 'SUPERIO' may be misspelled - perhaps ''? File src/mainboard/supermicro/x11-lga1151v2-series/bootblock.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-137348): https://review.coreboot.org/c/coreboot/+/37441/comment/b3ba78a9_23134606 PS72, Line 4: #include <superio/aspeed/ast2400/ast2400.h> 'superio' may be misspelled - perhaps ''? Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-137348): https://review.coreboot.org/c/coreboot/+/37441/comment/422af2a5_1b9041c7 PS72, Line 5: #include <superio/aspeed/common/aspeed.h> 'superio' may be misspelled - perhaps ''? Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-137348): https://review.coreboot.org/c/coreboot/+/37441/comment/3254e7a8_55f97cef PS72, Line 9: static void early_config_superio(void) 'superio' may be misspelled - perhaps ''? Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-137348): https://review.coreboot.org/c/coreboot/+/37441/comment/baf2012c_9fc05768 PS72, Line 19: early_config_superio(); 'superio' may be misspelled - perhaps ''? File src/mainboard/supermicro/x11-lga1151v2-series/devicetree.cb: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-137348): https://review.coreboot.org/c/coreboot/+/37441/comment/82cbe804_31a878a1 PS72, Line 69: chip superio/common 'superio' may be misspelled - perhaps ''? Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-137348): https://review.coreboot.org/c/coreboot/+/37441/comment/dc65d3f9_8c147039 PS72, Line 71: chip superio/aspeed/ast2400 'superio' may be misspelled - perhaps ''? -- To view, visit https://review.coreboot.org/c/coreboot/+/37441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ab1cb9462607b9af068bc2374508d99c60d0a30 Gerrit-Change-Number: 37441 Gerrit-PatchSet: 72 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Guido Beyer @ Prodrive Technologies <guido.beyer(a)prodrive-technologies.com> Gerrit-Reviewer: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stef van Os <stef.van.os(a)prodrive-technologies.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: wouter.eckhardt(a)prodrive-technologies.com Gerrit-CC: Jonas Löffelholz Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shawn C <citypw(a)hardenedlinux.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Wed, 05 Jan 2022 12:33:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F
by Angel Pons (Code Review) 05 Jan '22

05 Jan '22

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Change in coreboot[master]: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F
by Angel Pons (Code Review) 05 Jan '22

05 Jan '22

Attention is currently required from: Christian Walter, Arthur Heymans, Michael Niewöhner. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37441 ) Change subject: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F ...................................................................... Patch Set 71: (4 comments) File Documentation/mainboard/supermicro/x11-lga1151v2-series/x11sch-f/x11sch-f.md: https://review.coreboot.org/c/coreboot/+/37441/comment/665f7796_7f7d5cd5 PS64, Line 31: 0x235=03 and 0x13E=84 > Then let's add that as comment I remember reading somewhere that these offsets seem to be wrong. I haven't checked them myself. File src/mainboard/supermicro/x11-lga1151v2-series/devicetree.cb: https://review.coreboot.org/c/coreboot/+/37441/comment/3e50202d_5ea0c480 PS67, Line 92: device pci 1f.2 off end # PMC > Haven't checked myself. I re-enabled it and doesn't seem to have any side-effects. Done File src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/overridetree.cb: https://review.coreboot.org/c/coreboot/+/37441/comment/4c2b8f19_97be1329 PS64, Line 6: > sry for the delay. it's not required, but makes matching acpi code easier, when gpe mapping matches. Hmmm, not sure how to obtain the values and I haven't seen any side-effects of not specifying them. Anything to do? File src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/overridetree.cb: https://review.coreboot.org/c/coreboot/+/37441/comment/84e295b0_2876857f PS67, Line 87: smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" : "M.2-P_1" "SlotDataBusWidth4X" : > I have no clue. Marking as resolved for now. -- To view, visit https://review.coreboot.org/c/coreboot/+/37441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ab1cb9462607b9af068bc2374508d99c60d0a30 Gerrit-Change-Number: 37441 Gerrit-PatchSet: 71 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Guido Beyer @ Prodrive Technologies <guido.beyer(a)prodrive-technologies.com> Gerrit-Reviewer: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stef van Os <stef.van.os(a)prodrive-technologies.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: wouter.eckhardt(a)prodrive-technologies.com Gerrit-CC: Jonas Löffelholz Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shawn C <citypw(a)hardenedlinux.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Wed, 05 Jan 2022 12:27:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Christian Walter <christian.walter(a)9elements.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/sarien: Add VBT extracted from Chrome OS
by Paul Menzel (Code Review) 05 Jan '22

05 Jan '22

Attention is currently required from: Felix Singer, Matt DeVillier, Paul Menzel, Angel Pons. Hello Felix Singer, build bot (Jenkins), Matt DeVillier, Tim Wawrzynczak, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60735 to look at the new patch set (#4). Change subject: mb/google/sarien: Add VBT extracted from Chrome OS ...................................................................... mb/google/sarien: Add VBT extracted from Chrome OS The VBT is extracted from Chromium OS in developer mode with the device running firwmare . $ sudo dmesg | grep ' DMI:' [ 0.000000] DMI: Dell Inc. Sarien/Sarien, BIOS Google_Sarien.12200.99.0 07/29/2020 $ sudo cbmem -1 coreboot-v1.9308_26_0.0.22-8761-gdba94f429a Wed Jul 29 16:09:30 UTC 2020 bootblock starting (log level: 8)... […] coreboot-v1.9308_26_0.0.22-8761-gdba94f429a Wed Jul 29 16:09:30 UTC 2020 ramstage starting (log level: 8)... […] CBFS: Locating 'vbt.bin' CBFS: Found @ offset 614c0 size 4a0 Found a VBT of 4608 bytes after decompression […] $ sudo cp /sys/kernel/debug/dri/0/i915_vbt vbt.bin Using the Chrome OS recovery image, Matt DeVillier verified, that the Sarien VBT is identical to Arcada, so add the VBT for all variants. Change-Id: Ibab8a7b0b3f721ca434ac38b51528b81e66f3bb7 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/google/sarien/Kconfig A src/mainboard/google/sarien/data.vbt 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/60735/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/60735 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibab8a7b0b3f721ca434ac38b51528b81e66f3bb7 Gerrit-Change-Number: 60735 Gerrit-PatchSet: 4 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Fix GPIO reset mapping as per GPIO BWG
by Subrata Banik (Code Review) 05 Jan '22

05 Jan '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60789 ) Change subject: soc/intel/alderlake: Fix GPIO reset mapping as per GPIO BWG ...................................................................... soc/intel/alderlake: Fix GPIO reset mapping as per GPIO BWG This patch fixes the documentation discrepancy of GPIO reset type between PCH EDS and GPIO BWG. As per GPIO BWG, there are 4-GPIO reset types in Alder Lake as below: - Power Good - (Value 00) - Deep - (Value 01) - Host Reset/PLTRST - (Value 10) - RSMRST for GPD/Reserved for GPP - (Value 11) Hence, created two different reset types for `GPP` and `GPD`. Also, replaced PAD_CFG0_LOGICAL_RESET_x macros with PAD_RESET(). BUG=b:213293047 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I4b8742c7a0cc1dc420e3e22e34a16355294ed61b --- M src/soc/intel/alderlake/gpio.c 1 file changed, 23 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/60789/1 diff --git a/src/soc/intel/alderlake/gpio.c b/src/soc/intel/alderlake/gpio.c index aa05136e..3d5af83 100644 --- a/src/soc/intel/alderlake/gpio.c +++ b/src/soc/intel/alderlake/gpio.c @@ -9,20 +9,20 @@ /* * This file is created based on Intel Alder Lake Processor PCH Datasheet - * Document number: 630094 - * Chapter number: 27 + * Document number: 630094, Chapter number: 27 + * Document number: 630603, Chapter number: 16 */ -static const struct reset_mapping rst_map[] = { - { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 }, - { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 }, - { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 }, +static const struct reset_mapping rst_map_gpp[] = { + { .logical = PAD_RESET(PWROK), .chipset = 0U << 30 }, + { .logical = PAD_RESET(DEEP), .chipset = 1U << 30 }, + { .logical = PAD_RESET(PLTRST), .chipset = 2U << 30 }, }; -static const struct reset_mapping rst_map_com2[] = { - { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 }, - { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 }, - { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 }, - { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 }, +static const struct reset_mapping rst_map_gpd[] = { + { .logical = PAD_RESET(PWROK), .chipset = 0U << 30 }, + { .logical = PAD_RESET(DEEP), .chipset = 1U << 30 }, + { .logical = PAD_RESET(PLTRST), .chipset = 2U << 30 }, + { .logical = PAD_RESET(RSMRST), .chipset = 3U << 30 }, }; /* @@ -104,8 +104,8 @@ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_BTA", .acpi_path = "\\_SB.PCI0.GPIO", - .reset_map = rst_map, - .num_reset_vals = ARRAY_SIZE(rst_map), + .reset_map = rst_map_gpp, + .num_reset_vals = ARRAY_SIZE(rst_map_gpp), .groups = adl_community0_groups, .num_groups = ARRAY_SIZE(adl_community0_groups), .vw_base = DEFAULT_VW_BASE, @@ -128,8 +128,8 @@ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_SDH", .acpi_path = "\\_SB.PCI0.GPIO", - .reset_map = rst_map, - .num_reset_vals = ARRAY_SIZE(rst_map), + .reset_map = rst_map_gpp, + .num_reset_vals = ARRAY_SIZE(rst_map_gpp), .groups = adl_community1_groups, .num_groups = ARRAY_SIZE(adl_community1_groups), .vw_base = DEFAULT_VW_BASE, @@ -151,8 +151,8 @@ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPD", .acpi_path = "\\_SB.PCI0.GPIO", - .reset_map = rst_map_com2, - .num_reset_vals = ARRAY_SIZE(rst_map_com2), + .reset_map = rst_map_gpd, + .num_reset_vals = ARRAY_SIZE(rst_map_gpd), .groups = adl_community2_groups, .num_groups = ARRAY_SIZE(adl_community2_groups), }, @@ -171,8 +171,8 @@ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_VGPIO", .acpi_path = "\\_SB.PCI0.GPIO", - .reset_map = rst_map, - .num_reset_vals = ARRAY_SIZE(rst_map), + .reset_map = rst_map_gpp, + .num_reset_vals = ARRAY_SIZE(rst_map_gpp), .groups = adl_community3_groups, .num_groups = ARRAY_SIZE(adl_community3_groups), }, @@ -192,8 +192,8 @@ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_FCE", .acpi_path = "\\_SB.PCI0.GPIO", - .reset_map = rst_map, - .num_reset_vals = ARRAY_SIZE(rst_map), + .reset_map = rst_map_gpp, + .num_reset_vals = ARRAY_SIZE(rst_map_gpp), .groups = adl_community4_groups, .num_groups = ARRAY_SIZE(adl_community4_groups), .vw_base = DEFAULT_VW_BASE, @@ -216,8 +216,8 @@ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_RSPI0", .acpi_path = "\\_SB.PCI0.GPIO", - .reset_map = rst_map, - .num_reset_vals = ARRAY_SIZE(rst_map), + .reset_map = rst_map_gpp, + .num_reset_vals = ARRAY_SIZE(rst_map_gpp), .groups = adl_community5_groups, .num_groups = ARRAY_SIZE(adl_community5_groups), } -- To view, visit https://review.coreboot.org/c/coreboot/+/60789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b8742c7a0cc1dc420e3e22e34a16355294ed61b Gerrit-Change-Number: 60789 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: payloads/U-Boot: use realpath for build directory
by Iru Cai (Code Review) 05 Jan '22

05 Jan '22

Iru Cai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60788 ) Change subject: payloads/U-Boot: use realpath for build directory ...................................................................... payloads/U-Boot: use realpath for build directory This is necessary when payloads/external/U-Boot/u-boot is a symbolic link, where u-boot/../build is not the specified build directory Change-Id: I940dc2b74294262db646b77af89c9194069bdcab Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M payloads/external/U-Boot/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/60788/1 diff --git a/payloads/external/U-Boot/Makefile b/payloads/external/U-Boot/Makefile index 07b6f48..d66b978 100644 --- a/payloads/external/U-Boot/Makefile +++ b/payloads/external/U-Boot/Makefile @@ -9,7 +9,7 @@ project_build_dir=build project_config_file=$(project_build_dir)/.config -make_args=-C $(project_dir) O=../build +make_args=-C $(project_dir) O=$(shell realpath $(project_build_dir)) unexport KCONFIG_AUTOHEADER unexport KCONFIG_AUTOCONFIG -- To view, visit https://review.coreboot.org/c/coreboot/+/60788 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I940dc2b74294262db646b77af89c9194069bdcab Gerrit-Change-Number: 60788 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/agah: Add new memory support
by Tony Huang (Code Review) 05 Jan '22

05 Jan '22

Tony Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60787 ) Change subject: mb/google/brya/var/agah: Add new memory support ...................................................................... mb/google/brya/var/agah: Add new memory support Do initial memory support for project agah BUG=b:210970640 TEST=FW_NAME=agah emerge-brya coreboot Change-Id: Iaeea12a9dd8110a499b5df4de89dc1f74b88a580 Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- A src/mainboard/google/brya/variants/agah/Makefile.inc A src/mainboard/google/brya/variants/agah/dram_id.generated.txt M src/mainboard/google/brya/variants/agah/memory/mem_parts_used.txt 3 files changed, 45 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/60787/1 diff --git a/src/mainboard/google/brya/variants/agah/Makefile.inc b/src/mainboard/google/brya/variants/agah/Makefile.inc new file mode 100644 index 0000000..af6c1e3 --- /dev/null +++ b/src/mainboard/google/brya/variants/agah/Makefile.inc @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# /home/tony/ChromeProject/chroot_tot/GOlang/go1.17.5.linux-amd64/go/bin/part_id_gen ADL lp4x /home/tony/ChromeProject/coreboot/src/mainboard/google/brya/variants/agah/ /home/tony/ChromeProject/coreboot/src/mainboard/google/brya/variants/agah/memory/mem_parts_used.txt + +SPD_SOURCES = +SPD_SOURCES += spd/lp4x/set-0/spd-4.hex # ID = 0(0b0000) Parts = MT53E1G32D2NP-046 WT:A +SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 1(0b0001) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D2NP-046 WT:E, MT53E512M32D1NP-046 WT:B, H54G46CYRBX267, K4U6E3S4AB-MGCL +SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR, MT53E1G32D2NP-046 WT:B, H54G56CYRBX247, K4UBE3D4AB-MGCL +SPD_SOURCES += spd/lp4x/set-0/spd-2.hex # ID = 3(0b0011) Parts = H9HCNNNFAMMLXR-NEE +SPD_SOURCES += spd/lp4x/set-0/spd-7.hex # ID = 4(0b0100) Parts = MT53E2G32D4NQ-046 WT:A diff --git a/src/mainboard/google/brya/variants/agah/dram_id.generated.txt b/src/mainboard/google/brya/variants/agah/dram_id.generated.txt new file mode 100644 index 0000000..20511a4 --- /dev/null +++ b/src/mainboard/google/brya/variants/agah/dram_id.generated.txt @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# /home/tony/ChromeProject/chroot_tot/GOlang/go1.17.5.linux-amd64/go/bin/part_id_gen ADL lp4x /home/tony/ChromeProject/coreboot/src/mainboard/google/brya/variants/agah/ /home/tony/ChromeProject/coreboot/src/mainboard/google/brya/variants/agah/memory/mem_parts_used.txt + +DRAM Part Name ID to assign +MT53E1G32D2NP-046 WT:A 0 (0000) +H9HCNNNBKMMLXR-NEE 1 (0001) +K4U6E3S4AA-MGCR 1 (0001) +MT53E512M32D2NP-046 WT:E 1 (0001) +H9HCNNNCPMMLXR-NEE 2 (0010) +K4UBE3D4AA-MGCR 2 (0010) +H9HCNNNFAMMLXR-NEE 3 (0011) +MT53E2G32D4NQ-046 WT:A 4 (0100) +MT53E512M32D1NP-046 WT:B 1 (0001) +MT53E1G32D2NP-046 WT:B 2 (0010) +H54G46CYRBX267 1 (0001) +K4U6E3S4AB-MGCL 1 (0001) +H54G56CYRBX247 2 (0010) +K4UBE3D4AB-MGCL 2 (0010) diff --git a/src/mainboard/google/brya/variants/agah/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/agah/memory/mem_parts_used.txt index 9621137..ca83c7f 100644 --- a/src/mainboard/google/brya/variants/agah/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/agah/memory/mem_parts_used.txt @@ -1,11 +1,14 @@ -# This is a CSV file containing a list of memory parts used by this variant. -# One part per line with an optional fixed ID in column 2. -# Only include a fixed ID if it is required for legacy reasons! -# Generated IDs are dependent on the order of parts in this file, -# so new parts must always be added at the end of the file! -# -# Generate an updated Makefile.inc and dram_id.generated.txt by running the -# part_id_gen tool from util/spd_tools. -# See util/spd_tools/README.md for more details and instructions. - -# Part Name +MT53E1G32D2NP-046 WT:A +H9HCNNNBKMMLXR-NEE +K4U6E3S4AA-MGCR +MT53E512M32D2NP-046 WT:E +H9HCNNNCPMMLXR-NEE +K4UBE3D4AA-MGCR +H9HCNNNFAMMLXR-NEE +MT53E2G32D4NQ-046 WT:A +MT53E512M32D1NP-046 WT:B +MT53E1G32D2NP-046 WT:B +H54G46CYRBX267 +K4U6E3S4AB-MGCL +H54G56CYRBX247 +K4UBE3D4AB-MGCL -- To view, visit https://review.coreboot.org/c/coreboot/+/60787 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaeea12a9dd8110a499b5df4de89dc1f74b88a580 Gerrit-Change-Number: 60787 Gerrit-PatchSet: 1 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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