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Change subject: soc/intel/ehl: Replace dt `HeciEnabled` by `CSE disable` config
......................................................................
Patch Set 3: Code-Review+1
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Change subject: soc/intel/skl: Replace dt `HeciEnabled` by `CSE disable` config
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
Note that the following boards don't specify `HeciEnabled` in the devicetree, so this patch would change the behavior for them (HECI would no longer be hidden):
kontron/bsl6
system76/kbl-u
hp/280_g2
intel/saddlebrook
supermicro/x11-lga1151-series
For now, I'd have these boards select the "hide HECI" Kconfig option so that this change doesn't change the code behavior, and adjust individual boards in follow-up commits if needed.
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Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60790 )
Change subject: drivers/ipmi: Change type of custom_count from int to size_t
......................................................................
drivers/ipmi: Change type of custom_count from int to size_t
The variable `custom_count` is the number of custom fields, so only
holds non-negative values, so change the struct member type from int to
size_t.
Change-Id: Ic35aafefc870092298523ba2e10adf4fcb687a01
Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de>
---
M src/drivers/ipmi/ipmi_ops.h
1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/60790/1
diff --git a/src/drivers/ipmi/ipmi_ops.h b/src/drivers/ipmi/ipmi_ops.h
index 60983b4..3f15a24 100644
--- a/src/drivers/ipmi/ipmi_ops.h
+++ b/src/drivers/ipmi/ipmi_ops.h
@@ -111,7 +111,7 @@
char *asset_tag;
char *fru_file_id;
char **product_custom;
- int custom_count; /* Number of custom fields */
+ size_t custom_count; /* Number of custom fields */
};
struct fru_board_info {
@@ -121,7 +121,7 @@
char *part_number;
char *fru_file_id;
char **board_custom;
- int custom_count;
+ size_t custom_count;
};
struct fru_chassis_info {
@@ -129,7 +129,7 @@
char *chassis_partnumber;
char *serial_number;
char **chassis_custom;
- int custom_count;
+ unsigned int custom_count;
};
struct fru_info_str {
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Change subject: soc/intel/skl: Replace dt `HeciEnabled` by `CSE disable` config
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60722/comment/13b9fdaa_01e61d0d
PS3, Line 9: Lists
nit: List
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Change subject: soc/intel/common/cse: Add config to disable CSE at pre-boot
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/common/block/cse/Kconfig:
https://review.coreboot.org/c/coreboot/+/60721/comment/14ecac92_bd8daef2
PS2, Line 13: This config decides the state of CSE/Heci1 device at the end of boot.
> How about renaming this to `DISABLE_HECI_AT_PRE_BOOT`?
Sure, then DISABLE_HECI1_AT_PRE_BOOT? to make sure we are trying to disable HECI1(CSE)
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Change subject: soc/intel/skl: Replace dt `HeciEnabled` by `CSE disable` config
......................................................................
Patch Set 3: Code-Review+1
(2 comments)
File src/mainboard/asrock/h110m/Kconfig:
https://review.coreboot.org/c/coreboot/+/60722/comment/09e6b74d_b41cc516
PS3, Line 6: select DISABLE_CSE_AT_PRE_BOOT
I think this board as well as some others doesn't require this, but I'll take care of them in follow-ups.
File src/soc/intel/skylake/finalize.c:
https://review.coreboot.org/c/coreboot/+/60722/comment/77c49b79_5dfd2c5a
PS3, Line 54: config = config_of(dev);
This is no longer used
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Change subject: drivers/ipmi: Use correct unsigned int length modifier
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS1:
> since the custom count should never be negative and from a brief look at the code it's either zero o […]
But it’s still not going to fix the issue, and is unrelated to this patch, isn’t it?
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Change subject: soc/intel/cnl: Replace `dt CSE dev state` by `CSE disable` config
......................................................................
Patch Set 3: Code-Review+1
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Change subject: mb/google/{drallion, hatch. sarien}: Rework CSE dt policy
......................................................................
Patch Set 3: Code-Review+1
(5 comments)
File src/mainboard/google/drallion/variants/drallion/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/60725/comment/4d44501b_1df7b496
PS3, Line 414:
nit: add another space to preserve alignment
File src/mainboard/google/hatch/Kconfig:
https://review.coreboot.org/c/coreboot/+/60725/comment/35393707_0daf43b5
PS3, Line 32: select DISABLE_CSE_AT_PRE_BOOT
Hatch and Puff use the same devicetree, shouldn't this be selected from `BOARD_GOOGLE_HATCH_COMMON`?
File src/mainboard/google/hatch/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/60725/comment/f49bd67f_89996460
PS3, Line 299:
nit: add another space to preserve alignment
File src/mainboard/google/sarien/variants/arcada/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/60725/comment/bdc5efa3_2f23e53e
PS3, Line 345:
nit: add another space to preserve alignment
File src/mainboard/google/sarien/variants/sarien/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/60725/comment/d7405d36_7b732c0d
PS3, Line 366:
nit: add another space to preserve alignment
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Sudheer Amrabadi has uploaded a new patch set (#32) to the change originally created by Ravi kumar. ( https://review.coreboot.org/c/coreboot/+/57449 )
Change subject: mb/google/herobrine : Add support for audio
......................................................................
mb/google/herobrine : Add support for audio
Add GPIO configuration for target specific i2s ports.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 developement board
Signed-off-by: Srinivasa Rao Mandadapu <srivasam(a)codeaurora.org>
Change-Id: I2ce95332f892d5d4acb2755307df84d37feb8002
---
M src/mainboard/google/herobrine/board.h
M src/mainboard/google/herobrine/chromeos.c
M src/mainboard/google/herobrine/mainboard.c
3 files changed, 28 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/57449/32
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