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Change subject: Denverton-NS boards: Factor out common PCI IRQ config
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Hmmm, interesting. Leaving this comment open.
Kyosti is correct that it is board-specific. I will endeavor to provide a patch that will make the correct routing information auto-generated for all platforms.
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Change subject: soc/intel/alderlake: Fix GPIO reset mapping as per GPIO BWG
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Patch Set 1: Code-Review+1
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Change subject: soc/intel/common/cse: Add config to disable CSE at pre-boot
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/common/block/cse/Kconfig:
https://review.coreboot.org/c/coreboot/+/60721/comment/0c426560_d07d43aa
PS2, Line 13: This config decides the state of CSE/Heci1 device at the end of boot.
> Sure, then DISABLE_HECI1_AT_PRE_BOOT? to make sure we are trying to disable HECI1(CSE)
Sounds good. Also, don't forget to update all the references to `CSE disable` in the patch train accordingly: Kconfig help texts, commit messages...
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Change subject: soc/intel/common/cse: Add config to disable CSE at pre-boot
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/common/block/cse/Kconfig:
https://review.coreboot.org/c/coreboot/+/60721/comment/cb79686a_8f83fa2d
PS2, Line 10: depends on SOC_INTEL_COMMON_BLOCK_CSE
Just noticed that this setting also shows up for APL, which unconditionally disables HECI: soc/intel/apollolake/cse.c function `heci_cse_lockdown()` unconditionally calls the `disable_heci1()` function. We could guard the `disable_heci1()` call with this Kconfig option, and override its default value in `soc/intel/apollolake/Kconfig` as follows:
config DISABLE_CSE_AT_PRE_BOOT
default y
This should be done in a separate commit.
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Change subject: soc/intel/icl: Replace dt `HeciEnabled` by `CSE disable` config
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
What about the intel/icelake_rvp mainboard? It doesn't specify `HeciEnabled`, so this change would result in the HECI device no longer being hidden.
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Change subject: soc/intel/adl: Replace dt `HeciEnabled` by `CSE disable` config
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Patch Set 2: Code-Review+1
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Change subject: soc/intel/tgl: Replace dt `HeciEnabled` by `CSE disable` config
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
File src/soc/intel/tigerlake/smihandler.c:
https://review.coreboot.org/c/coreboot/+/60730/comment/70210cc4_825e1826
PS2, Line 19: CONFIG(HECI_DISABLE_USING_SMM)
This is redundant because TGL selects `HECI_DISABLE_USING_SMM`. However, we can take care of this in a follow-up.
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Change subject: soc/intel/jsl: Replace dt `HeciEnabled` by `CSE disable` config
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> What about the intel/jslrvp mainboard? It doesn't specify `HeciEnabled`, so this change would result […]
er, intel/jasperlake_rvp
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Change subject: soc/intel/jsl: Replace dt `HeciEnabled` by `CSE disable` config
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
What about the intel/jslrvp mainboard? It doesn't specify `HeciEnabled`, so this change would result in the HECI device no longer being hidden.
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