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Change subject: util/ifdtool: Add support for Denverton platforms
......................................................................
Patch Set 3:
(1 comment)
File util/ifdtool/ifdtool.c:
https://review.coreboot.org/c/coreboot/+/60737/comment/79d0e6c2_675f7dcd
PS3, Line 717: has_10gbe_A = (platform == PLATFORM_DNV);
: has_10gbe_B = (platform == PLATFORM_DNV);
> Well this was my suggestion, I don't know if there is platform that could only have A or B. […]
OK, looks like Lewisburg only has one 10GbE region
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Change subject: mb/google/brya: Create agah variant
......................................................................
Patch Set 2: Code-Review+2
(2 comments)
Patchset:
PS2:
The build failure is not because of this patch, the tree was broken, please rebase on master again and jenkins should give you Verified+1
File src/mainboard/google/brya/Kconfig.name:
https://review.coreboot.org/c/coreboot/+/60785/comment/e997eeec_4893ce4e
PS2, Line 146: config BOARD_GOOGLE_AGAH
nit: blank line between config options
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Change subject: cpu/x86/lapic: Fix choice X2APIC_ONLY
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60213/comment/2e279028_623bef2e
PS2, Line 11: avoid entering a printk() and acquiring console_lock and
: dead-locking.
Ah yes, excerpt from document 493770 (Haswell BWG):
> Note: The WRMSR instruction serializing semantic is relaxed for writes to the extended xAPIC MSRs. Software must not use WRMSR instructions which access extended xAPIC MSRs as a serializing instruction.
And the document doesn't tell what one should use to serialize things instead...
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Change subject: soc/amd/common/lpc/espi_util: move register definitions to header file
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Patch Set 2: Code-Review+2
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Change subject: mb/google/brya/(anahera,primus): Use eNEM for CAR by default
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Patch Set 3: Code-Review+2
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Change subject: mb/google/brya: Use PAD config macro to add lock support
......................................................................
Patch Set 7:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60320/comment/0d965107_9c8c6716
PS7, Line 13: TEST=Boot to OS, issue warm reboot and see no issue with any IP
: enumeration
But are the corresponding GPIO pads actually locked? Or does the coreboot log contain a bunch of "gpio_lock_pads: Error: must be called from SMM!" lines?
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Change subject: soc/intel/common/gpio: Rework PAD config macro to add lock support
......................................................................
Patch Set 4:
(2 comments)
File src/soc/intel/common/block/gpio/gpio.c:
https://review.coreboot.org/c/coreboot/+/60774/comment/f84a45e2_9c5ea5c5
PS4, Line 345: gpio_lock_pad(cfg->pad, cfg->action);
Doesn't this need to run in SMM?
File src/soc/intel/common/block/include/intelblocks/gpio_defs.h:
https://review.coreboot.org/c/coreboot/+/60774/comment/8250aa23_5ab84ab5
PS4, Line 203: PWROK
> should we use RSMRST here?
Why not keep parity with the existing `PAD_CFG_NF()` macro and take the reset type as parameter?
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Change subject: soc/intel/common/gpio: Skip GPP pad lock config if config is not set
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Patch Set 3: Code-Review+1
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