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Change subject: mb/google/brya/var/anahera: Fine tune I2C frequency
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/google/dedede/var/bugzzy: Increase reset_delay_ms for touch screen
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS2:
> Thanks!
Please update the commit message with that information next time.
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Change subject: mb/google/brya/var/primus: Fix some GPIO programming
......................................................................
Patch Set 29: Code-Review+2
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Change subject: mb/google/dedede/var/bugzzy: Increase reset_delay_ms for touch screen
......................................................................
mb/google/dedede/var/bugzzy: Increase reset_delay_ms for touch screen
Touch screen IC couldn't wake up after rebind with current 120 ms delay
after reset since the HID would be activated after 200 ms from reset.
This change increases the reset_delay_ms for touch device to 200 ms to
wait for the touch HID to be ready.
BUG=b:204950000
BRANCH=dedede
TEST=Verified that TSP IC could wake up after rebind
Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com>
Change-Id: I34cbc82e2d691266389d498e77d8389cdee23efe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60273
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Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
index de1e46d..b56fb30 100644
--- a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
@@ -214,7 +214,7 @@
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)"
register "generic.probed" = "1"
register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)"
- register "generic.reset_delay_ms" = "120"
+ register "generic.reset_delay_ms" = "200"
register "generic.reset_off_delay_ms" = "2"
register "generic.has_power_resource" = "1"
register "hid_desc_reg_offset" = "0x1"
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Change subject: mb/google/dedede/var/bugzzy: Increase reset_delay_ms for touch screen
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Patchset:
PS2:
> We didn't get a spec document but according to himax HID will be activated after 200ms: https://part […]
Thanks!
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Change subject: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F
......................................................................
Patch Set 72:
(1 comment)
File src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/37441/comment/2ec6b0f5_5b4c6c0e
PS64, Line 6:
> Hmmm, not sure how to obtain the values and I haven't seen any side-effects of not specifying them. […]
proooobably not required, since the supermicro server boards don't have much acpi stuff. check the DSDT for any GPE (_Lxx)
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Change subject: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F
......................................................................
Patch Set 72:
(2 comments)
Patchset:
PS70:
> MAINBOARD_HAS_SPI_TPM is wrong. Try this: […]
oh, and probably the devicetree needs this:
device pci 1f.0 on
......
.....
chip drivers/pc80/tpm # TPM
device pnp 0c31.0 on end
end
end
File src/mainboard/supermicro/x11-lga1151v2-series/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/37441/comment/38dbe278_fbbafe84
PS72, Line 100:
probably required for tpm support:
chip drivers/pc80/tpm # TPM
device pnp 0c31.0 on end
end
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Change subject: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F
......................................................................
Patch Set 72:
(1 comment)
File src/mainboard/supermicro/x11-lga1151v2-series/Kconfig:
https://review.coreboot.org/c/coreboot/+/37441/comment/b8524b96_95e40442
PS72, Line 15:
missing:
select MAINBOARD_HAS_LPC_TPM
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Change subject: soc/intel/common/gpio: Rework PAD config macro to add lock support
......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/gpio_defs.h:
https://review.coreboot.org/c/coreboot/+/60774/comment/ff2aed98_de8a0d18
PS4, Line 203: PWROK
> Why not keep parity with the existing `PAD_CFG_NF()` macro and take the reset type as parameter?
@Angel, there is a design gap between GPIO PAD reset type and PAD lock configuration reset type. Hence, we wish to force PAD reset type in sync with lock reset type which is POWER GOOD. Please find detailed analysis below.
As per GPIO BWG, there are 4 types of GPIO reset types
Power Good (RSMRST# for GPP) - (Value 00) = Doesn't allow GPP reset except Deep Sx and G3. (Read as Sx state doesn't reset the GPP)
Deep (Value 01) = Almost same #1
Host Reset/PLTRST (Value 10) = Allow to reset the GPP in warm, Sx state etc.
RSMRST for GPD/Reserved for GPP
Now the Pad Config Lock for a GPP allows locking specific register fields in the PAD configuration register. The Pad Config Lock registers reset type is default hardcoded to #1 Power Good as per EDS) and it's "not" configurable by DW0.PadRstCfg. It may appear that for a GPP, the Pad Reset Config (DW0 Bit 31) is configured differently from #1 Power Good. This would create confusion where the Pad configuration is returned to its default value and its still lock, this would prevent SW to reprogram the GPP.
Hence, it's recommended to change the Pad Reset Config for lock GPP as #1 Power Good so that pad configuration and lock bit can be reset at the same time.
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