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Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60833 )
Change subject: soc/mediatek/mt8186: revise wrong setting of devapc
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60833/comment/0e8af188_df4dc4e0
PS3, Line 7: revise
if this is fixing something then it's fix instead of revise.
maybe
fix incorrect devapc settings
https://review.coreboot.org/c/coreboot/+/60833/comment/cc6e6126_80e90f23
PS3, Line 9: We need to protect debugsys for firmware image without serial console.
: Original settings for protecting debugsys is wrong which will cause some
: hardware modules failed to set their registers correctly.
can you explain why moving it from one function to another is the right fix?
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Hello build bot (Jenkins), Maulik V Vaghela, Tim Wawrzynczak, Nick Vaccaro, Angel Pons, Meera Ravindranath, Patrick Rudolph, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/60774
to look at the new patch set (#8).
Change subject: soc/intel/common/gpio: Rework PAD config macro to add lock support
......................................................................
soc/intel/common/gpio: Rework PAD config macro to add lock support
This patch creates new GPIO PAD configuration macros that
would help to perform GPIO pad configuration and pad lock
configuration as well.
List of new macros are:
1. PAD_CFG_NF_LOCK
2. PAD_CFG_GPO_LOCK
3. PAD_CFG_GPI_LOCK
4. PAD_CFG_GPI_TRIG_OWN_LOCK
5. PAD_CFG_GPI_GPIO_DRIVER_LOCK
6. PAD_CFG_GPI_INT_LOCK
7. PAD_CFG_GPI_APIC_LOCK
8. PAD_CFG_GPI_IRQ_WAKE_LOCK
Mainboard users can use the above macros to lock the PAD after
configuration.
So far on IA chipset. the default GPIO pad lock configuration reset
type is POWERGOOD hence, its recommended as per GPIO BWG (doc: 630603)
to configure the GPP PAD reset type as same as lock configuration
reset type to avoid GPP reset value misconfiguration issue.
BUG=b:211573253, b:211950520
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ibf8b0a845005ad545266d995449d0aa711f45a61
---
M src/soc/intel/common/block/gpio/gpio.c
M src/soc/intel/common/block/include/intelblocks/gpio.h
M src/soc/intel/common/block/include/intelblocks/gpio_defs.h
3 files changed, 81 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/60774/8
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EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60388 )
Change subject: mb/google/brya/var/kano: Disable autonomous GPIO power management
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60388/comment/b1a07006_06241e2f
PS3, Line 11:
> For existing cr50 stock, this is the FW version that comes straight out of the factory, so the first […]
@Tim, this issue hit ADL everywhere.
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Subrata Banik has uploaded a new patch set (#10) to the change originally created by Meera Ravindranath. ( https://review.coreboot.org/c/coreboot/+/60320 )
Change subject: mb/google/brya: Use PAD config macro to add lock support
......................................................................
mb/google/brya: Use PAD config macro to add lock support
Use PAD config macro to add lock support for all the gpios used
in CB:58352 CB:58353.
BUG=b:211573253
TEST=Boot to OS, issue warm reboot and see no issue with any IP
enumeration
Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com>
Change-Id: I558bab39f935ab31a89541c6498a73af70cbf9ee
---
M src/mainboard/google/brya/variants/baseboard/brya/gpio.c
1 file changed, 42 insertions(+), 42 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/60320/10
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Hello build bot (Jenkins), Maulik V Vaghela, Tim Wawrzynczak, Nick Vaccaro, Angel Pons, Meera Ravindranath, Patrick Rudolph, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/60774
to look at the new patch set (#7).
Change subject: soc/intel/common/gpio: Rework PAD config macro to add lock support
......................................................................
soc/intel/common/gpio: Rework PAD config macro to add lock support
This patch creates new GPIO PAD configuration macros that
would help to perform GPIO pad configuration and pad lock
configuration as well.
List of new macros are:
1. PAD_CFG_NF_LOCK
2. PAD_CFG_GPO_LOCK
3. PAD_CFG_GPI_LOCK
4. PAD_CFG_GPI_TRIG_OWN_LOCK
5. PAD_CFG_GPI_GPIO_DRIVER_LOCK
6. PAD_CFG_GPI_INT_LOCK
7. PAD_CFG_GPI_APIC_LOCK
8. PAD_CFG_GPI_IRQ_WAKE_LOCK
Mainboard users can use the above macros to lock the PAD after
configuration.
So far on IA chipset. the default GPIO pad lock configuration reset
type is POWERGOOD hence, its recommended as per GPIO BWG (doc: 630603)
to configure the GPP PAD reset type as same as lock configuration
reset type to avoid GPP reset value misconfiguration issue.
BUG=b:211573253, b:211950520
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ibf8b0a845005ad545266d995449d0aa711f45a61
---
M src/soc/intel/common/block/gpio/gpio.c
M src/soc/intel/common/block/include/intelblocks/gpio.h
M src/soc/intel/common/block/include/intelblocks/gpio_defs.h
3 files changed, 81 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/60774/7
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Change subject: soc/intel/common/gpio: Rework PAD config macro to add lock support
......................................................................
Patch Set 5:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/gpio_defs.h:
https://review.coreboot.org/c/coreboot/+/60774/comment/fa0643e8_249115bb
PS4, Line 203: PWROK
> You can find this description in doc 630603 (as mentioned by Intel)
Also, I have also updated the commit msg with this recommendation. Are you recommending this to capture in some program file as well ?
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Change subject: soc/intel/common/gpio: Perform GPIO PAD lock outside SMM
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60801/comment/c5c2a301_e8d21233
PS1, Line 9: This patch performs GPIO PAD lock configuration in non-smm
: mode. Typically, coreboot enables SMI at latest boot phase
: post FSP-S, hence, FSP-S might get chance to perform GPP lock
: configuration. With this code changes, coreboot can be able to
: perform GPIO PAD lock configuration early in the boot flow,
: prior to calling FSP-S.
> Please reflow for 72 characters per line.
Ack
File src/soc/intel/common/block/gpio/gpio.c:
https://review.coreboot.org/c/coreboot/+/60801/comment/bf6d33d4_96145367
PS1, Line 569:
> Can we do a check for BIOS_DONE. […]
@Tim, can you please help me to understand your comment above.
This is what I understood:
You are asking to check if MSR(0x151) bit 0 (ENABLE_IA_UNTRUSTED) is set or not? if not set then coreboot returns -1 and exit from here. is that what you meant ?
But looks like BIOS_DONE MSR 0x151 is being set as part of FSP-S doing CPU feature programming (SetBiosDone Start) hence, prior to that, BIT 0 would always return `0` and we won't be able to perform GPP lock using this function (outside SMM). Note: this function might get called from coreboot gpio programming prior to FSP-S being call.
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Hsuan-ting Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59714 )
Change subject: util/cbfstool: Port elogtool to libflashrom
......................................................................
Patch Set 10:
(1 comment)
File util/cbfstool/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/59714/comment/aa928171_cfd0d072
PS10, Line 156: $(HOSTPKGCONFIG) --exists flashrom || \
A note that coreboot-sdk still does not support this --
(tried it in my docker)
But it seems that we did not really build elogtool in Jenkins:
(ref: https://qa.coreboot.org/job/coreboot-gerrit/192039/testReport/(root)/util/a…)
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Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60213 )
Change subject: cpu/x86/lapic: Fix choice X2APIC_ONLY
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60213/comment/56fd5f27_4a43e2a8
PS2, Line 11: avoid entering a printk() and acquiring console_lock and
: dead-locking.
> `mfence; lfence` […]
The ones Angel referred to in linux kernel seem to serve different purpose; the fence are inserted prior to the IPI? I think that is required for the raised interrupt service to not fetch stale data from memory?
I can test on a intel/denverton platform, maybe this weekend.
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