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Change subject: soc/intel/common/cse: Add config to disable HECI1 at pre-boot
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/common/block/cse/Kconfig:
https://review.coreboot.org/c/coreboot/+/60721/comment/75dcf925_72f173a5
PS2, Line 10: depends on SOC_INTEL_COMMON_BLOCK_CSE
> Sure, I will address this in subsequent CL. Thanks for highlighting.
Here is CB:60835 for review
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Change subject: soc/intel/common/block/pcie/rtd3: Update ACPI methods for CPU PCIe RPs
......................................................................
Patch Set 5: Code-Review+1
(2 comments)
File src/soc/intel/common/block/pcie/rtd3/rtd3.c:
https://review.coreboot.org/c/coreboot/+/60183/comment/31dd4a5c_7ba24f0c
PS4, Line 284: printk(BIOS_ERR, "%s: Unknown PCIe RP\n", __func__);
do we need to maintain this msg in https://review.coreboot.org/c/coreboot/+/60183/4..5/src/soc/intel/common/bl… ?
File src/soc/intel/common/block/pcie/rtd3/rtd3.c:
https://review.coreboot.org/c/coreboot/+/60183/comment/f96a329c_df136140
PS5, Line 293: CPU
nit: `get_pcie_rp_pmc_idx()` function can return -1 irrespective of being PCH or CPU hence just *CPU* in debug log might be misleading? Can we go for more generic word, may be PCIe(CPU/PCH)?
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Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60835 )
Change subject: soc/intel/apl: Use Kconfig to disable HECI1
......................................................................
soc/intel/apl: Use Kconfig to disable HECI1
This patch makes DISABLE_HECI1_AT_PRE_BOOT=y default for Apollo Lake
and ensures disable_heci1() is guarded against this config.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I7ac0cad97fcd42b2c6386693319d863352356864
---
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/apollolake/cse.c
2 files changed, 5 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/60835/1
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 45e21dd..d3f7332 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -116,6 +116,9 @@
# provide a custom media driver that facilitates mapping
select X86_CUSTOM_BOOTMEDIA
+config DISABLE_HECI1_AT_PRE_BOOT
+ default y
+
config MAX_CPUS
int
default 4
diff --git a/src/soc/intel/apollolake/cse.c b/src/soc/intel/apollolake/cse.c
index 24fb417..29d0a5e 100644
--- a/src/soc/intel/apollolake/cse.c
+++ b/src/soc/intel/apollolake/cse.c
@@ -206,7 +206,8 @@
* It is safe to disable HECI1 now since we won't be talking to the ME
* anymore.
*/
- disable_heci1();
+ if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
+ disable_heci1();
}
BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, fpf_blown, NULL);
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Change subject: soc/intel/common/cse: Add config to disable HECI1 at pre-boot
......................................................................
Patch Set 3:
(2 comments)
File src/soc/intel/common/block/cse/Kconfig:
https://review.coreboot.org/c/coreboot/+/60721/comment/db01de8b_8edfef4c
PS2, Line 10: depends on SOC_INTEL_COMMON_BLOCK_CSE
> Just noticed that this setting also shows up for APL, which unconditionally disables HECI: soc/intel […]
Sure, I will address this in subsequent CL. Thanks for highlighting.
https://review.coreboot.org/c/coreboot/+/60721/comment/a15876d9_566c3ac9
PS2, Line 13: This config decides the state of CSE/Heci1 device at the end of boot.
> Sounds good. […]
Ack
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: soc/intel/common/cse: Add config to disable HECI1 at pre-boot
......................................................................
soc/intel/common/cse: Add config to disable HECI1 at pre-boot
This patch adds a config to let mainboard users choose the correct
state of HECI1(CSE) device prior to handing off to payload.
`DISABLE_HECI1_AT_PRE_BOOT` config to make HECI1 function disable
at pre-boot.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I7e127816c506df3ac0cf973b69021d02d05bef4a
---
M src/soc/intel/common/block/cse/Kconfig
1 file changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/60721/3
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Change subject: Revert "mb/google/dedede/var/beadrix: Remove SD controller"
......................................................................
Patch Set 2: Code-Review+1
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Change subject: Revert "mb/google/dedede/var/beadrix: Remove SD controller"
......................................................................
Revert "mb/google/dedede/var/beadrix: Remove SD controller"
This reverts commit bcd7873ea80be0ee576a10e6a11b7dcf8294ffb5.
Reason for revert: It makes cret can't boot to os without depthcharge change. The depthcharge change related with fw_config and will effect other variants.
BUG=b:204882915
BRANCH=None
TEST=Build and boot into OS.
Signed-off-by: Teddy Shih <teddyshih(a)ami.corp-partner.google.com>
Change-Id: Id5e76fc78a56d30caf9f805a8a430f176a653bbe
---
M src/mainboard/google/dedede/variants/beadrix/overridetree.cb
1 file changed, 0 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/60849/2
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Change subject: Revert "mb/google/dedede/var/beadrix: Remove SD controller"
......................................................................
Revert "mb/google/dedede/var/beadrix: Remove SD controller"
This reverts commit bcd7873ea80be0ee576a10e6a11b7dcf8294ffb5.
Reason for revert: It makes cret can't boot to os without depthcharge change. The depthcharge change related with fw_config and will effect other variants.
BUG=b:204882915
BRANCH=None
TEST=Build and boot into OS.
Change-Id: Id5e76fc78a56d30caf9f805a8a430f176a653bbe
---
M src/mainboard/google/dedede/variants/beadrix/overridetree.cb
1 file changed, 0 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/60849/1
diff --git a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb
index c64765b..97e77439 100644
--- a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb
@@ -52,7 +52,6 @@
end
end
end # USB xHCI
- device pci 14.5 off end # SDCard
device pci 15.0 on
chip drivers/i2c/hid
register "generic.hid" = ""PIXA2635""
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