coreboot-gerrit January 2022

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Change in coreboot[master]: mb/google/{drallion, hatch. sarien}: Rework CSE dt policy
by Subrata Banik (Code Review) 06 Jan '22

06 Jan '22

Attention is currently required from: Felix Singer, Tim Wawrzynczak, Angel Pons, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60725 ) Change subject: mb/google/{drallion, hatch. sarien}: Rework CSE dt policy ...................................................................... Patch Set 3: (5 comments) File src/mainboard/google/drallion/variants/drallion/devicetree.cb: https://review.coreboot.org/c/coreboot/+/60725/comment/f9a73ffe_88f3c5bb PS3, Line 414: > nit: add another space to preserve alignment Ack File src/mainboard/google/hatch/Kconfig: https://review.coreboot.org/c/coreboot/+/60725/comment/927c4756_937e48d5 PS3, Line 32: select DISABLE_CSE_AT_PRE_BOOT > Hatch and Puff use the same devicetree, shouldn't this be selected from `BOARD_GOOGLE_HATCH_COMMON`? Ack File src/mainboard/google/hatch/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/60725/comment/1c6e88fe_240d6e9d PS3, Line 299: > nit: add another space to preserve alignment Ack File src/mainboard/google/sarien/variants/arcada/devicetree.cb: https://review.coreboot.org/c/coreboot/+/60725/comment/81fb4c4f_5e5393c5 PS3, Line 345: > nit: add another space to preserve alignment Ack File src/mainboard/google/sarien/variants/sarien/devicetree.cb: https://review.coreboot.org/c/coreboot/+/60725/comment/f77bec83_b75d7463 PS3, Line 366: > nit: add another space to preserve alignment Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/60725 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd57d2713fe83de5fb93e399734414ca99977d0c Gerrit-Change-Number: 60725 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Thu, 06 Jan 2022 12:51:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/{drallion, hatch. sarien}: Rework CSE dt policy
by Subrata Banik (Code Review) 06 Jan '22

06 Jan '22

Attention is currently required from: Felix Singer, Subrata Banik, Tim Wawrzynczak, EricR Lai. Hello Felix Singer, build bot (Jenkins), Tim Wawrzynczak, Angel Pons, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60725 to look at the new patch set (#4). Change subject: mb/google/{drallion, hatch. sarien}: Rework CSE dt policy ...................................................................... mb/google/{drallion, hatch. sarien}: Rework CSE dt policy This patch makes dt CSE PCI device `on` by default and Mainboards selects DISABLE_HECI1_AT_PRE_BOOT config to make HECI1 function disable at pre-boot instead of making dt CSE device 'off'. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Idd57d2713fe83de5fb93e399734414ca99977d0c --- M src/mainboard/google/drallion/Kconfig M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/sarien/Kconfig M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 7 files changed, 7 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/60725/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/60725 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd57d2713fe83de5fb93e399734414ca99977d0c Gerrit-Change-Number: 60725 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/gpio: Perform GPIO PAD lock outside SMM
by Subrata Banik (Code Review) 06 Jan '22

06 Jan '22

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Paul Menzel, Meera Ravindranath, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60801 ) Change subject: soc/intel/common/gpio: Perform GPIO PAD lock outside SMM ...................................................................... Patch Set 7: (1 comment) Patchset: PS4: > Verified Subrata, does not break anything. Thanks Meera -- To view, visit https://review.coreboot.org/c/coreboot/+/60801 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71b4e2f24303b6acb56debd581bd6bc818b6f926 Gerrit-Change-Number: 60801 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 06 Jan 2022 12:32:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: fix incorrect devapc settings
by Rex-BC Chen (Code Review) 06 Jan '22

06 Jan '22

Attention is currently required from: Paul Menzel, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60833 ) Change subject: soc/mediatek/mt8186: fix incorrect devapc settings ...................................................................... Patch Set 6: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/60833/comment/c0a0da9d_b3677c72 PS5, Line 11: failed > to fail Done Patchset: PS5: > Thank you for improving the commit message. You are welcome, and thanks for your review! -- To view, visit https://review.coreboot.org/c/coreboot/+/60833 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibce626386ac1f8de42f8717c4ad9ba403640b3ec Gerrit-Change-Number: 60833 Gerrit-PatchSet: 6 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 06 Jan 2022 12:06:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: fix incorrect devapc settings
by Rex-BC Chen (Code Review) 06 Jan '22

06 Jan '22

Attention is currently required from: Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60833 ) Change subject: soc/mediatek/mt8186: fix incorrect devapc settings ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/60833 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibce626386ac1f8de42f8717c4ad9ba403640b3ec Gerrit-Change-Number: 60833 Gerrit-PatchSet: 6 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 06 Jan 2022 12:05:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: DO-NOT-SUBMIT: MT8186 Corsola review ToT
by Rex-BC Chen (Code Review) 06 Jan '22

06 Jan '22

Attention is currently required from: Rex-BC Chen. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58639 to look at the new patch set (#93). Change subject: DO-NOT-SUBMIT: MT8186 Corsola review ToT ...................................................................... DO-NOT-SUBMIT: MT8186 Corsola review ToT Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I53f304822c426417bb58037daa536bfb8dda1db3 --- M README.md 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/58639/93 -- To view, visit https://review.coreboot.org/c/coreboot/+/58639 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53f304822c426417bb58037daa536bfb8dda1db3 Gerrit-Change-Number: 58639 Gerrit-PatchSet: 93 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8186: fix incorrect devapc settings
by Rex-BC Chen (Code Review) 06 Jan '22

06 Jan '22

Attention is currently required from: Rex-BC Chen, Yu-Ping Wu. Hello Hung-Te Lin, build bot (Jenkins), Paul Menzel, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60833 to look at the new patch set (#6). Change subject: soc/mediatek/mt8186: fix incorrect devapc settings ...................................................................... soc/mediatek/mt8186: fix incorrect devapc settings We need to protect debugsys for firmware image without serial console. Original settings for protecting debugsys is wrong which will cause some hardware modules to fail to set their registers correctly. We move the setting from MM_AO_APC to INFRA_AO_APC because the setting of debugsys is defined in INFRA_AO_APC and set the debugsys index to correct value of 94. BUG=b:213125558 TEST=all modules work normally using image without serial console. Signed-off-by: Runyang Chen <runyang.chen(a)mediatek.corp-partner.google.com> Change-Id: Ibce626386ac1f8de42f8717c4ad9ba403640b3ec --- M src/soc/mediatek/mt8186/devapc.c M src/soc/mediatek/mt8186/include/soc/devapc.h 2 files changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/60833/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/60833 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibce626386ac1f8de42f8717c4ad9ba403640b3ec Gerrit-Change-Number: 60833 Gerrit-PatchSet: 6 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: tree-wide: Resource transitions _range/resource64()
by Arthur Heymans (Code Review) 06 Jan '22

06 Jan '22

Attention is currently required from: Hung-Te Lin, Raul Rangel, Philipp Hug, Mariusz Szafrański, Julius Werner, Angel Pons, Kyösti Mälkki, Andrey Petrov, Patrick Rudolph, Xi Chen, Jason Glenesk, Damien Zammit, Marshall Dawson, Christian Walter, Tim Wawrzynczak, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Ron Minnich, Felix Held. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55937 ) Change subject: tree-wide: Resource transitions _range/resource64() ...................................................................... Patch Set 1: (1 comment) File src/southbridge/amd/cimx/sb800/lpc.c: https://review.coreboot.org/c/coreboot/+/55937/comment/000c8d5a_a3673c7d PS1, Line 22: / 1024) * KiB remove? -- To view, visit https://review.coreboot.org/c/coreboot/+/55937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I903c0183e7fc6b14aeb00325cd10cd48682c2e85 Gerrit-Change-Number: 55937 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Damien Zammit Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 06 Jan 2022 11:58:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp: Don't handle FSP reserved memory explicitly
by Arthur Heymans (Code Review) 06 Jan '22

06 Jan '22

Attention is currently required from: Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Christian Walter, Patrick Rudolph, Tim Chu. Hello Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Christian Walter, Arthur Heymans, Patrick Rudolph, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60838 to look at the new patch set (#2). Change subject: soc/intel/xeon_sp: Don't handle FSP reserved memory explicitly ...................................................................... soc/intel/xeon_sp: Don't handle FSP reserved memory explicitly FSP reserved memory is allocated inside cbmem which already gets marked as a reserved memory region, so there is no need to do this explicitly. Change-Id: I39ec70bd9404d7bc2a4228c4364e4cc86f95d7c1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/uncore.c 1 file changed, 3 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/60838/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39ec70bd9404d7bc2a4228c4364e4cc86f95d7c1 Gerrit-Change-Number: 60838 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/xeon_sp: Don't handle FSP reserved memory explicitly
by Arthur Heymans (Code Review) 06 Jan '22

06 Jan '22

Attention is currently required from: Arthur Heymans. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/60838 to review the following change. Change subject: soc/intel/xeon_sp: Don't handle FSP reserved memory explicitly ...................................................................... soc/intel/xeon_sp: Don't handle FSP reserved memory explicitly FSP reserved memory is allocated inside cbmem which already gets marked as a reserved memory region, so there is no need to do this explicitly. Change-Id: I39ec70bd9404d7bc2a4228c4364e4cc86f95d7c1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/uncore.c 1 file changed, 3 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/60838/1 diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index e51efbd..bde89e9 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -13,6 +13,7 @@ #include <fsp/util.h> #include <security/intel/txt/txt_platform.h> #include <security/intel/txt/txt.h> +#include <stdint.h> struct map_entry { uint32_t reg; @@ -165,10 +166,8 @@ static void mc_add_dram_resources(struct device *dev, int *res_count) { - struct range_entry fsp_mem; uint64_t base_kb; uint64_t size_kb; - uint64_t top_of_ram; uint64_t mc_values[NUM_MAP_ENTRIES]; struct resource *resource; int index = *res_count; @@ -177,34 +176,22 @@ if (dev->bus->secondary != 0) return; - fsp_find_reserved_memory(&fsp_mem); - /* Read in the MAP registers and report their values. */ mc_read_map_entries(dev, &mc_values[0]); mc_report_map_entries(dev, &mc_values[0]); - top_of_ram = range_entry_base(&fsp_mem) - 1; - printk(BIOS_SPEW, "cbmem_top: 0x%lx, fsp range: [0x%llx - 0x%llx], top_of_ram: 0x%llx\n", - (uintptr_t) cbmem_top(), range_entry_base(&fsp_mem), - range_entry_end(&fsp_mem), top_of_ram); - /* Conventional Memory (DOS region, 0x0 to 0x9FFFF) */ base_kb = 0; size_kb = (0xa0000 >> 10); LOG_MEM_RESOURCE("legacy_ram", dev, index, base_kb, size_kb); ram_resource(dev, index++, base_kb, size_kb); - /* 1MB -> top_of_ram i.e., fsp_mem_base+1*/ + /* 1MB -> top_of_ram i.e., cbmem_top */ base_kb = (0x100000 >> 10); - size_kb = (top_of_ram - 0xfffff) >> 10; + size_kb = ((uintptr_t)cbmem_top() - 1 * MiB) >> 10; LOG_MEM_RESOURCE("low_ram", dev, index, base_kb, size_kb); ram_resource(dev, index++, base_kb, size_kb); - /* fsp_mem_base -> cbmem_top */ - base_kb = top_of_ram / KiB; - size_kb = ((uintptr_t)cbmem_top() - top_of_ram) / KiB; - reserved_ram_resource(dev, index++, base_kb, size_kb); - /* * FSP meomoy, CBMem regions are already added as reserved * Add TSEG and MESEG Regions as reserved memory -- To view, visit https://review.coreboot.org/c/coreboot/+/60838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39ec70bd9404d7bc2a4228c4364e4cc86f95d7c1 Gerrit-Change-Number: 60838 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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coreboot-gerrit January 2022