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Vaibhav Shankar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56662 )
Change subject: Revert "src/soc/intel/cannonlake: Update C-state latency control limits"
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Patch Set 1:
(1 comment)
Patchset:
PS1:
The original patch is not a hack. The IRTL values are based out of extensive silicon testing for S0ix on Cannon lake platfrom(initial 10nm).
Please note the current IRTL limits are for 14nm process and does not work on 10nm proess.
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56756 )
Change subject: mb/amd/bilby: Add support for HDMI display
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Patch Set 2:
(1 comment)
File src/mainboard/amd/bilby/mainboard.c:
https://review.coreboot.org/c/coreboot/+/56756/comment/773a4d29_1e10a3d6
PS2, Line 96: gpio_output(display_sel[idx], 0);
GPIO 31 gets configured as input here https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/sr… and GPIO 29 doesn't get configured at all, so i'd configure the GPIOs here in both cases and also remove the GPIO setting in the file linked above
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Change subject: soc/intel/cannonlake: Disable `TccOffsetClamp` if no offset is given
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Patch Set 1: Code-Review+2
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Change subject: soc/intel/broadwell: Replace soc/intel/common include
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Patch Set 6:
(1 comment)
Patchset:
PS5:
> Ideally, everyone would use the code in `device/azalia_device`. […]
ok
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Change subject: mb/amd/bilby: Enable DP2 and DP3 enumeration
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Patch Set 2: Code-Review+2
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Change subject: libpayload: Mark Intel 300 series AHCI as tested
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Patch Set 1: Code-Review+2
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Change subject: soc/intel/cannonlake: Allow to configure maximum package C state
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Patch Set 1: Code-Review+2
(1 comment)
Patchset:
PS1:
I don't really like the magic 0xf mask
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