coreboot-gerrit August 2021

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Change in coreboot[master]: mb/google/dedede/var/cappy2: Add camera support
by Sunwei Li (Code Review) 03 Aug '21

03 Aug '21

Attention is currently required from: Sunwei Li, Henry Sun, Bob Moragues, Weimin Wu. Hello build bot (Jenkins), Henry Sun, Bob Moragues, Aseda Aboagye, Weimin Wu, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56647 to look at the new patch set (#6). Change subject: mb/google/dedede/var/cappy2: Add camera support ...................................................................... mb/google/dedede/var/cappy2: Add camera support Add camera support in devicetree and associated GPIO configuration. BUG=b:193397569 BRANCH=dedede TEST=Camera function is OK Signed-off-by: Sunwei Li <lisunwei(a)huaqin.corp-partner.google.com> Change-Id: I3275ab408f6a03735a35eaa8025c36df09c9898c --- A src/mainboard/google/dedede/variants/cappy2/Makefile.inc A src/mainboard/google/dedede/variants/cappy2/gpio.c M src/mainboard/google/dedede/variants/cappy2/overridetree.cb 3 files changed, 36 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/56647/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/56647 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3275ab408f6a03735a35eaa8025c36df09c9898c Gerrit-Change-Number: 56647 Gerrit-PatchSet: 6 Gerrit-Owner: Sunwei Li <lisunwei(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Sunwei Li <lisunwei(a)huaqin.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Bob Moragues <moragues(a)google.com> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Calculate and configure SF Mask 2
by Subrata Banik (Code Review) 03 Aug '21

03 Aug '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Arthur Heymans, Patrick Rudolph. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Arthur Heymans, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56717 to look at the new patch set (#4). Change subject: soc/intel/common: Calculate and configure SF Mask 2 ...................................................................... soc/intel/common: Calculate and configure SF Mask 2 As per TGL EDS, two ways will be controlled with one bit of SF QoS register hence, this patch introduces SF_MASK_2BITS_PER_WAY Kconfig to allow SoC users to select SF_MASK_2BITS_PER_WAY to follow the EDS recommendation. Calculate SF masks: 1. if CONFIG_SF_MASK_2BITS_PER_WAY: a. data_ways = data_ways / 2 Also, program SF Mask#2 using below logic: 2. Set SF_MASK_2 = (1 << data_ways) - 1 Change-Id: I442bed75f13d26f357cfb32c54c5fe9efa4b474b Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/include/cpu/x86/msr.h M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/car/cache_as_ram.S 3 files changed, 35 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/56717/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/56717 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I442bed75f13d26f357cfb32c54c5fe9efa4b474b Gerrit-Change-Number: 56717 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Calculate and configure SF Mask 2
by Subrata Banik (Code Review) 03 Aug '21

03 Aug '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Arthur Heymans, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56717 ) Change subject: soc/intel/common: Calculate and configure SF Mask 2 ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/common/block/cpu/car/cache_as_ram.S: https://review.coreboot.org/c/coreboot/+/56717/comment/f39431e4_21560835 PS2, Line 522: #if CONFIG(SF_MASK_2BITS_PER_WAY) : mov %edx, %ebx /* back up data_ways in ebx */ : #endif : #if CONFIG(CAR_HAS_SF_MASKS) : /* : * Calculate SF masks: : * if CONFIG_SF_MASK_2BITS_PER_WAY: data_ways = data_ways / 2 : * Program MSR 0x1892 Non-Eviction Mask #2 : * IA32_CR_SF_QOS_MASK_2 = ((1 << data_ways) - 1) : */ : #if CONFIG(SF_MASK_2BITS_PER_WAY) : movl $0x01, %ecx : shr %cl, %ebx : mov %ebx, %ecx : movl $0x01, %ebx : shl %cl, %ebx : subl $0x01, %ebx : #else : mov %esi, %ebx : #endif : mov %ebx, %eax /* restore data_ways in eax */ > yes, i had the exact discussion with Furquan about what if the data_way is 1 then /2 would be proble […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/56717 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I442bed75f13d26f357cfb32c54c5fe9efa4b474b Gerrit-Change-Number: 56717 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 03 Aug 2021 09:09:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subi.banik(a)gmail.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Calculate and configure SF Mask 2
by Subrata Banik (Code Review) 03 Aug '21

03 Aug '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Arthur Heymans, Patrick Rudolph. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Arthur Heymans, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56717 to look at the new patch set (#3). Change subject: soc/intel/common: Calculate and configure SF Mask 2 ...................................................................... soc/intel/common: Calculate and configure SF Mask 2 As per TGL EDS, two ways will be controlled with one bit of SF QoS register hence, this patch introduces SF_MASK_2BITS_PER_WAY Kconfig to allow SoC users to select SF_MASK_2BITS_PER_WAY to follow the EDS recommendation. Calculate SF masks: 1. if CONFIG_SF_MASK_2BITS_PER_WAY: a. data_ways = data_ways / 2 Also, program SF Mask#2 using below logic: 2. Set SF_MASK_2 = (1 << data_ways) - 1 Change-Id: I442bed75f13d26f357cfb32c54c5fe9efa4b474b Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/include/cpu/x86/msr.h M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/car/cache_as_ram.S 3 files changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/56717/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/56717 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I442bed75f13d26f357cfb32c54c5fe9efa4b474b Gerrit-Change-Number: 56717 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Calculate and configure SF Mask 2
by Subrata Banik (Code Review) 03 Aug '21

03 Aug '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Arthur Heymans, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56717 ) Change subject: soc/intel/common: Calculate and configure SF Mask 2 ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/cpu/car/cache_as_ram.S: https://review.coreboot.org/c/coreboot/+/56717/comment/9a610963_c8007de1 PS2, Line 522: #if CONFIG(SF_MASK_2BITS_PER_WAY) : mov %edx, %ebx /* back up data_ways in ebx */ : #endif : #if CONFIG(CAR_HAS_SF_MASKS) : /* : * Calculate SF masks: : * if CONFIG_SF_MASK_2BITS_PER_WAY: data_ways = data_ways / 2 : * Program MSR 0x1892 Non-Eviction Mask #2 : * IA32_CR_SF_QOS_MASK_2 = ((1 << data_ways) - 1) : */ : #if CONFIG(SF_MASK_2BITS_PER_WAY) : movl $0x01, %ecx : shr %cl, %ebx : mov %ebx, %ecx : movl $0x01, %ebx : shl %cl, %ebx : subl $0x01, %ebx : #else : mov %esi, %ebx : #endif : mov %ebx, %eax /* restore data_ways in eax */ > 1) What if %ebx (# of data ways to protect) is 1 on line 534? […] yes, i had the exact discussion with Furquan about what if the data_way is 1 then /2 would be problem but later i have forget that to comprehend, thanks for catching this case. only one thing i would like to change here is that rogram_sf2: // for #1 xorl %edx, %edx mov %eax, %ebx /* Back up %ebx for programming SF1 */ mov $IA32_CR_SF_QOS_MASK_2, %ecx wrmsr -- To view, visit https://review.coreboot.org/c/coreboot/+/56717 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I442bed75f13d26f357cfb32c54c5fe9efa4b474b Gerrit-Change-Number: 56717 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 03 Aug 2021 09:03:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/primus: Remove DPTF fan control
by Scott Chao (Code Review) 03 Aug '21

03 Aug '21

Scott Chao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56768 ) Change subject: mb/google/brya/variants/primus: Remove DPTF fan control ...................................................................... mb/google/brya/variants/primus: Remove DPTF fan control BUG=b:195378817 BRANCH=none TEST=Check fan is able to control by EC Signed-off-by: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Change-Id: I84c020e470194072bb796f75f8a1304832504469 --- M src/mainboard/google/brya/variants/gimble/overridetree.cb 1 file changed, 0 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/56768/1 diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb index 15275bd..a47d143 100644 --- a/src/mainboard/google/brya/variants/gimble/overridetree.cb +++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb @@ -78,22 +78,6 @@ [2] = { 16, 1000 }, [3] = { 8, 500 } }" - ## Fan Performance Control (Percent, Speed, Noise, Power) - register "controls.fan_perf" = "{ - [0] = { 90, 6700, 220, 2200, }, - [1] = { 80, 5800, 180, 1800, }, - [2] = { 70, 5000, 145, 1450, }, - [3] = { 60, 4900, 115, 1150, }, - [4] = { 50, 3838, 90, 900, }, - [5] = { 40, 2904, 55, 550, }, - [6] = { 30, 2337, 30, 300, }, - [7] = { 20, 1608, 15, 150, }, - [8] = { 10, 800, 10, 100, }, - [9] = { 0, 0, 0, 50, } - }" - ## Fan options - register "options.fan.fine_grained_control" = "1" - register "options.fan.step_size" = "2" device generic 0 on end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/56768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84c020e470194072bb796f75f8a1304832504469 Gerrit-Change-Number: 56768 Gerrit-PatchSet: 1 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/apollolake: add 4Gb and 6Gb dram density
by Jamie Chen (Code Review) 03 Aug '21

03 Aug '21

Attention is currently required from: Jamie Chen, Furquan Shaikh, Kane Chen, Andrey Petrov, Patrick Rudolph. Hello build bot (Jenkins), Jamie Chen, Furquan Shaikh, Kane Chen, Andrey Petrov, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55153 to look at the new patch set (#5). Change subject: soc/intel/apollolake: add 4Gb and 6Gb dram density ...................................................................... soc/intel/apollolake: add 4Gb and 6Gb dram density This patch adds 4gb and 6gb dram density support to APL and GLK. Because ch0_density = 0 is not appropriate to determine whether the channel is disabled or not, so ch0_enable and ch1_enable are provided to turn on/off channel respectively. BUG=b:178665760 BRANCH=NONE TEST=build fw and flash to the dut, the dut can boot up successfully. Change-Id: Ic0d5d14f26a30da7a9caf4ef43d7fac88a4d2bf1 Signed-off-by: Jamie Chen <jamie.chen(a)intel.com> --- M src/mainboard/google/octopus/variants/baseboard/memory.c M src/mainboard/google/reef/variants/baseboard/memory.c M src/mainboard/google/reef/variants/pyro/memory.c M src/mainboard/intel/glkrvp/variants/baseboard/memory.c M src/mainboard/up/squared/romstage.c M src/soc/intel/apollolake/include/soc/meminit.h M src/soc/intel/apollolake/meminit.c 7 files changed, 94 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/55153/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/55153 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0d5d14f26a30da7a9caf4ef43d7fac88a4d2bf1 Gerrit-Change-Number: 55153 Gerrit-PatchSet: 5 Gerrit-Owner: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/variant/taeko: Update memory settings.
by Joey Peng (Code Review) 03 Aug '21

03 Aug '21

Joey Peng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56766 ) Change subject: mb/google/brya/variant/taeko: Update memory settings. ...................................................................... mb/google/brya/variant/taeko: Update memory settings. Based on the Taeko's schematic, generate memory settings. BUG=b:161089195 TEST=FW_NAME=taeko emerge-brya coreboot chromeos-bootimage Signed-off-by: joey.peng <joey.peng(a)lcfc.corp-partner.google.com> Change-Id: I4e23c28aaf20d9e52b43033b4e41c751e26872bf --- M src/mainboard/google/brya/variants/taeko/Makefile.inc A src/mainboard/google/brya/variants/taeko/memory.c M src/mainboard/google/brya/variants/taeko/memory/Makefile.inc M src/mainboard/google/brya/variants/taeko/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/taeko/memory/mem_parts_used.txt 5 files changed, 113 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/56766/1 diff --git a/src/mainboard/google/brya/variants/taeko/Makefile.inc b/src/mainboard/google/brya/variants/taeko/Makefile.inc index 9fb63f5..1d38b77 100644 --- a/src/mainboard/google/brya/variants/taeko/Makefile.inc +++ b/src/mainboard/google/brya/variants/taeko/Makefile.inc @@ -1,3 +1,5 @@ bootblock-y += gpio.c +romstage-y += memory.c + ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/taeko/memory.c b/src/mainboard/google/brya/variants/taeko/memory.c new file mode 100644 index 0000000..2a0b6ac --- /dev/null +++ b/src/mainboard/google/brya/variants/taeko/memory.c @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <gpio.h> + +static const struct mb_cfg baseboard_memcfg = { + .type = MEM_TYPE_LP4X, + + .rcomp = { + /* Baseboard uses only 100ohm Rcomp resistors */ + .resistor = 100, + + /* Baseboard Rcomp target values */ + .targets = {40, 30, 30, 30, 30}, + }, + + /* DQ byte map */ + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 0, 1, 2, 3, 4, 5, 6, 7, }, + .dq1 = { 12, 13, 14, 15, 11, 10, 9, 8, }, + }, + .ddr1 = { + .dq0 = { 7, 2, 6, 3, 5, 1, 4, 0, }, + .dq1 = { 10, 8, 9, 11, 15, 12, 14, 13, }, + }, + .ddr2 = { + .dq0 = { 3, 2, 1, 0, 4, 5, 6, 7, }, + .dq1 = { 12, 13, 14, 15, 11, 10, 9, 8, }, + }, + .ddr3 = { + .dq0 = { 7, 0, 1, 6, 5, 4, 2, 3, }, + .dq1 = { 15, 14, 8, 9, 10, 12, 11, 13, }, + }, + .ddr4 = { + .dq0 = { 3, 2, 1, 0, 4, 5, 6, 7, }, + .dq1 = { 12, 13, 14, 15, 11, 10, 9, 8, }, + }, + .ddr5 = { + .dq0 = { 3, 4, 2, 5, 0, 6, 1, 7, }, + .dq1 = { 13, 12, 11, 10, 14, 15, 9, 8, }, + }, + .ddr6 = { + .dq0 = { 3, 2, 1, 0, 7, 4, 5, 6, }, + .dq1 = { 15, 14, 13, 12, 8, 9, 10, 11, }, + }, + .ddr7 = { + .dq0 = { 3, 4, 2, 5, 1, 0, 7, 6, }, + .dq1 = { 15, 14, 9, 8, 12, 10, 11, 13, }, + }, + }, + + /* DQS CPU<>DRAM map */ + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, + }, + + .ect = 1, /* Enable Early Command Training */ +}; + +const struct mb_cfg *__weak variant_memory_params(void) +{ + return &baseboard_memcfg; +} + +int __weak variant_memory_sku(void) +{ + /* + * Memory configuration board straps + * GPIO_MEM_CONFIG_0 GPP_E11 + * GPIO_MEM_CONFIG_1 GPP_E2 + * GPIO_MEM_CONFIG_2 GPP_E1 + * GPIO_MEM_CONFIG_3 GPP_E12 + */ + gpio_t spd_gpios[] = { + GPP_E11, + GPP_E2, + GPP_E1, + GPP_E12, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + +bool __weak variant_is_half_populated(void) +{ + /* GPIO_MEM_CH_SEL GPP_E13 */ + return gpio_get(GPP_E13); +} diff --git a/src/mainboard/google/brya/variants/taeko/memory/Makefile.inc b/src/mainboard/google/brya/variants/taeko/memory/Makefile.inc index b0ca222..3133ab5 100644 --- a/src/mainboard/google/brya/variants/taeko/memory/Makefile.inc +++ b/src/mainboard/google/brya/variants/taeko/memory/Makefile.inc @@ -1,5 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-or-later ## This is an auto-generated file. Do not edit!! -## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. -SPD_SOURCES = placeholder.spd.hex +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, H9HCNNNBKMMLXR-NEE, MT53E512M32D1NP-046 WT:B, K4U6E3S4AB-MGCL, H54G46CYRBX267 diff --git a/src/mainboard/google/brya/variants/taeko/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/taeko/memory/dram_id.generated.txt index fa24790..12a2bd5 100644 --- a/src/mainboard/google/brya/variants/taeko/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/taeko/memory/dram_id.generated.txt @@ -1 +1,7 @@ DRAM Part Name ID to assign +MT53E512M32D2NP-046 WT:E 0 (0000) +K4U6E3S4AA-MGCR 0 (0000) +H9HCNNNBKMMLXR-NEE 0 (0000) +MT53E512M32D1NP-046 WT:B 0 (0000) +K4U6E3S4AB-MGCL 0 (0000) +H54G46CYRBX267 0 (0000) diff --git a/src/mainboard/google/brya/variants/taeko/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/taeko/memory/mem_parts_used.txt index 9cff262..dd80fc8 100644 --- a/src/mainboard/google/brya/variants/taeko/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/taeko/memory/mem_parts_used.txt @@ -1,11 +1,6 @@ -# This is a CSV file containing a list of memory parts used by this variant. -# One part per line with an optional fixed ID in column 2. -# Only include a fixed ID if it is required for legacy reasons! -# Generated IDs are dependent on the order of parts in this file, -# so new parts must always be added at the end of the file! -# -# Generate an updated Makefile.inc and dram_id.generated.txt by running the -# gen_part_id tool from util/spd_tools/lp4x. -# See util/spd_tools/lp4x/README.md for more details and instructions. - -# Part Name +MT53E512M32D2NP-046 WT:E +K4U6E3S4AA-MGCR +H9HCNNNBKMMLXR-NEE +MT53E512M32D1NP-046 WT:B +K4U6E3S4AB-MGCL +H54G46CYRBX267 -- To view, visit https://review.coreboot.org/c/coreboot/+/56766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e23c28aaf20d9e52b43033b4e41c751e26872bf Gerrit-Change-Number: 56766 Gerrit-PatchSet: 1 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya: Create felwinter variant
by EricR Lai (Code Review) 03 Aug '21

03 Aug '21

Attention is currently required from: Ian Feng, Tim Wawrzynczak. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56765 ) Change subject: mb/google/brya: Create felwinter variant ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56765 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff2b9daec40995a013f9fe0dd76ad667d1807d1b Gerrit-Change-Number: 56765 Gerrit-PatchSet: 1 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 03 Aug 2021 07:27:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Create felwinter variant
by Ian Feng (Code Review) 03 Aug '21

03 Aug '21

Ian Feng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56765 ) Change subject: mb/google/brya: Create felwinter variant ...................................................................... mb/google/brya: Create felwinter variant Create the felwinter variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:194431541 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_FELWINTER Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Change-Id: Iff2b9daec40995a013f9fe0dd76ad667d1807d1b --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name A src/mainboard/google/brya/variants/felwinter/include/variant/ec.h A src/mainboard/google/brya/variants/felwinter/include/variant/gpio.h A src/mainboard/google/brya/variants/felwinter/memory/Makefile.inc A src/mainboard/google/brya/variants/felwinter/memory/dram_id.generated.txt A src/mainboard/google/brya/variants/felwinter/memory/mem_parts_used.txt A src/mainboard/google/brya/variants/felwinter/overridetree.cb 8 files changed, 45 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/56765/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index d1b6f24..3637959 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -77,6 +77,7 @@ default "Redrix" if BOARD_GOOGLE_REDRIX default "Kano" if BOARD_GOOGLE_KANO default "Taeko" if BOARD_GOOGLE_TAEKO + default "Felwinter" if BOARD_GOOGLE_FELWINTER config VARIANT_DIR default "brya0" if BOARD_GOOGLE_BRYA0 @@ -85,6 +86,7 @@ default "redrix" if BOARD_GOOGLE_REDRIX default "kano" if BOARD_GOOGLE_KANO default "taeko" if BOARD_GOOGLE_TAEKO + default "felwinter" if BOARD_GOOGLE_FELWINTER config DIMM_SPD_SIZE int diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 657c411..f11a998 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -30,3 +30,7 @@ config BOARD_GOOGLE_TAEKO bool "-> Taeko" select BOARD_GOOGLE_BASEBOARD_BRYA + +config BOARD_GOOGLE_FELWINTER + bool "-> Felwinter" + select BOARD_GOOGLE_BASEBOARD_BRYA diff --git a/src/mainboard/google/brya/variants/felwinter/include/variant/ec.h b/src/mainboard/google/brya/variants/felwinter/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/brya/variants/felwinter/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/brya/variants/felwinter/include/variant/gpio.h b/src/mainboard/google/brya/variants/felwinter/include/variant/gpio.h new file mode 100644 index 0000000..c4fe342 --- /dev/null +++ b/src/mainboard/google/brya/variants/felwinter/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/brya/variants/felwinter/memory/Makefile.inc b/src/mainboard/google/brya/variants/felwinter/memory/Makefile.inc new file mode 100644 index 0000000..b0ca222 --- /dev/null +++ b/src/mainboard/google/brya/variants/felwinter/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! +## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder.spd.hex diff --git a/src/mainboard/google/brya/variants/felwinter/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/felwinter/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/brya/variants/felwinter/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/brya/variants/felwinter/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/felwinter/memory/mem_parts_used.txt new file mode 100644 index 0000000..9cff262 --- /dev/null +++ b/src/mainboard/google/brya/variants/felwinter/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/lp4x. +# See util/spd_tools/lp4x/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb new file mode 100644 index 0000000..4f2c04a --- /dev/null +++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/alderlake + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/56765 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff2b9daec40995a013f9fe0dd76ad667d1807d1b Gerrit-Change-Number: 56765 Gerrit-PatchSet: 1 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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