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Hello build bot (Jenkins), Julius Werner, Jan Dabros,
I'd like you to reexamine a change. Please visit
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Change subject: tests/Makefile.inc: Add function wrapping mechanism
......................................................................
tests/Makefile.inc: Add function wrapping mechanism
This patch extends mocks functionality to allowing wrapping of mocked
functions. Original function name will be prefixed with `__real_`.
Example:
- Mocked function: cbfs_lookup()
- New function name: __real_cbfs_lookup()
- Mock name: cbfs_lookup()
Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com>
Change-Id: I7cd0d66a17029955cbf75c8b155a7ebb7f5513aa
---
M tests/Makefile.inc
1 file changed, 11 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/56719/4
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Change subject: soc/intel/common: Calculate and configure SF Mask 2
......................................................................
Patch Set 5:
(1 comment)
File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/56717/comment/16cc56e8_7ec42513
PS5, Line 543: wrmsr
> let me take a look, did u see any thing obvious broken in the code
I just ran this code in gdb and don't see any problem in programming. I will test again tomorrow, my board is not available on remote currently, sorry for delay.
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Change subject: Revert "src/soc/intel/cannonlake: Update C-state latency control limits"
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> reference to previous IRTL values(14nm)-
> https://github.com/coreboot/coreboot/blob/master/src/soc/intel/skylake/cpu.c
>
> Why are we modfying cannonlake values ?
soc/cannonlake *is* Coffee Lake, it just wasn't renamed. So, this commit/revert actually changes Coffee Lake values, not Cannon Lake values.
> The cannon lake support was dropped. If you are using Coffe lake, then you might have to use board- skylake values becaue its based out of 14nm.
When CFL matches SKL, then this commit/revert is correct.
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Change subject: soc/intel/common: Calculate and configure SF Mask 2
......................................................................
Patch Set 5:
(1 comment)
File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/56717/comment/cb970128_e5e03665
PS5, Line 543: wrmsr
> also my brya is crashing on this line when I cherry-pick this through CB:48345
let me take a look, did u see any thing obvious broken in the code
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Change subject: Revert "src/soc/intel/cannonlake: Update C-state latency control limits"
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56662/comment/a20c6d0a_3f6ebcea
PS1, Line 14:
> S0ix is enabled by default on all recent chromeOs platfroms. […]
Sure :-) I wanted to know if it still works with this change. Also, this should be added to the commit msg
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Hello Lance Zhao, build bot (Jenkins), Dmitry Torokhov, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56763
to look at the new patch set (#3).
Change subject: arch/x86/acpi: rename KEY_KBDILLUMTOGGLE to KEY_KBD_BKLIGHT_TOGGLE
......................................................................
arch/x86/acpi: rename KEY_KBDILLUMTOGGLE to KEY_KBD_BKLIGHT_TOGGLE
Also change scan code from e02b to e01e. This is trying to fill the gaps in the standard table. The advise from Googler is using e01e for the keyboard backlight toggle key.
BUG=b:194146863
BRANCH=none
TEST=check on evtest
Signed-off-by: Scott Chao <scott_chao(a)wistron.corp-partner.google.com>
Change-Id: I402192ff354f30da35aec43202df9f1407911d34
---
M src/acpi/acpigen_ps2_keybd.c
M src/include/acpi/acpigen_ps2_keybd.h
2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/56763/3
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Change subject: soc/intel/common: Calculate and configure SF Mask 2
......................................................................
Patch Set 5:
(1 comment)
File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/56717/comment/2a079797_5645c3c8
PS5, Line 543: wrmsr
also my brya is crashing on this line when I cherry-pick this through CB:48345
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Change subject: soc/intel/common: Calculate and configure SF Mask 2
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
Might also consider adding a new POST code
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Change subject: soc/intel/common: Calculate and configure SF Mask 1
......................................................................
Patch Set 18:
(1 comment)
File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/51374/comment/9ed93ba5_6df3c002
PS18, Line 555: cmp $0x01, %eax /* Skip Step 2 if SFWayCnt = 1 */
: jz program_sf1
> This should be an effectively impossible situation though, shouldn't it? 1 SF way would effectively […]
yes, i agree, and i just put this to have a discussion. 😊
Do we agree, we don't need to worry about this case, isn't it ?
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Change subject: soc/intel/common: Calculate and configure SF Mask 1
......................................................................
Patch Set 18: Code-Review+1
(1 comment)
File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/51374/comment/9a437533_53e6c548
PS18, Line 555: cmp $0x01, %eax /* Skip Step 2 if SFWayCnt = 1 */
: jz program_sf1
This should be an effectively impossible situation though, shouldn't it? 1 SF way would effectively mean 1 or 2 ways in the LLC total, which would be very odd.
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