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April 2021

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Change in coreboot[master]: soc/amd/cezanne: Add support to perform early EC sync
by Karthik Ramasubramanian (Code Review) March 31, 2021

March 31, 2021

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52008 ) Change subject: soc/amd/cezanne: Add support to perform early EC sync ...................................................................... soc/amd/cezanne: Add support to perform early EC sync Ideally we would like to perform EC Software Sync in payload. But with the hardware requirement (EC_IN_RW) and firmware requirement (TPM command to get EC execution environment) not met yet, adding the support to perform early EC Software sync. With EFS2 enabled, this will also help cr50 to set the boot mode as NORMAL instead of NO_BOOT. BUG=None TEST=Build and Boot to OS in Guybrush. Ensure that the EC software sync is successfully complete. CBFS: Found 'ecrw.hash' @0x50400 size 0x20 in mcache @0x020171ec VB2:check_ec_hash() Hexp RW(active): 2dd8dbb78d0c626358a626037973a3d81982f88f3f38e7f759039bf84e05ccc6 VB2:check_ec_hash() Hmir: 2dd8dbb78d0c626358a626037973a3d81982f88f3f38e7f759039bf84e05ccc6 <snip> VB2:check_ec_hash() Heff RW(active): 2dd8dbb78d0c626358a626037973a3d81982f88f3f38e7f759039bf84e05ccc6 VB2:sync_ec() select_rw=RW(active) Change-Id: I820e651c6b22a833fef6f17a4ceb5a8cfb6f1616 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/amd/cezanne/romstage.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/52008/1 diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c index 643b067..57c1961 100644 --- a/src/soc/amd/cezanne/romstage.c +++ b/src/soc/amd/cezanne/romstage.c @@ -8,12 +8,16 @@ #include <console/console.h> #include <fsp/api.h> #include <program_loading.h> +#include <security/vboot/vboot_common.h> asmlinkage void car_stage_entry(void) { post_code(0x40); console_init(); + if (CONFIG(VBOOT_EARLY_EC_SYNC)) + vboot_sync_ec(); + post_code(0x41); fsp_memory_init(acpi_is_wakeup_s3()); -- To view, visit https://review.coreboot.org/c/coreboot/+/52008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I820e651c6b22a833fef6f17a4ceb5a8cfb6f1616 Gerrit-Change-Number: 52008 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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