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Change in coreboot[master]: mb/intel/d510: Fix spaces to tabs
by Arthur Heymans (Code Review) 01 Mar '21

01 Mar '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51149 ) Change subject: mb/intel/d510: Fix spaces to tabs ...................................................................... mb/intel/d510: Fix spaces to tabs This is a cosmetic change. Make the formatting consistent with the rest of the tree. Change-Id: Ic90e5584938592f1c2ab41edfcc773702822070d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/intel/d510mo/devicetree.cb 1 file changed, 94 insertions(+), 94 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/51149/1 diff --git a/src/mainboard/intel/d510mo/devicetree.cb b/src/mainboard/intel/d510mo/devicetree.cb index 7486f7e..22e67e7 100644 --- a/src/mainboard/intel/d510mo/devicetree.cb +++ b/src/mainboard/intel/d510mo/devicetree.cb @@ -1,100 +1,100 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/pineview # Northbridge - register "gfx.use_spread_spectrum_clock" = "0" - register "use_crt" = "1" - register "use_lvds" = "0" + register "gfx.use_spread_spectrum_clock" = "0" + register "use_crt" = "1" + register "use_lvds" = "0" - device cpu_cluster 0 on # APIC cluster - chip cpu/intel/socket_FCBGA559 # CPU - device lapic 0 on end # APIC - end - end - device domain 0 on # PCI domain - device pci 0.0 on end # Host Bridge - device pci 1.0 off end # PEG - device pci 2.0 on end # Integrated graphics controller - device pci 2.1 on end # Integrated graphics controller 2 - chip southbridge/intel/i82801gx # Southbridge - register "pirqa_routing" = "0x0b" - register "pirqb_routing" = "0x0b" - register "pirqc_routing" = "0x0b" - register "pirqd_routing" = "0x0b" - register "pirqe_routing" = "0x0b" - register "pirqf_routing" = "0x0b" - register "pirqg_routing" = "0x0b" - register "pirqh_routing" = "0x0b" - register "sata_ports_implemented" = "0x3" - register "gpe0_en" = "0x20000040" + device cpu_cluster 0 on # APIC cluster + chip cpu/intel/socket_FCBGA559 # CPU + device lapic 0 on end # APIC + end + end + device domain 0 on # PCI domain + device pci 0.0 on end # Host Bridge + device pci 1.0 off end # PEG + device pci 2.0 on end # Integrated graphics controller + device pci 2.1 on end # Integrated graphics controller 2 + chip southbridge/intel/i82801gx # Southbridge + register "pirqa_routing" = "0x0b" + register "pirqb_routing" = "0x0b" + register "pirqc_routing" = "0x0b" + register "pirqd_routing" = "0x0b" + register "pirqe_routing" = "0x0b" + register "pirqf_routing" = "0x0b" + register "pirqg_routing" = "0x0b" + register "pirqh_routing" = "0x0b" + register "sata_ports_implemented" = "0x3" + register "gpe0_en" = "0x20000040" - device pci 1b.0 on end # Audio - device pci 1c.0 on # PCIe 1 - device pci 0.0 on end # NIC - end - device pci 1c.1 on end # PCIe 2 - device pci 1c.2 on end # PCIe 3 - device pci 1c.3 on end # PCIe 4 - device pci 1d.0 on end # USB - device pci 1d.1 on end # USB - device pci 1d.2 on end # USB - device pci 1d.3 on end # USB - device pci 1d.7 on end # USB - device pci 1e.0 on end # PCI bridge - #device pci 1e.2 off end # AC'97 Audio (not on nm10?) - #device pci 1e.3 off end # AC'97 Modem (not on nm10?) - device pci 1f.0 on # ISA bridge - chip superio/winbond/w83627thg # Super I/O - device pnp 4e.0 off end # Floppy - device pnp 4e.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 4 - end - device pnp 4e.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.3 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - irq 0xf1 = 0 - end - device pnp 4e.5 on # PS/2 keyboard / mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - irq 0xf0 = 0x80 - end - device pnp 4e.6 off end - device pnp 4e.7 off end - device pnp 4e.8 off end - device pnp 4e.9 off end - device pnp 4e.a off end # ACPI - device pnp 4e.b on # HWM - io 0x60 = 0x290 - irq 0x70 = 0 - end - end - end - device pci 1f.1 off end # PATA - device pci 1f.2 on end # SATA - device pci 1f.3 on # SMbus - chip drivers/i2c/ck505 # ICS9EPRS525 - register "mask" = "{ 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, - 0xff }" - register "regs" = "{ 0x61, 0xd9, 0xfe, 0xff, - 0xff, 0x00, 0x00, 0x01, - 0x03, 0x25, 0x83, 0x17, - 0x0d }" - device i2c 69 on end - end - end - device pci 1f.4 off end - device pci 1f.5 off end - device pci 1f.6 off end - end - end + device pci 1b.0 on end # Audio + device pci 1c.0 on # PCIe 1 + device pci 0.0 on end # NIC + end + device pci 1c.1 on end # PCIe 2 + device pci 1c.2 on end # PCIe 3 + device pci 1c.3 on end # PCIe 4 + device pci 1d.0 on end # USB + device pci 1d.1 on end # USB + device pci 1d.2 on end # USB + device pci 1d.3 on end # USB + device pci 1d.7 on end # USB + device pci 1e.0 on end # PCI bridge + #device pci 1e.2 off end # AC'97 Audio (not on nm10?) + #device pci 1e.3 off end # AC'97 Modem (not on nm10?) + device pci 1f.0 on # ISA bridge + chip superio/winbond/w83627thg # Super I/O + device pnp 4e.0 off end # Floppy + device pnp 4e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 4 + end + device pnp 4e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + irq 0xf1 = 0 + end + device pnp 4e.5 on # PS/2 keyboard / mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + irq 0xf0 = 0x80 + end + device pnp 4e.6 off end + device pnp 4e.7 off end + device pnp 4e.8 off end + device pnp 4e.9 off end + device pnp 4e.a off end # ACPI + device pnp 4e.b on # HWM + io 0x60 = 0x290 + irq 0x70 = 0 + end + end + end + device pci 1f.1 off end # PATA + device pci 1f.2 on end # SATA + device pci 1f.3 on # SMbus + chip drivers/i2c/ck505 # ICS9EPRS525 + register "mask" = "{ 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, + 0xff }" + register "regs" = "{ 0x61, 0xd9, 0xfe, 0xff, + 0xff, 0x00, 0x00, 0x01, + 0x03, 0x25, 0x83, 0x17, + 0x0d }" + device i2c 69 on end + end + end + device pci 1f.4 off end + device pci 1f.5 off end + device pci 1f.6 off end + end + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/51149 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic90e5584938592f1c2ab41edfcc773702822070d Gerrit-Change-Number: 51149 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/gigabyte: Add GA-D510UD
by Arthur Heymans (Code Review) 01 Mar '21

01 Mar '21

Attention is currently required from: Christian Walter, Angel Pons. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40465 ) Change subject: mb/gigabyte: Add GA-D510UD ...................................................................... Patch Set 7: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/40465/comment/311b30ea_2caa877f PS6, Line 11: M > I remember that the raminit is somewhat picky (when there are 2 DIMMs). LGTM File src/mainboard/gigabyte/ga-d510ud/devicetree.cb: https://review.coreboot.org/c/coreboot/+/40465/comment/cd70863d_f846e101 PS7, Line 13: device pci 0.0 on end # Host Bridge > Pineview does not have PEG... Oh I got confused by a devicetree. -- To view, visit https://review.coreboot.org/c/coreboot/+/40465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2126c7d31e0d8a8f80df69fdcdcd202b87f219a4 Gerrit-Change-Number: 40465 Gerrit-PatchSet: 7 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 01 Mar 2021 17:23:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Christian Walter <christian.walter(a)9elements.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Move `gpi_clear_int_cfg()` call
by Angel Pons (Code Review) 01 Mar '21

01 Mar '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51148 ) Change subject: soc/intel/cannonlake: Move `gpi_clear_int_cfg()` call ...................................................................... soc/intel/cannonlake: Move `gpi_clear_int_cfg()` call To allow unifying bootblock.c in follow-ups, move a function call. Change-Id: I0f40ee7fd47f7f9f582f314dfcd1b4b93b1db791 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/cannonlake/bootblock/bootblock.c M src/soc/intel/cannonlake/bootblock/pch.c 2 files changed, 7 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/51148/1 diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c index dfa0bd0..1354c43 100644 --- a/src/soc/intel/cannonlake/bootblock/bootblock.c +++ b/src/soc/intel/cannonlake/bootblock/bootblock.c @@ -61,11 +61,6 @@ void bootblock_soc_init(void) { - /* - * Clear the GPI interrupt status and enable registers. These - * registers do not get reset to default state when booting from S5. - */ - gpi_clear_int_cfg(); report_platform_info(); bootblock_pch_init(); diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index 51f8fb5..a4f47c9 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -6,6 +6,7 @@ #include <device/pci_ops.h> #include <intelblocks/dmi.h> #include <intelblocks/fast_spi.h> +#include <intelblocks/gpio.h> #include <intelblocks/gspi.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/p2sb.h> @@ -132,6 +133,12 @@ void bootblock_pch_init(void) { /* + * Clear the GPI interrupt status and enable registers. These + * registers do not get reset to default state when booting from S5. + */ + gpi_clear_int_cfg(); + + /* * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, * GPE0_STS, GPE0_EN registers. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/51148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f40ee7fd47f7f9f582f314dfcd1b4b93b1db791 Gerrit-Change-Number: 51148 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [DO NOT SUBMIT] 3rdparty/libgfxinit: Update submodule pointer
by Angel Pons (Code Review) 01 Mar '21

01 Mar '21

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51147 to look at the new patch set (#2). Change subject: [DO NOT SUBMIT] 3rdparty/libgfxinit: Update submodule pointer ...................................................................... [DO NOT SUBMIT] 3rdparty/libgfxinit: Update submodule pointer Change-Id: I35cefa2aa8107b7841d7cf7a7bb61d4b591d14ae Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M 3rdparty/libgfxinit 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/51147/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/51147 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35cefa2aa8107b7841d7cf7a7bb61d4b591d14ae Gerrit-Change-Number: 51147 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/chromeos: Use the same inventory each time and verify checksums
by Leah Rowe (Code Review) 01 Mar '21

01 Mar '21

Attention is currently required from: Paul Menzel, Arthur Heymans. Leah Rowe has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51144 ) Change subject: util/chromeos: Use the same inventory each time and verify checksums ...................................................................... Patch Set 5: (1 comment) Patchset: PS4: > Try to do one change per commit. In what way do you think I should split up this commit? -- To view, visit https://review.coreboot.org/c/coreboot/+/51144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0166518d252a36d8f9a9c17d375fbdd9e3116f6 Gerrit-Change-Number: 51144 Gerrit-PatchSet: 5 Gerrit-Owner: Leah Rowe <leahleahrowerowe(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 01 Mar 2021 17:03:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Implement soc_get_north_xhci_usb_info
by Tim Wawrzynczak (Code Review) 01 Mar '21

01 Mar '21

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47414 ) Change subject: soc/intel/alderlake: Implement soc_get_north_xhci_usb_info ...................................................................... soc/intel/alderlake: Implement soc_get_north_xhci_usb_info Alder Lake-P supports 1 USB2 port and 4 USB3 ports on the TCSS XHCI device. Change-Id: I57e721dc6fb98aca19fa4c84648c33735aa8f2f0 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/Makefile.inc A src/soc/intel/alderlake/north_xhci.c 2 files changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/47414/1 diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index f1d7b65..f21ad18 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -37,6 +37,7 @@ ramstage-y += gpio.c ramstage-y += lockdown.c ramstage-y += me.c +ramstage-y += north_xhci.c ramstage-y += p2sb.c ramstage-y += pmc.c ramstage-y += reset.c diff --git a/src/soc/intel/alderlake/north_xhci.c b/src/soc/intel/alderlake/north_xhci.c new file mode 100644 index 0000000..5ca6430 --- /dev/null +++ b/src/soc/intel/alderlake/north_xhci.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <intelblocks/north_xhci.h> + +#define USB2_PORT_STATUS_REG 0x480 +#define USB3_PORT_STATUS_REG 0x490 +#define USB2_PORT_NUM 1 +#define USB3_PORT_NUM 4 + +static const struct north_xhci_usb_info usb_info = { + .usb2_port_status_reg = USB2_PORT_STATUS_REG, + .num_usb2_ports = USB2_PORT_NUM, + .usb3_port_status_reg = USB3_PORT_STATUS_REG, + .num_usb3_ports = USB3_PORT_NUM, +}; + +const struct north_xhci_usb_info *soc_get_north_xhci_usb_info(void) +{ + return &usb_info; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/47414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I57e721dc6fb98aca19fa4c84648c33735aa8f2f0 Gerrit-Change-Number: 47414 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne: Fill out pci devices in chipset.cb
by Mathew King (Code Review) 01 Mar '21

01 Mar '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Angel Pons, Felix Held. Mathew King has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51045 ) Change subject: soc/amd/cezanne: Fill out pci devices in chipset.cb ...................................................................... Patch Set 9: (1 comment) Patchset: PS9: > hm, i wonder if we should call the sata devices sata_0 and sata_1, since those are the two sata cont […] The PPR shows Function 0: SATA AHCI Mode with MS Driver support or SATA AHCI Mode with AMD driver support Function 1: SATA Controller; SATA Raid/AHCI Mode or SATA Controller: SATA Raid AHCI Mode for second vendor -- To view, visit https://review.coreboot.org/c/coreboot/+/51045 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecc75afd7a914651ca15b811163d3559bf73ac9b Gerrit-Change-Number: 51045 Gerrit-PatchSet: 9 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 01 Mar 2021 16:51:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: Backport SMRR locking support
by Angel Pons (Code Review) 01 Mar '21

01 Mar '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner, Patrick Rudolph. Angel Pons has removed a vote from this change. ( https://review.coreboot.org/c/coreboot/+/50936 ) Change subject: soc/intel: Backport SMRR locking support ...................................................................... Removed Verified+1 by build bot (Jenkins) <no-reply(a)coreboot.org> -- To view, visit https://review.coreboot.org/c/coreboot/+/50936 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icbee0985b04418e83cbf41b81f00934f5a663e30 Gerrit-Change-Number: 50936 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: deleteVote

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Change in coreboot[master]: soc/intel: Backport SMRR locking support
by Angel Pons (Code Review) 01 Mar '21

01 Mar '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50936 ) Change subject: soc/intel: Backport SMRR locking support ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/50936/comment/dcb0d86d_1d5a2117 PS2, Line 13: follow-up will deduplicate smmrelocate.c files into common CPU code. > Elkhart Lake is neither older nor big-core and seems to support the […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/50936 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icbee0985b04418e83cbf41b81f00934f5a663e30 Gerrit-Change-Number: 50936 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 01 Mar 2021 16:44:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: Backport SMRR locking support
by Angel Pons (Code Review) 01 Mar '21

01 Mar '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner, Patrick Rudolph. Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Arthur Heymans, Michael Niewöhner, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50936 to look at the new patch set (#3). Change subject: soc/intel: Backport SMRR locking support ...................................................................... soc/intel: Backport SMRR locking support Backport commit 0cded1f116 (soc/intel/tigerlake: Add SMRR Locking support) to other client platforms. The SMRR MSRs are core-scoped on Skylake and Ice Lake, at least. Older platforms do not support SMRR locking, but now there's seven copies of the same file in the tree. A follow-up will deduplicate smmrelocate.c files into common CPU code. I cannot test Jasper Lake nor Elkhart Lake, but they should still work. As per documentation I do not have access to, Elkhart Lake seems to support SMRR locking. However, Jasper Lake documentation is unclear. Tested on Purism Librem Mini v1 (WHL-U i7-8565U), still boots and SMRR MSRs have the same value on all cores/threads (i7-8565U supports HT). Change-Id: Icbee0985b04418e83cbf41b81f00934f5a663e30 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/cannonlake/smmrelocate.c M src/soc/intel/elkhartlake/smmrelocate.c M src/soc/intel/icelake/smmrelocate.c M src/soc/intel/jasperlake/smmrelocate.c M src/soc/intel/skylake/smmrelocate.c 5 files changed, 85 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/50936/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/50936 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icbee0985b04418e83cbf41b81f00934f5a663e30 Gerrit-Change-Number: 50936 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit March 2021