coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

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6394 discussions

Change in coreboot[master]: soc/intel/alderlake: enable gpio locking
by Tim Wawrzynczak (Code Review) 01 Nov '21

01 Nov '21

Attention is currently required from: Furquan Shaikh, Nick Vaccaro, Patrick Rudolph, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58352 ) Change subject: soc/intel/alderlake: enable gpio locking ...................................................................... Patch Set 4: Code-Review+1 (1 comment) File src/soc/intel/alderlake/gpio.c: https://review.coreboot.org/c/coreboot/+/58352/comment/7f2c2152_612f3dc0 PS4, Line 278: { GPP_E9, GPIO_LOCK_CONFIG }, /* ISH_GP4 NF2 */ another pad to consider (for a different reason) is GPP_H3. Its NF1 is `SX_EXIT_HOLDOFF#` which, when selected, can be used to delay exiting from Sx states (depending on SLP_A#). This can be misused to prevent a device from exiting S4 or S5 (see the PCH EDS vol 1 for details) -- To view, visit https://review.coreboot.org/c/coreboot/+/58352 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I457bab39f945ab31a89542c6498a73af70cbf9ee Gerrit-Change-Number: 58352 Gerrit-PatchSet: 4 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 01 Nov 2021 22:57:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: tests/Makefile: Remove ./ prefix when running tests
by Raul Rangel (Code Review) 01 Nov '21

01 Nov '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58806 ) Change subject: tests/Makefile: Remove ./ prefix when running tests ...................................................................... tests/Makefile: Remove ./ prefix when running tests If ran with obj=/absolute path, then tests were failing to execute because the recipe tried running `.//absolutepath/...run`. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I9c3638b1af7531dbe8e956dcbe168250a235ead4 --- M tests/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/58806/1 diff --git a/tests/Makefile.inc b/tests/Makefile.inc index 6397e9b..7a7ab1d 100644 --- a/tests/Makefile.inc +++ b/tests/Makefile.inc @@ -232,7 +232,7 @@ $(alltests): $$($$(@)-bin) rm -f $(testobj)/junit-$(subst /,_,$(patsubst $(testobj)/%/,%,$(dir $^)))$*$.xml rm -f $(testobj)/$(subst /,_,$^).failed - -./$^ || echo failed > $(testobj)/$(subst /,_,$^).failed + -$^ || echo failed > $(testobj)/$(subst /,_,$^).failed # Build a code coverage report by collecting all the gcov files into a single # report. If COV is not set, this might be a user error, and they're trying -- To view, visit https://review.coreboot.org/c/coreboot/+/58806 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c3638b1af7531dbe8e956dcbe168250a235ead4 Gerrit-Change-Number: 58806 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/cbfs: Add cbfs_preload()
by Raul Rangel (Code Review) 01 Nov '21

01 Nov '21

Attention is currently required from: Jason Glenesk, Furquan Shaikh, Marshall Dawson, Julius Werner, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56491 ) Change subject: lib/cbfs: Add cbfs_preload() ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/56491 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I879fc1316f97417a4b82483d353abdbd02b98a31 Gerrit-Change-Number: 56491 Gerrit-PatchSet: 11 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 01 Nov 2021 22:28:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: lib/list: Add list_append
by Raul Rangel (Code Review) 01 Nov '21

01 Nov '21

Attention is currently required from: Jakub Czapiga. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58805 ) Change subject: lib/list: Add list_append ...................................................................... lib/list: Add list_append This method will add a node to the end of the list. BUG=b:179699789 TEST=Boot guybrush to the OS Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I1792e40f789e3ef16ceca65ce4cae946e08583d1 --- M src/include/list.h M src/lib/list.c M tests/lib/list-test.c 3 files changed, 30 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/58805/1 diff --git a/src/include/list.h b/src/include/list.h index 6f0b54d..bfd92a7 100644 --- a/src/include/list.h +++ b/src/include/list.h @@ -15,6 +15,8 @@ void list_insert_after(struct list_node *node, struct list_node *after); // Insert list_node node before list_node before in a doubly linked list. void list_insert_before(struct list_node *node, struct list_node *before); +// Appends the node to the end of the list. +void list_append(struct list_node *node, struct list_node *head); #define list_for_each(ptr, head, member) \ for ((ptr) = container_of((head).next, typeof(*(ptr)), member); \ diff --git a/src/lib/list.c b/src/lib/list.c index 01d5c89..c3f8ee4 100644 --- a/src/lib/list.c +++ b/src/lib/list.c @@ -28,3 +28,11 @@ if (node->prev) node->prev->next = node; } + +void list_append(struct list_node *node, struct list_node *head) +{ + while (head->next) + head = head->next; + + list_insert_after(node, head); +} diff --git a/tests/lib/list-test.c b/tests/lib/list-test.c index 309346a..39bfb17 100644 --- a/tests/lib/list-test.c +++ b/tests/lib/list-test.c @@ -116,12 +116,32 @@ free(c1); } +void test_list_append(void **state) +{ + size_t idx; + struct test_container *node; + struct list_node root = {}; + struct test_container nodes[] = { + {1}, {2}, {3} + }; + + for (idx = 0; idx < ARRAY_SIZE(nodes); ++idx) + list_append(&nodes[idx].list_node, &root); + + idx = 0; + list_for_each(node, root, list_node) { + assert_ptr_equal(node, &nodes[idx]); + idx++; + } +} + int main(void) { const struct CMUnitTest tests[] = { cmocka_unit_test(test_list_insert_after), cmocka_unit_test(test_list_insert_before), cmocka_unit_test(test_list_remove), + cmocka_unit_test(test_list_append), }; -- To view, visit https://review.coreboot.org/c/coreboot/+/58805 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1792e40f789e3ef16ceca65ce4cae946e08583d1 Gerrit-Change-Number: 58805 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib: Add lib.c to all stages
by Raul Rangel (Code Review) 01 Nov '21

01 Nov '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58804 ) Change subject: lib: Add lib.c to all stages ...................................................................... lib: Add lib.c to all stages This will be used in cbfs.c which is used in all stages. BUG=b:179699789 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I0713ae766c0ac9e43de702690ad0ba961d636d18 --- M src/lib/Makefile.inc 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/58804/1 diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 693a526..520a1ad 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -28,6 +28,8 @@ $(obj)/ramstage/lib/asan.o: CFLAGS_asan = endif +all-y += list.c + decompressor-y += decompressor.c $(call src-to-obj,decompressor,$(dir)/decompressor.c): $(objcbfs)/bootblock.lz4 $(call src-to-obj,decompressor,$(dir)/decompressor.c): CCACHE_EXTRAFILES=$(objcbfs)/bootblock.lz4 @@ -154,7 +156,6 @@ ramstage-$(CONFIG_GENERIC_UDELAY) += timer.c ramstage-y += b64_decode.c ramstage-$(CONFIG_ACPI_NHLT) += nhlt.c -ramstage-y += list.c ramstage-$(CONFIG_FLATTENED_DEVICE_TREE) += device_tree.c ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit.c ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit_payload.c -- To view, visit https://review.coreboot.org/c/coreboot/+/58804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0713ae766c0ac9e43de702690ad0ba961d636d18 Gerrit-Change-Number: 58804 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in edk2[coreboot-stable202108]: UefiPayloadPkg: Add build option to disable Above 4G Decode
by Sean Rhodes (Code Review) 01 Nov '21

01 Nov '21

Attention is currently required from: Matt DeVillier. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/edk2/+/58801 ) Change subject: UefiPayloadPkg: Add build option to disable Above 4G Decode ...................................................................... Patch Set 1: (1 comment) File UefiPayloadPkg/UefiPayloadPkg.dsc: https://review.coreboot.org/c/edk2/+/58801/comment/4efb8b51_7948497d PS1, Line 327: DECODE MEMORY -- To view, visit https://review.coreboot.org/c/edk2/+/58801 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: edk2 Gerrit-Branch: coreboot-stable202108 Gerrit-Change-Id: I50e9d9052b344519f46419a01b27b2ca43047943 Gerrit-Change-Number: 58801 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Mon, 01 Nov 2021 22:19:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/vendorcode/amd : Zork, MI: Bug in AGESA FabricResourceManagerUnbL...
by Jason Nein (Code Review) 01 Nov '21

01 Nov '21

Jason Nein has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58803 ) Change subject: src/vendorcode/amd : Zork, MI: Bug in AGESA FabricResourceManagerUnbLib.c ...................................................................... src/vendorcode/amd : Zork, MI: Bug in AGESA FabricResourceManagerUnbLib.c Fixing coverity issues: Out-of-bounds read BUG=b:147411796 TEST=Build pass and run the normal boot on Guybrush Signed-off-by: Jason Nien <finaljason(a)gmail.com> Change-Id: I01e134cb6b025bf7cb5030cd9378297d7f6df509 --- M src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c M src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/58803/1 diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c index 8735dac..afa8ae5 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c @@ -229,7 +229,7 @@ MmioRange[MmioPair].Base = (MmioRange[MmioPair].Base <= NewMmioRange.Base) ? MmioRange[MmioPair].Base : NewMmioRange.Base; MmioRange[MmioPair].Modified = TRUE; - for (i = 1; NewMmioRange.Limit >= MmioRange[MmioPair + i].Base; i++) { + for (i = 1; NewMmioRange.Limit >= MmioRange[MmioPair + i].Base && (MmioPair + i) < 12; i++) { if ((NewMmioRange.Attribute.MmioPostedRange == MmioRange[MmioPair + i].Attribute.MmioPostedRange) && (NewMmioRange.Attribute.MmioReadableRange == MmioRange[MmioPair + i].Attribute.MmioReadableRange) && (NewMmioRange.Attribute.MmioWritableRange == MmioRange[MmioPair + i].Attribute.MmioWritableRange) && diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c index 714f970..a087e2a 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c @@ -225,7 +225,7 @@ MmioRange[MmioPair].Base = (MmioRange[MmioPair].Base <= NewMmioRange.Base) ? MmioRange[MmioPair].Base : NewMmioRange.Base; MmioRange[MmioPair].Modified = TRUE; - for (i = 1; NewMmioRange.Limit >= MmioRange[MmioPair + i].Base; i++) { + for (i = 1; NewMmioRange.Limit >= MmioRange[MmioPair + i].Base && (MmioPair + i) < 12; i++) { if ((NewMmioRange.Attribute.MmioPostedRange == MmioRange[MmioPair + i].Attribute.MmioPostedRange) && (NewMmioRange.Attribute.MmioReadableRange == MmioRange[MmioPair + i].Attribute.MmioReadableRange) && (NewMmioRange.Attribute.MmioWritableRange == MmioRange[MmioPair + i].Attribute.MmioWritableRange) && -- To view, visit https://review.coreboot.org/c/coreboot/+/58803 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01e134cb6b025bf7cb5030cd9378297d7f6df509 Gerrit-Change-Number: 58803 Gerrit-PatchSet: 1 Gerrit-Owner: Jason Nein <finaljason(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/block/cpu: Add support for cbfs_cache region
by Karthik Ramasubramanian (Code Review) 01 Nov '21

01 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Furquan Shaikh, Marshall Dawson, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56578 ) Change subject: soc/amd/common/block/cpu: Add support for cbfs_cache region ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56578 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I268b6bc10906932ee94f795684a28cfac247a68c Gerrit-Change-Number: 56578 Gerrit-PatchSet: 10 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 01 Nov 2021 22:10:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: lib/cbfs: Add CBFS_CACHE_ALIGN Kconfig option
by Karthik Ramasubramanian (Code Review) 01 Nov '21

01 Nov '21

Attention is currently required from: Raul Rangel. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58706 ) Change subject: lib/cbfs: Add CBFS_CACHE_ALIGN Kconfig option ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58706 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74598d4bcbca9a01cc8c65012d7e4ae341d052b1 Gerrit-Change-Number: 58706 Gerrit-PatchSet: 6 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Mon, 01 Nov 2021 22:09:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/lpc: Set CBFS_CACHE_ALIGN to 64 when using SPI DMA
by Karthik Ramasubramanian (Code Review) 01 Nov '21

01 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Julius Werner, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58707 ) Change subject: soc/amd/common/block/lpc: Set CBFS_CACHE_ALIGN to 64 when using SPI DMA ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58707 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I228372ff19f958c8e9cf5e51dcc3d37d9f92abec Gerrit-Change-Number: 58707 Gerrit-PatchSet: 7 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 01 Nov 2021 22:09:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2021