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Change subject: UefiPayloadPkg: Allow below 4GB memory
......................................................................
Patch Set 1:
(1 comment)
File UefiPayloadPkg/UefiPayloadPkg.dec:
https://review.coreboot.org/c/edk2/+/58802/comment/14096320_ef6285cc
PS1, Line 80: 0x00000018
this will create a conflict with the Pcd defined below; bump to 19, reorder 😊
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Change subject: Add console deinit API, use in SMM handler
......................................................................
Patch Set 11:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56386/comment/4c26c6a5_373508ba
PS11, Line 14: on an OCP Delta Lake server: uart8250_init disables interrupts because it
> uart8250_init should only be called in the first SMM call (that prints something), no? That's normal […]
yes in coreboot stage it's fine, but this change is for entering and exiting smm while printing smm log under Linux, so it's in runtime OS stage.
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/edk2/+/58801
to look at the new patch set (#2).
Change subject: UefiPayloadPkg: Add build option to disable Above 4G Decode
......................................................................
UefiPayloadPkg: Add build option to disable Above 4G Decode
Dovetails with coreboot commit 766e481a:
"payloads/external/tianocore: Add build argument for 4G Decode"
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: I50e9d9052b344519f46419a01b27b2ca43047943
---
M UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.c
M UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf
M UefiPayloadPkg/UefiPayloadPkg.dec
M UefiPayloadPkg/UefiPayloadPkg.dsc
4 files changed, 52 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/edk2 refs/changes/01/58801/2
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Change subject: UefiPayloadPkg: Add build option to disable Above 4G Decode
......................................................................
Patch Set 1:
(1 comment)
File UefiPayloadPkg/UefiPayloadPkg.dsc:
https://review.coreboot.org/c/edk2/+/58801/comment/53ad37a4_c8ab3e88
PS1, Line 327: DECODE
> MEMORY
that's what I get for pulling it directly from your repo and not mine =P
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Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58803 )
Change subject: src/vendorcode/amd : Zork, MI: Bug in AGESA FabricResourceManagerUnbLib.c
......................................................................
Patch Set 1:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58803/comment/8ac1b980_76f35ee9
PS1, Line 7: src/vendorcode/amd : Zork, MI: Bug in AGESA FabricResourceManagerUnbLib.c
coreboot has a couple of references for how to write a good commit message although none are really excellent. But you can make sure you follow https://www.coreboot.org/Git#Commit_messages or https://doc.coreboot.org/tutorial/part2.html#step-4a-use-the-command-line-t….
Specifically, you'll often be asked to shorten the subject line:
* the subject needs to give some hint of what you're doing
* no need to use src in the path
* you can substitute vc for vendorcode
* no space before a colon
* this patch doesn't apply to Zork nor to MI
* I often feel there's no reason to identify the filename as it's already pretty evident
So the subject line might be "vc/amd/agesa: fix out of bounds read".
https://review.coreboot.org/c/coreboot/+/58803/comment/744a0d42_2f83f9bd
PS1, Line 9: Fixing coverity issues: Out-of-bounds read
Make sure you use complete sentences and that your verbs are imperative, e.g. "Fix out-of-bounds read issue found by coverity". And it doesn't hurt to put the coverity error into the commit message too.
235 MmioRange[MmioPair].Modified = TRUE;
>>> CID 1376956: Memory - illegal accesses (OVERRUN)
>>> Overrunning array "MmioRange" of 12 20-byte elements at element index 12 (byte offset 240) using index "MmioPair + i" (which evaluates to 12).
236 for (i = 1; NewMmioRange.Limit >= MmioRange[MmioPair + i].Base; i++) {
https://review.coreboot.org/c/coreboot/+/58803/comment/1b23749e_e465fae4
PS1, Line 11: BUG=b:147411796
This doesn't really apply for Trinity and Kabini changes. You could omit it.
https://review.coreboot.org/c/coreboot/+/58803/comment/22b68957_16e38f99
PS1, Line 12: Build pass and run the normal boot on Guybrush
Guybrush doesn't use this code. Since you don't have HW to test with, and Jenkins has built it, I'd be fine with simply saying TEST=none.
File src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c:
https://review.coreboot.org/c/coreboot/+/58803/comment/9ead3bfc_6fc213d9
PS1, Line 232: 12
Is there a defined value somewhere that can be used instead of 12?
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Change subject: psp_verstage: convert relative address in EFS2
......................................................................
Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58316/comment/b797527c_27b95da3
PS5, Line 9: is
> are relative addresses
Done
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Karthik Ramasubramanian, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58316
to look at the new patch set (#6).
Change subject: psp_verstage: convert relative address in EFS2
......................................................................
psp_verstage: convert relative address in EFS2
Addresses in AMD fw table with EFS gen2 are relative addresses, but
PSP doesn't accept relative addresses in update_psp_bios_dir().
Check for EFS gen2 and convert them as needed.
BUG=b:194263115
TEST=build and boot on guybrush and shuboz
Signed-off-by: Kangheui Won <khwon(a)chromium.org>
Change-Id: I95813beba7278480e6640599fcf7445923259361
---
M src/soc/amd/cezanne/include/soc/iomap.h
M src/soc/amd/common/block/include/amdblocks/psp_efs.h
M src/soc/amd/common/psp_verstage/psp_verstage.c
M src/soc/amd/picasso/include/soc/iomap.h
4 files changed, 13 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/58316/6
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58351 )
Change subject: soc/intel/common: add generic gpio lock mechanism
......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/common/block/smm/smihandler.c:
https://review.coreboot.org/c/coreboot/+/58351/comment/2fc7874d_53c30152
PS1, Line 348: gpio_lock_pad
> I implemented Karthik's suggestion in the latest patchset, let me know if this is what you had in mi […]
I think you may also need `HAVE_DEBUG_GPIO` ?
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