coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: lib: Add list.c to all stages
by Raul Rangel (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Julius Werner, Karthik Ramasubramanian. Hello build bot (Jenkins), Julius Werner, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58804 to look at the new patch set (#2). Change subject: lib: Add list.c to all stages ...................................................................... lib: Add list.c to all stages This will be used in cbfs.c which is used in all stages. BUG=b:179699789 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I0713ae766c0ac9e43de702690ad0ba961d636d18 --- M src/lib/Makefile.inc 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/58804/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0713ae766c0ac9e43de702690ad0ba961d636d18 Gerrit-Change-Number: 58804 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: commonlib/mem_pool: Allow configuring the alignment
by Raul Rangel (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Furquan Shaikh, Julius Werner, Angel Pons, Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56580 ) Change subject: commonlib/mem_pool: Allow configuring the alignment ...................................................................... Patch Set 10: (1 comment) File src/commonlib/include/commonlib/mem_pool.h: https://review.coreboot.org/c/coreboot/+/56580/comment/82fca91d_41ebdb7f PS7, Line 59: mp->alignment = alignment; > No, I'd say it's a libc thing and you can expect it to be available here (from <assert.h>). […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/56580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d77ffe4411f86c54450305320c9f52ab41a3075 Gerrit-Change-Number: 56580 Gerrit-PatchSet: 10 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 02 Nov 2021 03:36:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: commonlib/mem_pool: Allow configuring the alignment
by Raul Rangel (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Furquan Shaikh, Julius Werner, Angel Pons, Karthik Ramasubramanian. Hello build bot (Jenkins), Furquan Shaikh, Julius Werner, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56580 to look at the new patch set (#10). Change subject: commonlib/mem_pool: Allow configuring the alignment ...................................................................... commonlib/mem_pool: Allow configuring the alignment AMD platforms require the destination to be 64 byte aligned in order to use the SPI DMA controller. This is enforced by the destination address register because the first 6 bits are marked as reserved. This change adds an option to the mem_pool so the alignment can be configured. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I8d77ffe4411f86c54450305320c9f52ab41a3075 --- M src/commonlib/include/commonlib/mem_pool.h M src/commonlib/mem_pool.c M src/lib/cbfs.c 3 files changed, 18 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/56580/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/56580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d77ffe4411f86c54450305320c9f52ab41a3075 Gerrit-Change-Number: 56580 Gerrit-PatchSet: 10 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/variants/primus: disable LTR for PCIe-eMMC bridge
by Casper Chang (Code Review) 02 Nov '21

02 Nov '21

Casper Chang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58831 ) Change subject: mb/google/brya/variants/primus: disable LTR for PCIe-eMMC bridge ...................................................................... mb/google/brya/variants/primus: disable LTR for PCIe-eMMC bridge disable LTR for PCIe-eMMC bridge BUG=b:204469567 TEST=Boot into eMMC storage and perform suspend stress 100 cycle passed Signed-off-by: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Change-Id: I7236fc7f3318d07f0d9e9d9da7cd463ef3dde1a0 --- M src/mainboard/google/brya/variants/primus/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/58831/1 diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb index c4debb4..8db2ddb 100644 --- a/src/mainboard/google/brya/variants/primus/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus/overridetree.cb @@ -154,7 +154,7 @@ register "pch_pcie_rp[PCH_RP(9)]" = "{ .clk_src = 0, .clk_req = 0, - .flags = PCIE_RP_LTR | PCIE_RP_AER, + .flags = PCIE_RP_AER, }" end #PCIE9-12 SSD device ref i2c0 on -- To view, visit https://review.coreboot.org/c/coreboot/+/58831 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7236fc7f3318d07f0d9e9d9da7cd463ef3dde1a0 Gerrit-Change-Number: 58831 Gerrit-PatchSet: 1 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork/var/vilboz: Add fw_config probe for ALC5682-VD & VS
by Frank Wu (Code Review) 02 Nov '21

02 Nov '21

Frank Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58830 ) Change subject: mb/google/zork/var/vilboz: Add fw_config probe for ALC5682-VD & VS ...................................................................... mb/google/zork/var/vilboz: Add fw_config probe for ALC5682-VD & VS ALC5682-VD/ALC5682I-VS load different kernel driver by different hid name. Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config. Define FW_CONFIG bits 36 - 37 (SSFC bits 4 - 5) for codec selection. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:200103232, b:195042130 BRANCH=firmware-zork-13434.B TEST=ALC5682-VD/ALC5682I-VS audio codec can work Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Change-Id: Idf0119edf90a3372c8a34f708a7aac11c0188b76 --- M src/mainboard/google/zork/variants/baseboard/helpers.c M src/mainboard/google/zork/variants/vilboz/overridetree.cb M src/mainboard/google/zork/variants/vilboz/variant.c 3 files changed, 40 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/58830/1 diff --git a/src/mainboard/google/zork/variants/baseboard/helpers.c b/src/mainboard/google/zork/variants/baseboard/helpers.c index d6c5e48..7057a48 100644 --- a/src/mainboard/google/zork/variants/baseboard/helpers.c +++ b/src/mainboard/google/zork/variants/baseboard/helpers.c @@ -55,6 +55,9 @@ /* Audio AMP type */ FW_CONFIG_MASK_AUDIO_AMP = 0x1, FW_CONFIG_SHIFT_AUDIO_AMP = 35, + /* Audio codec type */ + FW_CONFIG_MASK_AUDIO_CODEC_SOURCE = 0x3, + FW_CONFIG_SHIFT_AUDIO_CODEC_SOURCE = 36, }; static int get_fw_config(uint64_t *val) diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb index 1e83f6f..f9a9a74 100644 --- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb @@ -5,6 +5,10 @@ option AUDIO_AMP_I2C_MODE 0 option AUDIO_AMP_AUTO_MODE 1 end + field AUDIO_CODEC_SOURCE 36 37 + option AUDIO_CODEC_ALC5682 0 + option AUDIO_CODEC_ALC5682I_VS 1 + end end chip soc/amd/picasso diff --git a/src/mainboard/google/zork/variants/vilboz/variant.c b/src/mainboard/google/zork/variants/vilboz/variant.c index 43ca0e5..47b60ac 100644 --- a/src/mainboard/google/zork/variants/vilboz/variant.c +++ b/src/mainboard/google/zork/variants/vilboz/variant.c @@ -5,6 +5,10 @@ #include <fw_config.h> #include <sar.h> #include "chip.h" +#include <drivers/i2c/generic/chip.h> +#include <device/device.h> +#include <device/path.h> +#include <console/console.h> static const fsp_ddi_descriptor hdmi_ddi_descriptors[] = { { // DDI0, DP0, eDP @@ -35,6 +39,33 @@ *ddi_num = ARRAY_SIZE(hdmi_ddi_descriptors); } +extern struct chip_operations drivers_i2c_generic_ops; + +static void audio_codec_update(void) +{ + const struct device_path codec_path[] = { + {.type = DEVICE_PATH_PCI, .pci.devfn = LPC_DEVFN}, + {.type = DEVICE_PATH_PNP, .pnp.port = 0xc09, .pnp.device = 0}, + {.type = DEVICE_PATH_GENERIC, .generic.id = 0}, + {.type = DEVICE_PATH_I2C, .i2c.device = 0x1a, .i2c.mode_10bit = I2C_MODE_7_BIT } + }; + + const struct device *codec = + find_dev_nested_path(pci_root_bus(), codec_path, ARRAY_SIZE(codec_path)); + struct drivers_i2c_generic_config *config; + + if (!codec || (codec->chip_ops != &drivers_i2c_generic_ops) || !codec->chip_info) + return; + + config = codec->chip_info; + + if (fw_config_probe(FW_CONFIG(AUDIO_CODEC_SOURCE, AUDIO_CODEC_ALC5682))) + config->hid = "10EC5682"; + else if (fw_config_probe(FW_CONFIG(AUDIO_CODEC_SOURCE, AUDIO_CODEC_ALC5682I_VS))) + config->hid = "RTL5682"; + printk(BIOS_INFO, "Configure audio codec, config->hid %s\n", config->hid); +} + void variant_devtree_update(void) { struct soc_amd_picasso_config *soc_cfg; @@ -57,6 +88,8 @@ soc_cfg->edp_tuningset.deemph_6db4 = 0x00; soc_cfg->edp_tuningset.boostadj = 0x80; } + + audio_codec_update(); } /* -- To view, visit https://review.coreboot.org/c/coreboot/+/58830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf0119edf90a3372c8a34f708a7aac11c0188b76 Gerrit-Change-Number: 58830 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/list: Add list_append
by Raul Rangel (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Jakub Czapiga, Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58805 ) Change subject: lib/list: Add list_append ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > I mean, there's nothing wrong with adding this, but why not just add new elements in your cbfs_prelo […] Yeah, I should have sent this later. It's related to having making cbfs_preload use a single thread. I want the newest items added at the end of the list so they get processed last. -- To view, visit https://review.coreboot.org/c/coreboot/+/58805 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1792e40f789e3ef16ceca65ce4cae946e08583d1 Gerrit-Change-Number: 58805 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 02 Nov 2021 02:57:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Add a stub implementation of the MT8186 SoC
by Rex-BC Chen (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Paul Menzel, Yu-Ping Wu, Felix Held. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58640 ) Change subject: soc/mediatek/mt8186: Add a stub implementation of the MT8186 SoC ...................................................................... Patch Set 5: (1 comment) File src/soc/mediatek/mt8186/include/soc/timer.h: https://review.coreboot.org/c/coreboot/+/58640/comment/24b8ace3_588f45a4 PS3, Line 9: TIE_0_EN = 1 << 3, : COMP_15_EN = 1 << 10, : COMP_20_EN = 1 << 11, : COMP_25_EN = 1 << 12, > I think I would move these to v2 on upcoming patches. […] I have done on https://review.coreboot.org/c/coreboot/+/58829 -- To view, visit https://review.coreboot.org/c/coreboot/+/58640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I579f79c15f4bf5e1daf6b35c70cfd00a985a0b81 Gerrit-Change-Number: 58640 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 02 Nov 2021 02:51:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: move timer enum variables to timer_v2.h
by Rex-BC Chen (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58829 ) Change subject: soc/mediatek/mt8195: move timer enum variables to timer_v2.h ...................................................................... soc/mediatek/mt8195: move timer enum variables to timer_v2.h Some enum variables of timer v2 is the same between MT8195 and MT8186, so we move these enum variable to common timer_v2.h TEST=emerge-cherry coreboot BUG=b:200134633 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I89891a19e622aa24783025e73c38c4ffa43aa166 --- M src/soc/mediatek/common/include/soc/timer_v2.h M src/soc/mediatek/mt8195/include/soc/timer.h 2 files changed, 13 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/58829/1 diff --git a/src/soc/mediatek/common/include/soc/timer_v2.h b/src/soc/mediatek/common/include/soc/timer_v2.h index 507814b..2305928 100644 --- a/src/soc/mediatek/common/include/soc/timer_v2.h +++ b/src/soc/mediatek/common/include/soc/timer_v2.h @@ -9,6 +9,19 @@ #define GPT_MHZ 13 +enum { + TIE_0_EN = 1 << 3, + COMP_15_EN = 1 << 10, + COMP_20_EN = 1 << 11, + COMP_25_EN = 1 << 12, + + COMP_FEATURE_MASK = COMP_15_EN | COMP_20_EN | COMP_25_EN | TIE_0_EN, + + COMP_15_MASK = COMP_15_EN, + COMP_20_MASK = COMP_20_EN | TIE_0_EN, + COMP_25_MASK = COMP_20_EN | COMP_25_EN, +}; + struct mtk_gpt_regs { u32 reserved1[40]; u32 gpt6_con; diff --git a/src/soc/mediatek/mt8195/include/soc/timer.h b/src/soc/mediatek/mt8195/include/soc/timer.h index da073e1..d2959bf 100644 --- a/src/soc/mediatek/mt8195/include/soc/timer.h +++ b/src/soc/mediatek/mt8195/include/soc/timer.h @@ -5,16 +5,4 @@ #include <soc/timer_v2.h> -enum { - TIE_0_EN = 1 << 3, - COMP_15_EN = 1 << 10, - COMP_20_EN = 1 << 11, - COMP_25_EN = 1 << 12, - - COMP_FEATURE_MASK = COMP_15_EN | COMP_20_EN | COMP_25_EN | TIE_0_EN, - - COMP_15_MASK = COMP_15_EN, - COMP_20_MASK = COMP_20_EN | TIE_0_EN, - COMP_25_MASK = COMP_20_EN | COMP_25_EN, -}; #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/58829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89891a19e622aa24783025e73c38c4ffa43aa166 Gerrit-Change-Number: 58829 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8186: Add a stub implementation of the MT8186 SoC
by Rex-BC Chen (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Rex-BC Chen, Paul Menzel, Yu-Ping Wu, Felix Held. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58640 to look at the new patch set (#5). Change subject: soc/mediatek/mt8186: Add a stub implementation of the MT8186 SoC ...................................................................... soc/mediatek/mt8186: Add a stub implementation of the MT8186 SoC Add new folder and basic drivers for Mediatek SoC 'MT8186'. Difference of modules including in this patch between MT8186 and existing SoCs: Timer: Similar to MT8195, MT8186 uses v2 timer. EMI/PLL/SPI: Different from existing SoCs. TEST=boot from SPI-NOR and show uart log on MT8186 EVB BUG=b:200134633 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I579f79c15f4bf5e1daf6b35c70cfd00a985a0b81 --- A src/soc/mediatek/mt8186/Kconfig A src/soc/mediatek/mt8186/Makefile.inc A src/soc/mediatek/mt8186/bootblock.c A src/soc/mediatek/mt8186/emi.c A src/soc/mediatek/mt8186/include/soc/addressmap.h A src/soc/mediatek/mt8186/include/soc/emi.h A src/soc/mediatek/mt8186/include/soc/memlayout.ld A src/soc/mediatek/mt8186/include/soc/pll.h A src/soc/mediatek/mt8186/include/soc/spi.h A src/soc/mediatek/mt8186/include/soc/timer.h A src/soc/mediatek/mt8186/soc.c A src/soc/mediatek/mt8186/spi.c 12 files changed, 288 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/58640/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/58640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I579f79c15f4bf5e1daf6b35c70cfd00a985a0b81 Gerrit-Change-Number: 58640 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: vc/amd/agesa: fix out-of-bounds read
by Bao Zheng (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Jason Nein, Matt Papageorge, Felix Held. Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58803 ) Change subject: vc/amd/agesa: fix out-of-bounds read ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/58803/comment/0ae09f7b_0c7062e6 PS3, Line 10: Should add a pointer to issue tracker which can get event in coreboot gerrit. BUG=b:147411796 File src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c: https://review.coreboot.org/c/coreboot/+/58803/comment/1eecc2aa_8bcbd486 PS3, Line 232: (MmioPair + i) < MMIO_REG_PAIR_NUM Should the check be done before accessing the table (before &&)? -- To view, visit https://review.coreboot.org/c/coreboot/+/58803 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01e134cb6b025bf7cb5030cd9378297d7f6df509 Gerrit-Change-Number: 58803 Gerrit-PatchSet: 3 Gerrit-Owner: Jason Nein <finaljason(a)gmail.com> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Nein <finaljason(a)gmail.com> Gerrit-Attention: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 02 Nov 2021 01:48:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2021