coreboot-gerrit November 2021

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Change in coreboot[master]: device/include: Fix potential build error
by Alan Huang (Code Review) 02 Nov '21

02 Nov '21

Alan Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58832 ) Change subject: device/include: Fix potential build error ...................................................................... device/include: Fix potential build error Add include guard for usbc_mux.h BUG=none BRANCH=none TEST=Build Pass Signed-off-by: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Change-Id: I47988edee84d17f0a15cfda1ac6f0187326bd331 --- M src/include/device/usbc_mux.h 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/58832/1 diff --git a/src/include/device/usbc_mux.h b/src/include/device/usbc_mux.h index e395d2d..0648a74 100644 --- a/src/include/device/usbc_mux.h +++ b/src/include/device/usbc_mux.h @@ -1,5 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __USBC_MUX_H__ +#define __USBC_MUX_H__ + /* struct to hold all USB-C mux related variables */ struct usbc_mux_info { bool dp; /* DP connected */ @@ -67,3 +70,5 @@ }; const struct usbc_ops *usbc_get_ops(void); + +#endif /* __USBC_MUX_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/58832 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47988edee84d17f0a15cfda1ac6f0187326bd331 Gerrit-Change-Number: 58832 Gerrit-PatchSet: 1 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8186: Add a stub implementation of the MT8186 SoC
by Rex-BC Chen (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yu-Ping Wu, Felix Held. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58640 ) Change subject: soc/mediatek/mt8186: Add a stub implementation of the MT8186 SoC ...................................................................... Patch Set 6: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/58640/comment/0cb3c73c_52e1c02d PS2, Line 10: > > And that is big problem, and has to be improved. […] I have added these comments for each module. File src/soc/mediatek/mt8186/include/soc/timer.h: PS2: > Yes, and that should be documented somewhere. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/58640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I579f79c15f4bf5e1daf6b35c70cfd00a985a0b81 Gerrit-Change-Number: 58640 Gerrit-PatchSet: 6 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 02 Nov 2021 04:53:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: util/spd_tools: Add LP5 support for ADL
by Reka Norman (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Sridhar Siricilla, Nick Vaccaro, Balaji Manigandan, Krishna P Bhat D, Karthik Ramasubramanian. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58679 ) Change subject: util/spd_tools: Add LP5 support for ADL ...................................................................... Patch Set 6: (2 comments) File util/spd_tools/src/spd_gen/lp5.go: https://review.coreboot.org/c/coreboot/+/58679/comment/27944892_2ef12d9d PS5, Line 18: DensityPerDieGb int Yes, LP5 only supports one channel per die. I believe dual channel dies were a new feature added in LP4 then removed again in LP5 to simplify the design. From Section 2.2 of the LP5 spec: > LPDDR5/LPDDR5X SDRAM is a high-speed synchronous SDRAM device internally configured with 1 channel containing either 16 or 8 DQ signals. https://review.coreboot.org/c/coreboot/+/58679/comment/3a75cf62_b6ef18e3 PS5, Line 221: TCKMinPs: > Is this the clock period in the command & address clock(CK) or the data clock(WCK)? I believe it is […] Yes, this is the CK period. Based on the Intel advisory, this is how the MRC expects this field to be used for LP5. I've added a comment to the code explaining this and also explaining the calculation. -- To view, visit https://review.coreboot.org/c/coreboot/+/58679 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1e68d44f7c0ad64aa9904b7e1297d24bd5db56e Gerrit-Change-Number: 58679 Gerrit-PatchSet: 6 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 02 Nov 2021 04:05:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: util/spd_tools: Add LP5 support for ADL
by Reka Norman (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Reka Norman, Sridhar Siricilla, Nick Vaccaro, Balaji Manigandan, Krishna P Bhat D. Hello build bot (Jenkins), Tim Wawrzynczak, Sridhar Siricilla, Nick Vaccaro, Balaji Manigandan, Krishna P Bhat D, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58679 to look at the new patch set (#6). Change subject: util/spd_tools: Add LP5 support for ADL ...................................................................... util/spd_tools: Add LP5 support for ADL Add LP5 support to spd_tools. Currently, only Intel Alder Lake (ADL) is supported. The SPDs are generated based on a combination of: - The LPDDR5 spec JESD209-5B. - The SPD spec SPD4.1.2.M-2 (the LPDDR3/4 spec is used since JEDEC has not released an SPD spec for LPDDR5). - Intel recommendations in advisory #616599. BUG=b:201234943, b:198704251 TEST=Generate the SPD and manifests for a test part, and check that the SPD matches Intel's expectation. More details in CB:58680. Change-Id: Ic1e68d44f7c0ad64aa9904b7e1297d24bd5db56e Signed-off-by: Reka Norman <rekanorman(a)google.com> --- M util/spd_tools/src/part_id_gen/part_id_gen.go A util/spd_tools/src/spd_gen/lp5.go M util/spd_tools/src/spd_gen/spd_gen.go 3 files changed, 591 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/58679/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/58679 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1e68d44f7c0ad64aa9904b7e1297d24bd5db56e Gerrit-Change-Number: 58679 Gerrit-PatchSet: 6 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8186: Add a stub implementation of the MT8186 SoC
by Rex-BC Chen (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Paul Menzel, Yu-Ping Wu, Felix Held. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58640 to look at the new patch set (#6). Change subject: soc/mediatek/mt8186: Add a stub implementation of the MT8186 SoC ...................................................................... soc/mediatek/mt8186: Add a stub implementation of the MT8186 SoC Add new folder and basic drivers for Mediatek SoC 'MT8186'. Difference of modules including in this patch between MT8186 and existing SoCs: Timer: Similar to MT8195, MT8186 uses v2 timer. EMI/PLL/SPI: Different from existing SoCs. TEST=boot from SPI-NOR and show uart log on MT8186 EVB BUG=b:200134633 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I579f79c15f4bf5e1daf6b35c70cfd00a985a0b81 --- A src/soc/mediatek/mt8186/Kconfig A src/soc/mediatek/mt8186/Makefile.inc A src/soc/mediatek/mt8186/bootblock.c A src/soc/mediatek/mt8186/emi.c A src/soc/mediatek/mt8186/include/soc/addressmap.h A src/soc/mediatek/mt8186/include/soc/emi.h A src/soc/mediatek/mt8186/include/soc/memlayout.ld A src/soc/mediatek/mt8186/include/soc/pll.h A src/soc/mediatek/mt8186/include/soc/spi.h A src/soc/mediatek/mt8186/include/soc/timer.h A src/soc/mediatek/mt8186/soc.c A src/soc/mediatek/mt8186/spi.c 12 files changed, 313 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/58640/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/58640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I579f79c15f4bf5e1daf6b35c70cfd00a985a0b81 Gerrit-Change-Number: 58640 Gerrit-PatchSet: 6 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya: Correct AT24 NVM address size
by Varshit B Pandya (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Paul Menzel. Varshit B Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58769 ) Change subject: mb/google/brya: Correct AT24 NVM address size ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/58769/comment/cfbdb59a_fdfffc9a PS2, Line 15: 0x0D > good eyes 👍 Done https://review.coreboot.org/c/coreboot/+/58769/comment/3b6289c5_f40c6037 PS2, Line 15: 0x0D > good eyes 👍 Done -- To view, visit https://review.coreboot.org/c/coreboot/+/58769 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c1ed5334396e0ca09ea0078426a7b5039ae4e8b Gerrit-Change-Number: 58769 Gerrit-PatchSet: 3 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 02 Nov 2021 03:44:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Correct AT24 NVM address size
by Varshit B Pandya (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Varshit B Pandya, Maulik V Vaghela, Tim Wawrzynczak, Paul Menzel. Hello build bot (Jenkins), Maulik V Vaghela, Tim Wawrzynczak, Paul Menzel, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58769 to look at the new patch set (#3). Change subject: mb/google/brya: Correct AT24 NVM address size ...................................................................... mb/google/brya: Correct AT24 NVM address size Currently, the address size field of AT24 NVM is incorrect, and Linux v5.10 kernel logs the message below: at24 i2c-PRP0001:01: Bad "address-width" property: 14 The valid size of the AT24 NVM is 16 bits so modify the value from 0x0E to 0x10. TEST=Boot brya and check the kernel log and see "Bad address-width" error message is not shown. Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com> Change-Id: I6c1ed5334396e0ca09ea0078426a7b5039ae4e8b --- M src/mainboard/google/brya/variants/brya0/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/58769/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/58769 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c1ed5334396e0ca09ea0078426a7b5039ae4e8b Gerrit-Change-Number: 58769 Gerrit-PatchSet: 3 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lib/cbfs: Add cbfs_preload()
by Raul Rangel (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Jason Glenesk, Furquan Shaikh, Marshall Dawson, Julius Werner, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56491 ) Change subject: lib/cbfs: Add cbfs_preload() ...................................................................... Patch Set 12: (2 comments) File src/lib/Kconfig: https://review.coreboot.org/c/coreboot/+/56491/comment/d8a3de8b_566350f1 PS7, Line 108: config CBFS_PRELOAD > Well, it shouldn't really make a practical difference if the controller uses PIO, it'll just not giv […] Right, it doesn't cause an actual problem booting. It just means that the async transactions can turn into sync transactions unexpectedly and thus penalizing a random section of code. File src/lib/cbfs.c: https://review.coreboot.org/c/coreboot/+/56491/comment/777d4c4e_a0b6a309 PS11, Line 511: cbfs_unmap(rdev_mmap_full(&rdev)); > Rather than duplicating everything in the error path I think it would be better to just merge them, […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/56491 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I879fc1316f97417a4b82483d353abdbd02b98a31 Gerrit-Change-Number: 56491 Gerrit-PatchSet: 12 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 02 Nov 2021 03:36:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: lib/cbfs: Add cbfs_preload()
by Raul Rangel (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Jason Glenesk, Furquan Shaikh, Marshall Dawson, Julius Werner, Karthik Ramasubramanian, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Furquan Shaikh, Marshall Dawson, Julius Werner, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56491 to look at the new patch set (#12). Change subject: lib/cbfs: Add cbfs_preload() ...................................................................... lib/cbfs: Add cbfs_preload() This API will hide all the complexity of preloading a CBFS file. It makes it so the callers simply specify the file to preload and CBFS takes care of the rest. It will start a new thread to read the file into the cbfs_cache. When the file is actually required (i.e., cbfs_load, etc) it will wait for the preload thread to complete (if it hasn't already) and perform verification/decompression using the preloaded buffer. This design allows decompression/verification to happen in the main BSP thread so that timestamps are correctly reflected. BUG=b:179699789 TEST=Test with whole CL chain, verify VGA bios was preloaded and boot time was reduced by 12ms. Logs: Preloading VGA ROM CBFS DEBUG: _cbfs_preload(name='pci1002,1638.rom', force_ro=false) CBFS: Found 'pci1002,1638.rom' @0x20ac40 size 0xd800 in mcache @0xcb7dd0f0 spi_dma_readat_dma: start: dest: 0x021c0000, source: 0x51cc80, size: 55296 took 0 us to acquire mutex start_spi_dma_transaction: dest: 0x021c0000, source: 0x51cc80, remaining: 55296 ... spi_dma_readat_dma: end: dest: 0x021c0000, source: 0x51cc80, remaining: 0 ... CBFS DEBUG: _cbfs_alloc(name='pci1002,1638.rom', alloc=0x00000000(0x00000000), force_ro=false, type=-1) CBFS: Found 'pci1002,1638.rom' @0x20ac40 size 0xd800 in mcache @0xcb7dd0f0 waiting for thread took 0 us CBFS DEBUG: get_preload_rdev(name='pci1002,1638.rom', force_ro=false) preload successful In CBFS, ROM address for PCI: 03:00.0 = 0x021c0000 PCI expansion ROM, signature 0xaa55, INIT size 0xd800, data ptr 0x01b0 PCI ROM image, vendor ID 1002, device ID 1638, PCI ROM image, Class Code 030000, Code Type 00 Copying VGA ROM Image from 0x021c0000 to 0xc0000, 0xd800 bytes $ cbmem ... 40:device configuration 5,399,404 (8,575) 65:Option ROM initialization 5,403,474 (4,070) 66:Option ROM copy done 5,403,488 (14) ... Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I879fc1316f97417a4b82483d353abdbd02b98a31 --- M src/include/cbfs.h M src/lib/Kconfig M src/lib/cbfs.c 3 files changed, 190 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/56491/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/56491 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I879fc1316f97417a4b82483d353abdbd02b98a31 Gerrit-Change-Number: 56491 Gerrit-PatchSet: 12 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lib: Add list.c to all stages
by Raul Rangel (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Julius Werner, Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58804 ) Change subject: lib: Add list.c to all stages ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/58804/comment/e1fac98f_f74804c8 PS1, Line 7: lib > typo Done -- To view, visit https://review.coreboot.org/c/coreboot/+/58804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0713ae766c0ac9e43de702690ad0ba961d636d18 Gerrit-Change-Number: 58804 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 02 Nov 2021 03:36:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit November 2021