coreboot-gerrit November 2021

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Change in coreboot[master]: mb/google/dedede/var/bugzzy: Update charger performance control table
by shkim (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: SH Kim. Hello SH Kim, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/58840 to review the following change. Change subject: mb/google/dedede/var/bugzzy: Update charger performance control table ...................................................................... mb/google/dedede/var/bugzzy: Update charger performance control table Update charger performance control table of DPTF for bugzzy. BUG=None BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> Change-Id: I33e176fcf5d380b315ff352c6c65af3b8b93c4b9 --- M src/mainboard/google/dedede/variants/bugzzy/overridetree.cb 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/58840/1 diff --git a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb index 453d8c3..947fa47 100644 --- a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb +++ b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb @@ -114,10 +114,10 @@ } }" register "controls.charger_perf" = "{ - [0] = { 55, 3500 }, - [1] = { 47, 3000 }, - [2] = { 39, 2500 }, - [3] = { 31, 2000 }, + [0] = { 255, 2800 }, + [1] = { 39, 2500 }, + [2] = { 31, 2000 }, + [3] = { 23, 1500 }, }" device generic 0 on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/58840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33e176fcf5d380b315ff352c6c65af3b8b93c4b9 Gerrit-Change-Number: 58840 Gerrit-PatchSet: 1 Gerrit-Owner: shkim <sh_.kim(a)samsung.com> Gerrit-Reviewer: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/siemens/mc_ehl1: Clean up PCIe root port settings in devicetree
by Werner Zeh (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Paul Menzel, Mario Scheithauer. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58568 ) Change subject: mb/siemens/mc_ehl1: Clean up PCIe root port settings in devicetree ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/58568/comment/cea1e1bc_4f9d6fa7 PS2, Line 9: ports #5 (00:1c.4) and #6 > For the numbering of the root ports #5 and #6 you use a hashtag in front of the number. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/58568 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06f59f0369ffcd958b5fe12bb3c646d37103811f Gerrit-Change-Number: 58568 Gerrit-PatchSet: 3 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Comment-Date: Tue, 02 Nov 2021 06:06:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/siemens/mc_ehl1: Adjust PCIe clock settings in devicetree
by Werner Zeh (Code Review) 02 Nov '21

02 Nov '21

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58740 to look at the new patch set (#3). Change subject: mb/siemens/mc_ehl1: Adjust PCIe clock settings in devicetree ...................................................................... mb/siemens/mc_ehl1: Adjust PCIe clock settings in devicetree On mc_ehl1 there are three of the 6 PCIe clocks used to drive PCIe devices. None of the used clock output is dedicated to a special device (CLK0 drives several devices on the mainboard, CLK1 and CLK2 are connected to a PCIe switch). Therefore do not use a port mapping of the clocks to avoid a stopping clock once a device is missing and the matching root port is disabled. Instead set the mapping to 'PCIE_CLK_FREE' to have a free running clock. In addition, use the defined constant 'PCIE_CLK_NOTUSED' instead of the value 0xFF to disable the CLKREQ-feature and unused clocks. Change-Id: I2beea76ff8fefd79f476bef343d13495b45cdfcf Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb 1 file changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/58740/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/58740 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2beea76ff8fefd79f476bef343d13495b45cdfcf Gerrit-Change-Number: 58740 Gerrit-PatchSet: 3 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/siemens/mc_ehl1: Clean up PCIe root port settings in devicetree
by Werner Zeh (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Paul Menzel, Werner Zeh. Hello build bot (Jenkins), Mario Scheithauer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58568 to look at the new patch set (#3). Change subject: mb/siemens/mc_ehl1: Clean up PCIe root port settings in devicetree ...................................................................... mb/siemens/mc_ehl1: Clean up PCIe root port settings in devicetree PCIe root ports #5 (00:1c.4) and #6 (00:1c.5) are not used on this mainboard and are not routed either, so remove them from the devicetree completely. PCIe root port #7 (00:1c.6) is connected and used. Add the missing settings for L1 substates and latency reporting to disable these features for this port as well. Change-Id: I06f59f0369ffcd958b5fe12bb3c646d37103811f Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb 1 file changed, 2 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/58568/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/58568 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06f59f0369ffcd958b5fe12bb3c646d37103811f Gerrit-Change-Number: 58568 Gerrit-PatchSet: 3 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8186: Add GPIO drivers
by build bot (Jenkins) (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58836 ) Change subject: soc/mediatek/mt8186: Add GPIO drivers ...................................................................... Patch Set 1: (1 comment) File src/soc/mediatek/mt8186/include/soc/gpio.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-131964): https://review.coreboot.org/c/coreboot/+/58836/comment/25edfbd2_4066f51b PS1, Line 21: #define PIN(id, name, flag, bit, base, offset, \ Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/c/coreboot/+/58836 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice342ab94397db8bc0fbbeb8fb5ee7e19de871ee Gerrit-Change-Number: 58836 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 02 Nov 2021 05:49:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/lib: Add FW_CONIFG_SOURCE_VPD
by Wonkyu Kim (Code Review) 02 Nov '21

02 Nov '21

Wonkyu Kim has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/58839 ) Change subject: src/lib: Add FW_CONIFG_SOURCE_VPD ...................................................................... src/lib: Add FW_CONIFG_SOURCE_VPD Read fw_config value from VPD. This new option can be used where chrome EC is not supported like pre-silicon platform and fw_config can be updated by VPD tool in OS. TEST= boot to OS and read fw_config from vpd 1. Boot to OS 2. Write "fw_config" in VPD ex)vpd -i "RW_VPD" -s "fw_config"="1" 3. reboot and check fw_config value from coreboot log Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: I4df7d5612e18957416a40ab854fa63c8b11b4216 --- M src/Kconfig M src/lib/fw_config.c 2 files changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/58839/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58839 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4df7d5612e18957416a40ab854fa63c8b11b4216 Gerrit-Change-Number: 58839 Gerrit-PatchSet: 2 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/lib: Support fallback option for fw_config
by Wonkyu Kim (Code Review) 02 Nov '21

02 Nov '21

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58833 to look at the new patch set (#3). Change subject: src/lib: Support fallback option for fw_config ...................................................................... src/lib: Support fallback option for fw_config To support both non-chrome EC platform and chrome EC platform in single coreboot binary, need to support fallback option. Make reading fw_config from CBI and support other options as fallback options and support backward compatiblity to support only one option as before. TEST=select both configs and check fallback behavior. 1. select both FW_CONFIG_SOURCE_CHROMEEC_CBI and FW_CONFIG_SOURCE_CBFS 2. check Coreboot tries to read CBI and CBFS Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: I215c13a4fcb9dc3b94f73c770e704d4e353e9cff --- M src/Kconfig M src/lib/fw_config.c 2 files changed, 29 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/58833/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/58833 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I215c13a4fcb9dc3b94f73c770e704d4e353e9cff Gerrit-Change-Number: 58833 Gerrit-PatchSet: 3 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8186: Add a stub implementation of the MT8186 SoC
by Rex-BC Chen (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yu-Ping Wu, Felix Held. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58640 ) Change subject: soc/mediatek/mt8186: Add a stub implementation of the MT8186 SoC ...................................................................... Patch Set 8: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/58640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I579f79c15f4bf5e1daf6b35c70cfd00a985a0b81 Gerrit-Change-Number: 58640 Gerrit-PatchSet: 8 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 02 Nov 2021 05:35:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/lib: Add FW_CONIFG_SOURCE_VPD
by Wonkyu Kim (Code Review) 02 Nov '21

02 Nov '21

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58839 ) Change subject: src/lib: Add FW_CONIFG_SOURCE_VPD ...................................................................... src/lib: Add FW_CONIFG_SOURCE_VPD Read fw_config value from VPD. This new option can be used where chrome EC is not supported like pre-silicon platform and fw_config can be updated by VPD tool in OS. TEST= boot to OS and read fw_config from vpd 1. Boot to OS 2. Write "fw_config" in VPD ex)vpd -i "RW_VPD" -s "fw_config"="1" 3. reboot and check fw_config value from coreboot log Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: I4df7d5612e18957416a40ab854fa63c8b11b4216 --- M src/Kconfig M src/lib/fw_config.c 2 files changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/58839/1 diff --git a/src/Kconfig b/src/Kconfig index 797819b..a6efceb 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -416,6 +416,16 @@ local image to preempt the mainboard selected source and and can be used as FW_CONFIG_SOURCE_CHROMEEC_CBI fallback option. +config FW_CONFIG_SOURCE_VPD + bool "Obtain Firmware Configuration value from VPD" + depends on FW_CONFIG + default n + help + With this option enabled coreboot will look for the 32bit firmware + configuration value in VPD key name "fw_config". This option will + override other sources and allow the local image to preempt the mainboard + selected source and can be used for other FW_CONFIG_SOURCEs fallback option. + config HAVE_RAMPAYLOAD bool diff --git a/src/lib/fw_config.c b/src/lib/fw_config.c index da4269a..71237ac 100644 --- a/src/lib/fw_config.c +++ b/src/lib/fw_config.c @@ -11,6 +11,7 @@ #include <lib.h> #include <stdbool.h> #include <stdint.h> +#include <drivers/vpd/vpd.h> uint64_t fw_config_get(void) { @@ -46,6 +47,19 @@ fw_config_value); } + if (CONFIG(FW_CONFIG_SOURCE_VPD) && fw_config_value == UNDEFINED_FW_CONFIG) { + int32_t vpd_value; + if (vpd_get_int("fw_config", VPD_RW_THEN_RO, (int *const) &vpd_value)) { + fw_config_value = vpd_value; + printk(BIOS_INFO, "FW_CONFIG value from VPD is 0x%" PRIx64 "\n", + fw_config_value); + } else { + printk(BIOS_WARNING, "%s: Could not get fw_config from vpd\n", + __func__); + fw_config_value = UNDEFINED_FW_CONFIG; + } + } + return fw_config_value; } -- To view, visit https://review.coreboot.org/c/coreboot/+/58839 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4df7d5612e18957416a40ab854fa63c8b11b4216 Gerrit-Change-Number: 58839 Gerrit-PatchSet: 1 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/corsola: Add NOR-Flash support
by Rex-BC Chen (Code Review) 02 Nov '21

02 Nov '21

Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58838 ) Change subject: mb/google/corsola: Add NOR-Flash support ...................................................................... mb/google/corsola: Add NOR-Flash support Add NOR-Flash drivers to pass verification of flash at verstage. TEST=boot to romstage BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Iee3dd336632b0cf998f5f7c1d118e01e8270e815 --- M src/mainboard/google/corsola/Kconfig M src/mainboard/google/corsola/bootblock.c 2 files changed, 31 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/58838/1 diff --git a/src/mainboard/google/corsola/Kconfig b/src/mainboard/google/corsola/Kconfig index 8b38d2b..bfdc8ee 100644 --- a/src/mainboard/google/corsola/Kconfig +++ b/src/mainboard/google/corsola/Kconfig @@ -22,4 +22,8 @@ config MAINBOARD_PART_NUMBER string default "Corsola" if BOARD_GOOGLE_CORSOLA + +config BOOT_DEVICE_SPI_FLASH_BUS + int + default 7 endif diff --git a/src/mainboard/google/corsola/bootblock.c b/src/mainboard/google/corsola/bootblock.c index 99947c0..81af529 100644 --- a/src/mainboard/google/corsola/bootblock.c +++ b/src/mainboard/google/corsola/bootblock.c @@ -2,7 +2,34 @@ #include <bootblock_common.h> #include <device/mmio.h> +#include <soc/gpio.h> +struct pad_func { + gpio_t gpio; + u8 func; +}; + +#define PAD_FUNC(name, func) {GPIO(name), PAD_##name##_FUNC_##func} + +static void nor_set_gpio_pinmux(void) +{ + const struct pad_func *ptr = NULL; + + /* GPIO 36 ~ 39 */ + struct pad_func nor_pinmux[] = { + PAD_FUNC(SPI0_CLK, SPINOR_CK), + PAD_FUNC(SPI0_CSB, SPINOR_CS), + PAD_FUNC(SPI0_MO, SPINOR_IO0), + PAD_FUNC(SPI0_MI, SPINOR_IO1), + }; + + ptr = nor_pinmux; + for (size_t i = 0; i < ARRAY_SIZE(nor_pinmux); i++) { + gpio_set_pull(nor_pinmux[i].gpio, GPIO_PULL_ENABLE, GPIO_PULL_UP); + gpio_set_mode(nor_pinmux[i].gpio, ptr[i].func); + } +} void bootblock_mainboard_init(void) { + nor_set_gpio_pinmux(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/58838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee3dd336632b0cf998f5f7c1d118e01e8270e815 Gerrit-Change-Number: 58838 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2021