coreboot-gerrit August 2020

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Change in ...coreboot[master]: WIP: update blobs repo submodule
by Martin Kepplinger (Code Review) 06 Aug '23

06 Aug '23

Martin Kepplinger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33197 Change subject: WIP: update blobs repo submodule ...................................................................... WIP: update blobs repo submodule Change-Id: I12fc447ee78d986f93f4c39bac282cb6a9a73814 Signed-off-by: Martin Kepplinger <martink(a)posteo.de> --- M 3rdparty/blobs 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/33197/1 diff --git a/3rdparty/blobs b/3rdparty/blobs index ca6cfcd..8147d6b 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit ca6cfcdbe1cdeb38c2622ee2e5236cc4657e3377 +Subproject commit 8147d6b601050f6fac6f4c5ccfd8cdadbe3507de -- To view, visit https://review.coreboot.org/c/coreboot/+/33197 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12fc447ee78d986f93f4c39bac282cb6a9a73814 Gerrit-Change-Number: 33197 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Kepplinger <martink(a)posteo.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: [NOTFORMERGE]3rdparty/blobs: Update submodule pointer
by Arthur Heymans (Code Review) 06 Aug '23

06 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43902 ) Change subject: [NOTFORMERGE]3rdparty/blobs: Update submodule pointer ...................................................................... [NOTFORMERGE]3rdparty/blobs: Update submodule pointer Use microcode for Intel family 6, model 0x37, stepping 8 from 3rdparty/intel-microcode as this a more recent version. Change-Id: Id886c5d71cc8b8a4f2caa9bea847cf6cfba5660b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M 3rdparty/blobs M src/soc/intel/baytrail/Makefile.inc 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/43902/1 diff --git a/3rdparty/blobs b/3rdparty/blobs index bbe5d99..2fbe86c 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit bbe5d99780d2d085e92d9bae2c0f7b6787419d72 +Subproject commit 2fbe86cf5e298ba189b418196ec1c522d6dbc49a diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 451f29e..25cd261 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -62,7 +62,7 @@ postcar-y += ../../../cpu/intel/car/non-evict/exit_car.S cpu_microcode_bins += 3rdparty/blobs/soc/intel/baytrail/microcode.bin \ - 3rdparty/intel-microcode/intel-ucode/06-37-09 + 3rdparty/intel-microcode/intel-ucode/06-37-* CPPFLAGS_common += -Isrc/soc/intel/baytrail/include -- To view, visit https://review.coreboot.org/c/coreboot/+/43902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id886c5d71cc8b8a4f2caa9bea847cf6cfba5660b Gerrit-Change-Number: 43902 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: payloads/external/Makefile.inc: Clean up targets
by Arthur Heymans (Code Review) 04 Aug '23

04 Aug '23

Hello Martin Roth, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/36460 to review the following change. Change subject: payloads/external/Makefile.inc: Clean up targets ...................................................................... payloads/external/Makefile.inc: Clean up targets - Combine the short target name with the filename. - All targets depend on top level dotconfig. - Payload targets depend on their payload .config. - Add .PHONY target for the short target names. - Add additional short target names grub, uboot, and memtest. - Remove reversed dependencies of config files on the output. - Set SeaBIOS vgabios target at same level as main SeaBIOS target to prevent rebuilds because of the vbios being included. This fixes an issue with SeaBIOS and Filo rebuilding every time. Change-Id: I917c4cce46461ed15212a86dc01b703f818aba23 Signed-off-by: Martin Roth <martinroth(a)google.com> Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M payloads/external/Makefile.inc 1 file changed, 18 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/36460/1 diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index f6417fd..cdc5552 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -17,14 +17,20 @@ ## ###################################################################### + +SEABIOS_DIR=payloads/external/SeaBIOS/seabios +SEABIOS_OUT=$(SEABIOS_DIR)/out +FILO_DIR=payloads/external/FILO/filo +FILO_OUT=$(FILO_DIR)/build + # set up payload config and version files for later inclusion ifeq ($(CONFIG_PAYLOAD_SEABIOS),y) -PAYLOAD_CONFIG=payloads/external/SeaBIOS/seabios/.config -PAYLOAD_VERSION=payloads/external/SeaBIOS/seabios/out/autoversion.h +PAYLOAD_CONFIG=$(SEABIOS_DIR)/.config +PAYLOAD_VERSION=$(SEABIOS_OUT)/autoversion.h endif ifeq ($(CONFIG_PAYLOAD_FILO),y) -PAYLOAD_CONFIG=payloads/external/FILO/filo/.config -PAYLOAD_VERSION=payloads/external/FILO/filo/build/version.h +PAYLOAD_CONFIG=$(FILO_DIR)/.config +PAYLOAD_VERSION=$(FILO_OUT)/version.h endif ifeq ($(CONFIG_PAYLOAD_DEPTHCHARGE),y) PAYLOAD_CONFIG=payloads/external/depthcharge/depthcharge/.config @@ -75,10 +81,12 @@ etc/grub.cfg-type := raw etc/grub.cfg-required := the GRUB runtime configuration file ($(CONFIG_GRUB2_RUNTIME_CONFIG_FILE)) +.PHONY: seabios depthcharge grub2 grub tint memtest u-boot uboot ipxe + # SeaBIOS SEABIOS_CC_OFFSET=$(if $(filter %ccache,$(HOSTCC)),2,1) -payloads/external/SeaBIOS/seabios/out/bios.bin.elf seabios: $(DOTCONFIG) +$(SEABIOS_OUT)/vgabios.bin $(SEABIOS_OUT)/bios.bin.elf seabios: $(DOTCONFIG) $(PAYLOAD_CONFIG) $(MAKE) -C payloads/external/SeaBIOS \ HOSTCC="$(HOSTCC)" \ CC=$(word $(SEABIOS_CC_OFFSET),$(CC_x86_32)) \ @@ -104,10 +112,6 @@ CONFIG_ENABLE_HSUART=$(CONFIG_ENABLE_HSUART) \ CONFIG_CONSOLE_UART_BASE_ADDRESS=$(CONFIG_CONSOLE_UART_BASE_ADDRESS) -payloads/external/SeaBIOS/seabios/out/vgabios.bin: seabios -payloads/external/SeaBIOS/seabios/.config: payloads/external/SeaBIOS/seabios/out/bios.bin.elf -payloads/external/SeaBIOS/seabios/out/autoversion.h: payloads/external/SeaBIOS/seabios/out/bios.bin.elf - # add a SeaBIOS bootorder file ifneq ($(strip $(CONFIG_SEABIOS_BOOTORDER_FILE)),) cbfs-files-y += bootorder @@ -117,7 +121,7 @@ # Depthcharge -payloads/external/depthcharge/depthcharge/build/depthcharge.elf depthcharge: $(DOTCONFIG) $(CBFSTOOL) +payloads/external/depthcharge/depthcharge/build/depthcharge.elf depthcharge: $(DOTCONFIG) $(CBFSTOOL) $(PAYLOAD_CONFIG) $(MAKE) -C payloads/external/depthcharge \ BOARD=$(BOARD) \ MFLAGS= MAKEFLAGS= \ @@ -153,7 +157,7 @@ # FILO -filo: +$(FILO_OUT)/filo.elf filo: $(DOTCONFIG) $(PAYLOAD_CONFIG) $(MAKE) -C payloads/external/FILO \ HOSTCC="$(HOSTCC)" \ CC="$(CC_x86_32)" LD="$(LD_x86_32)" OBJDUMP="$(OBJDUMP_x86_32)" \ @@ -161,13 +165,9 @@ CONFIG_FILO_MASTER=$(CONFIG_FILO_MASTER) \ CONFIG_FILO_STABLE=$(CONFIG_FILO_STABLE) -payloads/external/FILO/filo/build/filo.elf: filo -payloads/external/FILO/filo/.config: filo -payloads/external/FILO/filo/build/version.h: filo - # Grub -grub2: $(obj)/config.h +payloads/external/GRUB2/grub2/build/default_payload.elf grub2 grub: $(DOTCONFIG) $(MAKE) -C payloads/external/GRUB2 \ HOSTCC="$(HOSTCC)" \ CC="$(CC_x86_32)" LD="$(LD_x86_32)" \ @@ -179,11 +179,9 @@ CONFIG_GRUB2_REVISION_ID=$(CONFIG_GRUB2_REVISION_ID) \ CONFIG_GRUB2_EXTRA_MODULES=$(CONFIG_GRUB2_EXTRA_MODULES) -payloads/external/GRUB2/grub2/build/default_payload.elf: grub2 - # U-Boot -payloads/external/U-Boot/u-boot/u-boot-dtb.bin u-boot: $(DOTCONFIG) +payloads/external/U-Boot/u-boot/u-boot-dtb.bin u-boot uboot: $(DOTCONFIG) $(MAKE) -C payloads/external/U-Boot \ CONFIG_UBOOT_MASTER=$(CONFIG_UBOOT_MASTER) \ CONFIG_UBOOT_STABLE=$(CONFIG_UBOOT_STABLE) @@ -211,7 +209,7 @@ SERIAL_BAUD_RATE=$(CONFIG_TTYS0_BAUD) endif -payloads/external/Memtest86Plus/memtest86plus/memtest: $(DOTCONFIG) +payloads/external/Memtest86Plus/memtest86plus/memtest memtest: $(DOTCONFIG) $(MAKE) -C payloads/external/Memtest86Plus all \ CC="$(CC_x86_32)" \ LD="$(LD_x86_32)" \ -- To view, visit https://review.coreboot.org/c/coreboot/+/36460 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I917c4cce46461ed15212a86dc01b703f818aba23 Gerrit-Change-Number: 36460 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: vc/amd/agesa/[...]/Proc/Mem: Fix uninitialized scalar variable
by Name of user not set (Code Review) 03 Aug '23

03 Aug '23

awokd(a)danwin1210.me has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38495 ) Change subject: vc/amd/agesa/[...]/Proc/Mem: Fix uninitialized scalar variable ...................................................................... vc/amd/agesa/[...]/Proc/Mem: Fix uninitialized scalar variable FinalRxEnCycle[ByteLane] does not get set in mtthrcSeedTrain.c if (((UINT16) FinalRxEnCycle[ByteLane] >= NBPtr->MinRxEnSeedGross) && \ ((UINT16) FinalRxEnCycle[ByteLane] <= NBPtr->MaxRxEnSeedTotal)) evaluates FALSE. According to Coverity, this could result in cases where RxEnDlyTargetValue[ByteLane] = FinalRxEnCycle[ByteLane] is used with an uninitialized value. Move the FinalRxEnCycle[ByteLane] initial assignment up a line so it gets initialized regardless. Tested on Lenovo G505s. Change-Id: Id1d3580c8915ba31e87059851fec2ae4b8b0e1da Signed-off-by: Joe Moore <awokd(a)danwin1210.me> Found-by: Coverity CID 1370599 --- M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/38495/1 diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c index 991667b..d21c246 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c @@ -504,8 +504,8 @@ for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { if (RxEnDlyTargetFound[ByteLane] == FALSE) { MemClkCycle = (UINT8) (FailTestRxEnDly[ByteLane] >> 5); + FinalRxEnCycle[ByteLane] = PassTestRxEnDly[ByteLane] - 0x10; if (RxEnMemClkTested[ByteLane][MemClkCycle] ? RxEnMemClkSt[ByteLane][MemClkCycle] == TRUE : (TechPtr->ByteLaneError[ByteLane] && DlyWrittenToReg[ByteLane])) { - FinalRxEnCycle[ByteLane] = PassTestRxEnDly[ByteLane] - 0x10; if (((UINT16) FinalRxEnCycle[ByteLane] >= NBPtr->MinRxEnSeedGross) && ((UINT16) FinalRxEnCycle[ByteLane] <= NBPtr->MaxRxEnSeedTotal)) { // Since FailTestRxEnDly, we can set FinalRxEnCycle MemTRdPosRxEnSeedSetDly3 (TechPtr, (UINT16) FinalRxEnCycle[ByteLane], ByteLane); diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c index 1446f3e..7ea7c56 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c @@ -505,8 +505,8 @@ for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { if (RxEnDlyTargetFound[ByteLane] == FALSE) { MemClkCycle = (UINT8) (FailTestRxEnDly[ByteLane] >> 5); + FinalRxEnCycle[ByteLane] = PassTestRxEnDly[ByteLane] - 0x10; if (RxEnMemClkTested[ByteLane][MemClkCycle] ? RxEnMemClkSt[ByteLane][MemClkCycle] == TRUE : (TechPtr->ByteLaneError[ByteLane] && DlyWrittenToReg[ByteLane])) { - FinalRxEnCycle[ByteLane] = PassTestRxEnDly[ByteLane] - 0x10; if (((UINT16) FinalRxEnCycle[ByteLane] >= NBPtr->MinRxEnSeedGross) && ((UINT16) FinalRxEnCycle[ByteLane] <= NBPtr->MaxRxEnSeedTotal)) { // Since FailTestRxEnDly, we can set FinalRxEnCycle MemTRdPosRxEnSeedSetDly3 (TechPtr, (UINT16) FinalRxEnCycle[ByteLane], ByteLane); -- To view, visit https://review.coreboot.org/c/coreboot/+/38495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1d3580c8915ba31e87059851fec2ae4b8b0e1da Gerrit-Change-Number: 38495 Gerrit-PatchSet: 1 Gerrit-Owner: awokd(a)danwin1210.me Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/pcengines/apu2: describe serial ports in ACPI
by Michał Żygowski (Code Review) 03 Aug '23

03 Aug '23

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32989 Change subject: mb/pcengines/apu2: describe serial ports in ACPI ...................................................................... mb/pcengines/apu2: describe serial ports in ACPI FreeBSD users had to manually configure serial ports on their installations. Defining serial ports in ACPI save that effort. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I0de4172a1884abbe9d625060a9045c9d71469e27 --- A src/mainboard/pcengines/apu2/acpi/superio.asl M src/mainboard/pcengines/apu2/dsdt.asl 2 files changed, 68 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/32989/1 diff --git a/src/mainboard/pcengines/apu2/acpi/superio.asl b/src/mainboard/pcengines/apu2/acpi/superio.asl new file mode 100644 index 0000000..c61e3d7 --- /dev/null +++ b/src/mainboard/pcengines/apu2/acpi/superio.asl @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 PC Engines Gmbh + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.LIBR) { + + Device (COM1) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 1) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x03F8, 0x3F8, 0x08, 0x08) + IRQNoFlags () {4} + }) + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0, 0) { + IO (Decode16, 0x03F8, 0x3F8, 0x08, 0x08) + IRQNoFlags () {4} + } + EndDependentFn () + }) + } + + Device (COM2) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 2) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x02F8, 0x2F8, 0x08, 0x08) + IRQNoFlags () {3} + }) + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0, 0) { + IO (Decode16, 0x02F8, 0x2F8, 0x08, 0x08) + IRQNoFlags () {3} + } + EndDependentFn () + }) + } +} \ No newline at end of file diff --git a/src/mainboard/pcengines/apu2/dsdt.asl b/src/mainboard/pcengines/apu2/dsdt.asl index 3bf0ed6..409f03d 100644 --- a/src/mainboard/pcengines/apu2/dsdt.asl +++ b/src/mainboard/pcengines/apu2/dsdt.asl @@ -81,5 +81,8 @@ /* Define the System Indicators for the platform */ #include "acpi/si.asl" + + /* Super IO devices (COM ports) */ + #include "acpi/superio.asl" } /* End of ASL file */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0de4172a1884abbe9d625060a9045c9d71469e27 Gerrit-Change-Number: 32989 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in ...libgfxinit[master]: [WIP] gma: Add Gemini Lake support
by Nico Huber (Code Review) 02 Aug '23

02 Aug '23

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/31611 Change subject: [WIP] gma: Add Gemini Lake support ...................................................................... [WIP] gma: Add Gemini Lake support Change-Id: I84347130fc3fcaf33d9f3d84fab47c67899c792d Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M common/Makefile.inc M common/broxton/hw-gfx-gma-ddi_phy.ads M common/broxton/hw-gfx-gma-plls.adb M common/broxton/hw-gfx-gma-power_and_clocks.adb M common/hw-gfx-gma-config.ads.template M common/hw-gfx-gma-registers.ads M common/hw-gfx-gma.ads R configs/apollolake C configs/geminilake 9 files changed, 109 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/11/31611/1 diff --git a/common/Makefile.inc b/common/Makefile.inc index 61955eb..cfb2dfa 100644 --- a/common/Makefile.inc +++ b/common/Makefile.inc @@ -68,7 +68,7 @@ subdirs-y += ironlake else ifneq ($(filter Haswell Broadwell,$(CONFIG_GFX_GMA_CPU)),) subdirs-y += haswell_shared haswell -else ifneq ($(filter Broxton,$(CONFIG_GFX_GMA_CPU)),) +else ifneq ($(filter Apollolake Geminilake,$(CONFIG_GFX_GMA_CPU)),) subdirs-y += haswell_shared broxton else ifneq ($(filter Skylake Kabylake,$(CONFIG_GFX_GMA_CPU)),) subdirs-y += haswell_shared skylake diff --git a/common/broxton/hw-gfx-gma-ddi_phy.ads b/common/broxton/hw-gfx-gma-ddi_phy.ads index fc6cacf..e6301bf 100644 --- a/common/broxton/hw-gfx-gma-ddi_phy.ads +++ b/common/broxton/hw-gfx-gma-ddi_phy.ads @@ -16,7 +16,7 @@ private package HW.GFX.GMA.DDI_Phy is - type T is (BC, A); + type T is (BC, A, C); procedure Power_On (Phy : T); procedure Power_Off (Phy : T); diff --git a/common/broxton/hw-gfx-gma-plls.adb b/common/broxton/hw-gfx-gma-plls.adb index 087ff12..f7ecc05 100644 --- a/common/broxton/hw-gfx-gma-plls.adb +++ b/common/broxton/hw-gfx-gma-plls.adb @@ -170,6 +170,8 @@ PLL_10 : Registers_Index; PCS_DW12_LN01 : Registers_Index; PCS_DW12_GRP : Registers_Index; + TX_DW5_LN0 : Registers_Index; + TX_DW5_GRP : Registers_Index; end record; type Port_PLL_Array is array (Valid_PLLs) of Port_PLL_Regs; @@ -187,7 +189,9 @@ PLL_9 => BXT_PORT_PLL_9_A, PLL_10 => BXT_PORT_PLL_10_A, PCS_DW12_LN01 => BXT_PORT_PCS_DW12_01_A, - PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_A), + PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_A, + TX_DW5_LN0 => BXT_PORT_TX_DW5_LN0_A, + TX_DW5_GRP => BXT_PORT_TX_DW5_GRP_A), DPLL_B => (PLL_ENABLE => BXT_PORT_PLL_ENABLE_B, PLL_EBB_0 => BXT_PORT_PLL_EBB_0_B, @@ -201,7 +205,9 @@ PLL_9 => BXT_PORT_PLL_9_B, PLL_10 => BXT_PORT_PLL_10_B, PCS_DW12_LN01 => BXT_PORT_PCS_DW12_01_B, - PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_B), + PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_B, + TX_DW5_LN0 => BXT_PORT_TX_DW5_LN0_B, + TX_DW5_GRP => BXT_PORT_TX_DW5_GRP_B), DPLL_C => (PLL_ENABLE => BXT_PORT_PLL_ENABLE_C, PLL_EBB_0 => BXT_PORT_PLL_EBB_0_C, @@ -215,11 +221,15 @@ PLL_9 => BXT_PORT_PLL_9_C, PLL_10 => BXT_PORT_PLL_10_C, PCS_DW12_LN01 => BXT_PORT_PCS_DW12_01_C, - PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_C)); + PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_C, + TX_DW5_LN0 => BXT_PORT_TX_DW5_LN0_C, + TX_DW5_GRP => BXT_PORT_TX_DW5_GRP_C)); PORT_PLL_ENABLE : constant := 1 * 2 ** 31; PORT_PLL_ENABLE_LOCK : constant := 1 * 2 ** 30; PORT_PLL_ENABLE_REF_SEL : constant := 1 * 2 ** 27; + PORT_PLL_POWER_ENABLE : constant := 1 * 2 ** 26; + PORT_PLL_POWER_STATE : constant := 1 * 2 ** 25; PORT_PLL_EBB0_P1_SHIFT : constant := 13; PORT_PLL_EBB0_P1_MASK : constant := 16#07# * 2 ** 13; @@ -336,8 +346,17 @@ begin pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); - Set_Mask (PORT (P).PLL_ENABLE, PORT_PLL_ENABLE_REF_SEL); -- non-SSC ref - Unset_Mask (PORT (P).PLL_EBB_4, PORT_PLL_EBB4_10BIT_CLK_ENABLE); + Set_Mask (PORT (P).PLL_ENABLE, PORT_PLL_ENABLE_REF_SEL); -- non-SSC ref + + if Config.Has_Port_PLL_Pwr_En then + Set_Mask (PORT (P).PLL_ENABLE, PORT_PLL_POWER_ENABLE); + Wait_Set_Mask + (Register => PORT (P).PLL_ENABLE, + Mask => PORT_PLL_POWER_STATE, + TOut_MS => 1); -- 200us + end if; + + Unset_Mask (PORT (P).PLL_EBB_4, PORT_PLL_EBB4_10BIT_CLK_ENABLE); Unset_And_Set_Mask (Register => PORT (P).PLL_EBB_0, @@ -388,7 +407,16 @@ Wait_Set_Mask (Register => PORT (P).PLL_ENABLE, Mask => PORT_PLL_ENABLE_LOCK, - TOut_MS => 1); -- 100us + TOut_MS => 1); -- 200us + + if (Config.Has_DCC_Delay_Range) then + declare + Delay_Range : Word32; + begin + Read (PORT (P).DW5_LN0, Delay_Range); + Delay_Range := Delay_Range or PORT_TX_DW5_DCC_DELAY_RANGE_2; + Write (PORT (P).DW5_GRP, Delay_Range); + end if; Read (PORT (P).PCS_DW12_LN01, PCS); PCS := PCS and not PORT_PCS_LANE_STAGGER_MASK; @@ -471,6 +499,13 @@ begin if PLL in Valid_PLLs then Unset_Mask (PORT (PLL).PLL_ENABLE, PORT_PLL_ENABLE); + if Config.Has_Port_PLL_Pwr_En then + Unset_Mask (PORT (P).PLL_ENABLE, PORT_PLL_POWER_ENABLE); + Wait_Unset_Mask + (Register => PORT (P).PLL_ENABLE, + Mask => PORT_PLL_POWER_STATE, + TOut_MS => 1); -- 200us + end if; end if; end Free; diff --git a/common/broxton/hw-gfx-gma-power_and_clocks.adb b/common/broxton/hw-gfx-gma-power_and_clocks.adb index 8aa9a21..4e3fbc3 100644 --- a/common/broxton/hw-gfx-gma-power_and_clocks.adb +++ b/common/broxton/hw-gfx-gma-power_and_clocks.adb @@ -214,22 +214,12 @@ ---------------------------------------------------------------------------- - CDClk_Ref : constant := 19_200_000; - procedure Set_CDClk (Freq : Frequency_Type) with - Pre => - Freq = CDClk_Ref or Freq = 144_000_000 or Freq = 288_000_000 or - Freq = 384_000_000 or Freq = 576_000_000 or Freq = 624_000_000 + Pre => Config.Valid_CDClk (Freq) is VCO : constant Int64 := - CDClk_Ref * - (if Freq = CDClk_Ref then - 0 - elsif Freq = 624_000_000 then - 65 - else - 60); + Config.Broxton_CDClk_Ref * Config.CDClk_Ratio (Freq); CDCLK_CD2X_Div_Sel : constant Word32 := (case VCO / Freq is -- CDClk = VCO / 2 / Div when 2 => CDCLK_CD2X_DIV_SEL_1, @@ -255,7 +245,8 @@ Unset_And_Set_Mask (Register => BXT_DE_PLL_CTL, Mask_Unset => BXT_DE_PLL_RATIO_MASK, - Mask_Set => Word32 (VCO / CDClk_Ref)); + Mask_Set => (if Freq = Config.Broxton_CDClk_Ref then 0 else + Word32 (VCO / Config.Broxton_CDClk_Ref))); Write (Register => BXT_DE_PLL_ENABLE, Value => BXT_DE_PLL_PLL_ENABLE); @@ -297,7 +288,7 @@ -- Linux' i915 never keeps the PLL disabled but runs it -- at a "ratio" of 0 with CDClk at its reference clock. - Set_CDClk (CDClk_Ref); + Set_CDClk (Config.Broxton_CDClk_Ref); PW_Off (PW1); end Post_All_Off; diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template index 4653ae9..972cfa8 100644 --- a/common/hw-gfx-gma-config.ads.template +++ b/common/hw-gfx-gma-config.ads.template @@ -40,7 +40,8 @@ Has_Internal_Display : constant Boolean := Internal_Display /= None; Internal_Is_EDP : constant Boolean := Internal_Display = DP; Have_DVI_I : constant Boolean := Analog_I2C_Port /= PCH_DAC; - Has_Presence_Straps : constant Boolean := CPU /= Broxton; + Is_Broxton : constant Boolean := CPU in Apollolake..Geminilake; + Has_Presence_Straps : constant Boolean := not Is_Broxton; Is_ULT : constant Boolean := CPU_Var = ULT; Is_ULX : constant Boolean := CPU_Var = ULX; Is_LP : constant Boolean := Is_ULT or Is_ULX; @@ -57,7 +58,7 @@ Has_Pipe_MSA_Misc : constant Boolean := CPU >= Haswell; Has_Pipeconf_Misc : constant Boolean := CPU >= Broadwell; Has_Pipeconf_BPC : constant Boolean := CPU /= Haswell; - Has_Plane_Control : constant Boolean := CPU >= Broxton; + Has_Plane_Control : constant Boolean := CPU >= Apollolake; Has_DSP_Linoff : constant Boolean := CPU <= Ivybridge; Has_PF_Pipe_Select : constant Boolean := CPU in Ivybridge .. Haswell; Has_Cursor_FBC_Control : constant Boolean := CPU >= Ivybridge; @@ -73,7 +74,7 @@ Has_PCH_Panel_Power : constant Boolean := CPU >= Ironlake; ----- PCH/FDI: --------- - Has_PCH : constant Boolean := CPU /= Broxton and CPU /= G45; + Has_PCH : constant Boolean := not Is_Broxton and CPU /= G45; Has_PCH_DAC : constant Boolean := CPU in Ironlake .. Ivybridge or (CPU in Haswell .. Broadwell and not Is_LP); @@ -103,7 +104,9 @@ and Is_LP) or CPU >= Skylake; - Has_DDI_PHYs : constant Boolean := CPU = Broxton; + Has_DDI_PHYs : constant Boolean := Is_Broxton; + Has_Dual_DDI_Phy_BC : constant Boolean := CPU = Apollolake; + Has_Port_PLL_Pwr_En : constant Boolean := CPU = Geminilake; Has_DDI_D : constant Boolean := CPU >= Haswell and not Is_LP and @@ -112,8 +115,8 @@ Has_DDI_D; Has_DDI_Buffer_Trans : constant Boolean := CPU >= Haswell and - CPU /= Broxton; - Has_Low_Voltage_Swing : constant Boolean := CPU >= Broxton; + not Is_Broxton; + Has_Low_Voltage_Swing : constant Boolean := CPU >= Apollolake; Has_Iboost_Config : constant Boolean := CPU >= Skylake; Use_KBL_DDI_Buf_Trans : constant Boolean := CPU = Kabylake; @@ -126,7 +129,7 @@ ----- GMBUS: ----------- Ungate_GMBUS_Unit_Level : constant Boolean := CPU >= Skylake; - GMBUS_Alternative_Pins : constant Boolean := CPU = Broxton; + GMBUS_Alternative_Pins : constant Boolean := Is_Broxton; Has_PCH_GMBUS : constant Boolean := CPU >= Ironlake; ----- Power: ----------- @@ -178,7 +181,8 @@ DP3 => CPU_Var = Normal, Analog => CPU_Var = Normal, others => True), - Broxton => + Apollolake | + Geminilake => (Internal => Config.Internal_Display = DP, DP1 => True, DP2 => True, @@ -234,11 +238,12 @@ Default_DDI_HDMI_Buffer_Translation : constant DDI_HDMI_Buf_Trans_Range := (case CPU is - when Haswell => 6, - when Broadwell => 7, - when Broxton => 8, - when Skylake => 8, - when others => 0); + when Haswell => 6, + when Broadwell => 7, + when Apollolake | + Geminilake => 8, + when Skylake => 8, + when others => 0); ---------------------------------------------------------------------------- @@ -250,7 +255,8 @@ Ivybridge => 400_000_000, when Haswell | Broadwell => (if Is_ULX then 337_500_000 else 450_000_000), - when Broxton => 288_000_000, + when Apollolake => 288_000_000, + when Geminilake => 158_400_000, when Skylake | Kabylake => 337_500_000); @@ -262,13 +268,34 @@ Ivybridge => 125_000_000, when Haswell | Broadwell => (if Is_LP then 24_000_000 else 125_000_000), - when Broxton => Frequency_Type'First, -- none needed + when Apollolake | + Geminilake => Frequency_Type'First, -- none needed when Skylake | Kabylake => 24_000_000); Raw_Clock : Frequency_Type := Default_RawClk_Freq with Part_Of => GMA.Config_State; + Broxton_CDClk_Ref : constant := 19_200_000; + + function Valid_CDClk (Freq : Frequency_Type) return Boolean is + (case CPU is + when Geminilake => + Freq = Broxton_CDClk_Ref or Freq = 79_200_000 or + Freq = 158_400_000 or Freq = 316_800_000, + when Apollolake => + Freq = Broxton_CDClk_Ref or Freq = 144_000_000 or + Freq = 288_000_000 or Freq = 384_000_000 or + Freq = 576_000_000 or Freq = 624_000_000, + when others => + True); + + function CDClk_Ratio (Freq : Frequency_Type) return Int64 is + (case CPU is + when Geminilake => 33, + when Apollolake => if Freq = 624_000_000 then 65 else 60, + when others => 1); + ---------------------------------------------------------------------------- -- Maximum source width with enabled scaler. This only accounts @@ -414,7 +441,8 @@ when Normal => Is_Broadwell (Device_Id), when ULT => Is_Broadwell_U (Device_Id), when ULX => Is_Broadwell_Y (Device_Id)), - when Broxton => (Device_Id and 16#fffe#) = 16#5a84#, + when Apollolake => (Device_Id and 16#fffe#) = 16#5a84#, + when Geminilake => (Device_Id and 16#fffe#) = 16#3184#, when Skylake => (case CPU_Var is when Normal => Is_Skylake (Device_Id), when ULT => Is_Skylake_U (Device_Id), diff --git a/common/hw-gfx-gma-registers.ads b/common/hw-gfx-gma-registers.ads index 1220d1a..b14194b 100644 --- a/common/hw-gfx-gma-registers.ads +++ b/common/hw-gfx-gma-registers.ads @@ -413,6 +413,7 @@ BXT_PORT_TX_DW2_LN0_B, BXT_PORT_TX_DW3_LN0_B, BXT_PORT_TX_DW4_LN0_B, + BXT_PORT_TX_DW5_LN0_B, BXT_PORT_TX_DW14_LN0_B, BXT_PORT_TX_DW14_LN1_B, BXT_PORT_TX_DW14_LN2_B, @@ -422,6 +423,7 @@ BXT_PORT_TX_DW2_LN0_C, BXT_PORT_TX_DW3_LN0_C, BXT_PORT_TX_DW4_LN0_C, + BXT_PORT_TX_DW5_LN0_C, BXT_PORT_TX_DW14_LN0_C, BXT_PORT_TX_DW14_LN1_C, BXT_PORT_TX_DW14_LN2_C, @@ -431,11 +433,13 @@ BXT_PORT_TX_DW2_GRP_B, BXT_PORT_TX_DW3_GRP_B, BXT_PORT_TX_DW4_GRP_B, + BXT_PORT_TX_DW5_GRP_B, BXT_PORT_PCS_DW10_GRP_C, BXT_PORT_PCS_DW12_GRP_C, BXT_PORT_TX_DW2_GRP_C, BXT_PORT_TX_DW3_GRP_C, BXT_PORT_TX_DW4_GRP_C, + BXT_PORT_TX_DW5_GRP_C, BXT_DE_PLL_CTL, HTOTAL_EDP, HBLANK_EDP, @@ -722,6 +726,7 @@ BXT_PORT_TX_DW2_LN0_A, BXT_PORT_TX_DW3_LN0_A, BXT_PORT_TX_DW4_LN0_A, + BXT_PORT_TX_DW5_LN0_A, BXT_PORT_TX_DW14_LN0_A, BXT_PORT_TX_DW14_LN1_A, BXT_PORT_TX_DW14_LN2_A, @@ -730,7 +735,8 @@ BXT_PORT_PCS_DW12_GRP_A, BXT_PORT_TX_DW2_GRP_A, BXT_PORT_TX_DW3_GRP_A, - BXT_PORT_TX_DW4_GRP_A); + BXT_PORT_TX_DW4_GRP_A, + BXT_PORT_TX_DW5_GRP_A); pragma Warnings (GNATprove, Off, "pragma ""KEEP_NAMES"" ignored *(not yet supported)", @@ -1351,6 +1357,7 @@ BXT_PORT_TX_DW2_LN0_A => 16#16_2508# / Register_Width, BXT_PORT_TX_DW3_LN0_A => 16#16_250c# / Register_Width, BXT_PORT_TX_DW4_LN0_A => 16#16_2510# / Register_Width, + BXT_PORT_TX_DW5_LN0_A => 16#16_2514# / Register_Width, BXT_PORT_TX_DW14_LN0_A => 16#16_2538# / Register_Width, BXT_PORT_TX_DW14_LN1_A => 16#16_25b8# / Register_Width, BXT_PORT_TX_DW14_LN2_A => 16#16_2738# / Register_Width, @@ -1358,9 +1365,11 @@ BXT_PORT_TX_DW2_GRP_A => 16#16_2d08# / Register_Width, BXT_PORT_TX_DW3_GRP_A => 16#16_2d0c# / Register_Width, BXT_PORT_TX_DW4_GRP_A => 16#16_2d10# / Register_Width, + BXT_PORT_TX_DW5_GRP_A => 16#16_2d14# / Register_Width, BXT_PORT_TX_DW2_LN0_B => 16#06_c508# / Register_Width, BXT_PORT_TX_DW3_LN0_B => 16#06_c50c# / Register_Width, BXT_PORT_TX_DW4_LN0_B => 16#06_c510# / Register_Width, + BXT_PORT_TX_DW5_LN0_B => 16#06_c514# / Register_Width, BXT_PORT_TX_DW14_LN0_B => 16#06_c538# / Register_Width, BXT_PORT_TX_DW14_LN1_B => 16#06_c5b8# / Register_Width, BXT_PORT_TX_DW14_LN2_B => 16#06_c738# / Register_Width, @@ -1368,9 +1377,11 @@ BXT_PORT_TX_DW2_GRP_B => 16#06_cd08# / Register_Width, BXT_PORT_TX_DW3_GRP_B => 16#06_cd0c# / Register_Width, BXT_PORT_TX_DW4_GRP_B => 16#06_cd10# / Register_Width, + BXT_PORT_TX_DW5_GRP_B => 16#06_cd14# / Register_Width, BXT_PORT_TX_DW2_LN0_C => 16#06_c908# / Register_Width, BXT_PORT_TX_DW3_LN0_C => 16#06_c90c# / Register_Width, BXT_PORT_TX_DW4_LN0_C => 16#06_c910# / Register_Width, + BXT_PORT_TX_DW5_LN0_C => 16#06_c914# / Register_Width, BXT_PORT_TX_DW14_LN0_C => 16#06_c938# / Register_Width, BXT_PORT_TX_DW14_LN1_C => 16#06_c9b8# / Register_Width, BXT_PORT_TX_DW14_LN2_C => 16#06_cb38# / Register_Width, @@ -1378,6 +1389,7 @@ BXT_PORT_TX_DW2_GRP_C => 16#06_cf08# / Register_Width, BXT_PORT_TX_DW3_GRP_C => 16#06_cf0c# / Register_Width, BXT_PORT_TX_DW4_GRP_C => 16#06_cf10# / Register_Width, + BXT_PORT_TX_DW5_GRP_C => 16#06_cf14# / Register_Width, -- Broxton DDI PHY ref registers BXT_PORT_REF_DW3_A => 16#16_218c# / Register_Width, diff --git a/common/hw-gfx-gma.ads b/common/hw-gfx-gma.ads index 7ca0ca1..c282935 100644 --- a/common/hw-gfx-gma.ads +++ b/common/hw-gfx-gma.ads @@ -41,7 +41,8 @@ Ivybridge, Haswell, Broadwell, - Broxton, + Apollolake, + Geminilake, Skylake, Kabylake); diff --git a/configs/broxton b/configs/apollolake similarity index 83% rename from configs/broxton rename to configs/apollolake index b5f1f9a..24e0847 100644 --- a/configs/broxton +++ b/configs/apollolake @@ -1,4 +1,4 @@ -CONFIG_GFX_GMA_CPU = Broxton +CONFIG_GFX_GMA_CPU = Apollolake CONFIG_GFX_GMA_CPU_VARIANT = Normal # N/A CONFIG_GFX_GMA_INTERNAL_PORT = DP CONFIG_GFX_GMA_ANALOG_I2C_PORT = PCH_DAC # N/A diff --git a/configs/broxton b/configs/geminilake similarity index 83% copy from configs/broxton copy to configs/geminilake index b5f1f9a..be34de7 100644 --- a/configs/broxton +++ b/configs/geminilake @@ -1,4 +1,4 @@ -CONFIG_GFX_GMA_CPU = Broxton +CONFIG_GFX_GMA_CPU = Geminilake CONFIG_GFX_GMA_CPU_VARIANT = Normal # N/A CONFIG_GFX_GMA_INTERNAL_PORT = DP CONFIG_GFX_GMA_ANALOG_I2C_PORT = PCH_DAC # N/A -- To view, visit https://review.coreboot.org/c/libgfxinit/+/31611 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I84347130fc3fcaf33d9f3d84fab47c67899c792d Gerrit-Change-Number: 31611 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: mb/system76/lemp9: enable c6dram
by Jeremy Soller (Code Review) 02 Aug '23

02 Aug '23

Jeremy Soller has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43625 ) Change subject: mb/system76/lemp9: enable c6dram ...................................................................... mb/system76/lemp9: enable c6dram Tested on lemp9 Signed-off-by: Jeremy Soller <jeremy(a)system76.com> Change-Id: I9b19ad704096571f2a62f4e39051e52a720f393b --- M src/mainboard/system76/lemp9/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/43625/1 diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb index 3a158ed..8d77aa9 100644 --- a/src/mainboard/system76/lemp9/devicetree.cb +++ b/src/mainboard/system76/lemp9/devicetree.cb @@ -37,7 +37,7 @@ # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "SaGv" = "SaGv_Enabled" - #register "enable_c6dram" = "1" + register "enable_c6dram" = "1" # FSP Silicon (soc/intel/cannonlake/fsp_params.c) # Serial I/O -- To view, visit https://review.coreboot.org/c/coreboot/+/43625 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b19ad704096571f2a62f4e39051e52a720f393b Gerrit-Change-Number: 43625 Gerrit-PatchSet: 1 Gerrit-Owner: Jeremy Soller <jeremy(a)system76.com> Gerrit-MessageType: newchange

3 16

Change in coreboot[master]: [WIP] device/resource_allocator_v4.5: Directly recurse in pass 2 for ...
by Nico Huber (Code Review) 22 Jun '23

22 Jun '23

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41959 ) Change subject: [WIP] device/resource_allocator_v4.5: Directly recurse in pass 2 for each bridge resource ...................................................................... [WIP] device/resource_allocator_v4.5: Directly recurse in pass 2 for each bridge resource Change-Id: I9b31c7242f0cdf747db48203243f0e9ba6643bf4 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/device/resource_allocator_v4.5.c 1 file changed, 40 insertions(+), 61 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/41959/1 diff --git a/src/device/resource_allocator_v4.5.c b/src/device/resource_allocator_v4.5.c index 34e9fdd..96a6503 100644 --- a/src/device/resource_allocator_v4.5.c +++ b/src/device/resource_allocator_v4.5.c @@ -394,6 +394,43 @@ } /* + * Pass 2 of the resource allocator at the bridge level loops through + * all the resources for the bridge and assigns all the base addresses + * of its children's resources of the same type. update_bridge_resource() + * of pass 1 pre-calculated the offsets of these bases inside the bridge + * resource. Now that the bridge resource is allocated, all we have to + * do is to add its final base to these offsets. + * + * Once allocation at the current bridge is complete, resource allocator + * continues walking down the downstream bridges until it hits the leaf + * devices. + */ +static void allocate_bridge_resources(const struct device *bridge, struct resource *bridge_res) +{ + void assign_resource_cb(void *param, struct device *dev, struct resource *res) + { + /* We have to filter the same resources as update_bridge_resource(). */ + if (!res->size || !res->limit) + return; + + assign_resource(res, *(const resource_t *)param + res->base, dev); + + if (res->flags & IORESOURCE_BRIDGE) + allocate_bridge_resources(dev, res); + } + + const unsigned long type_mask = IORESOURCE_TYPE_MASK | IORESOURCE_PREFETCH; + const unsigned long type = bridge_res->flags & type_mask; + struct bus *const bus = bridge->link_list; + + if (!bus) + return; + + /* Run assign_resource_cb() for all downstream resources of the same type. */ + search_bus_resources(bus, type_mask, type, assign_resource_cb, &bridge_res->base); +} + +/* * This is where the actual allocation of resources happens during * pass 2. We construct a list of memory ranges corresponding to the * resource of a given type, then look for the biggest unallocated @@ -433,63 +470,15 @@ } assign_resource(res, base, dev); + + if (res->flags & IORESOURCE_BRIDGE) + allocate_bridge_resources(dev, res); } cleanup_resource_ranges(domain, &ranges, domain_res); } /* - * Pass 2 of the resource allocator at the bridge level loops through - * all the resources for the bridge and assigns all the base addresses - * of its children's resources of the same type. update_bridge_resource() - * of pass 1 pre-calculated the offsets of these bases inside the bridge - * resource. Now that the bridge resource is allocated, all we have to - * do is to add its final base to these offsets. - * - * Once allocation at the current bridge is complete, resource allocator - * continues walking down the downstream bridges until it hits the leaf - * devices. - */ -static void allocate_bridge_resources(const struct device *bridge) -{ - void assign_resource_cb(void *param, struct device *dev, struct resource *res) - { - /* We have to filter the same resources as update_bridge_resource(). */ - if (!res->size || !res->limit) - return; - - assign_resource(res, *(const resource_t *)param + res->base, dev); - } - - const unsigned long type_mask = IORESOURCE_TYPE_MASK | IORESOURCE_PREFETCH; - struct bus *const bus = bridge->link_list; - struct resource *res; - struct device *child; - - for (res = bridge->resource_list; res != NULL; res = res->next) { - if (!res->size) - continue; - - if (!(res->flags & IORESOURCE_BRIDGE)) - continue; - - if (!(res->flags & IORESOURCE_ASSIGNED)) - continue; - - /* Run assign_resource_cb() for all downstream resources of the same type. */ - search_bus_resources(bus, type_mask, res->flags & type_mask, - assign_resource_cb, &res->base); - } - - for (child = bus->children; child != NULL; child = child->sibling) { - if (!dev_has_children(child)) - continue; - - allocate_bridge_resources(child); - } -} - -/* * Pass 2 of resource allocator begins at the domain level. Every domain * has two types of resources - io and mem. For each of these resources, * this function creates a list of memory ranges that can be used for @@ -504,8 +493,6 @@ */ static void allocate_domain_resources(const struct device *domain) { - struct device *child; - /* Resource type I/O */ allocate_toplevel_resources(domain, IORESOURCE_IO); @@ -516,14 +503,6 @@ * on the biggest resource requirement. */ allocate_toplevel_resources(domain, IORESOURCE_MEM); - - for (child = domain->link_list->children; child; child = child->sibling) { - if (!dev_has_children(child)) - continue; - - /* Continue allocation for all downstream bridges. */ - allocate_bridge_resources(child); - } } /* -- To view, visit https://review.coreboot.org/c/coreboot/+/41959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b31c7242f0cdf747db48203243f0e9ba6643bf4 Gerrit-Change-Number: 41959 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: device: Introduce RESOURCE_ALLOCATION_COMPAT
by Nico Huber (Code Review) 22 Jun '23

22 Jun '23

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41958 ) Change subject: device: Introduce RESOURCE_ALLOCATION_COMPAT ...................................................................... device: Introduce RESOURCE_ALLOCATION_COMPAT Add a v3-compatibility mode to the v4.5 allocator. We avoid all space above 4G and then disable all remaining memranges but the biggest. It also forces top-down allocation. Change-Id: I1c8512e4b6264f1967cf7018debdf9cabf11d84f Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/device/Kconfig M src/device/resource_allocator_v4.5.c 2 files changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/41958/1 diff --git a/src/device/Kconfig b/src/device/Kconfig index 35433b0..50e3857 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -825,4 +825,9 @@ bool "Allocate resources from top down" depends on RESOURCE_ALLOCATOR_V4 || RESOURCE_ALLOCATOR_V4_5 +config RESOURCE_ALLOCATION_COMPAT + bool "Resource allocator v3 compatibility mode" + depends on RESOURCE_ALLOCATOR_V4_5 + select RESOURCE_ALLOCATION_TOP_DOWN + endmenu diff --git a/src/device/resource_allocator_v4.5.c b/src/device/resource_allocator_v4.5.c index 4a03a23..34e9fdd 100644 --- a/src/device/resource_allocator_v4.5.c +++ b/src/device/resource_allocator_v4.5.c @@ -350,6 +350,28 @@ avoid_fixed_resources(ranges, domain, mask_match); + if (CONFIG(RESOURCE_ALLOCATION_COMPAT)) { + struct range_entry *r, *biggest = NULL; + + /* Don't allow allocations above 4G. */ + memranges_create_hole(ranges, POWER_OF_2(32), UINT64_MAX - POWER_OF_2(32) + 1); + + /* Set all but the biggest range's tag to 0. */ + memranges_each_entry(r, ranges) { + if (!biggest) { + biggest = r; + continue; + } + + if (range_entry_size(r) > range_entry_size(biggest)) { + range_entry_update_tag(biggest, 0); + biggest = r; + } else { + range_entry_update_tag(r, 0); + } + } + } + print_resource_ranges(domain, ranges); } -- To view, visit https://review.coreboot.org/c/coreboot/+/41958 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c8512e4b6264f1967cf7018debdf9cabf11d84f Gerrit-Change-Number: 41958 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: device: Introduce v4.5 resource allocator
by Nico Huber (Code Review) 22 Jun '23

22 Jun '23

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41956 ) Change subject: device: Introduce v4.5 resource allocator ...................................................................... device: Introduce v4.5 resource allocator This is not a complete rewrite, more an adaptation of the v4 allocator. For the moment, I suggest this for experiments, until we have a better understanding what we require from the resource allocator. It differs mostly in pass 2. Instead of searching memranges for every bridge, we only do that for the top level and finish the calculations of pass 1 at the bridge level. And we don't handle above-4G resources separately. This implies that we need a top-down allocation at the top level to place things above 4G, which will be added in a later commit. Detailed list of functional differences --------------------------------------- Pass 1: * Completely ignore resources with 0 limit. * Don't propagate above-4G flag. Propagation makes it harder to effectively opt-out from 4G, e.g. for boot graphics / network devices. OTOH, this way resources can only be placed above 4G if all resources downstream of a bridge allow it. * Store the calculated `base` offset in the resources (like v3 did). This allows us to skip the largest_resource() walk at the bridge level in pass 2. Pass 2: * No separate handling for above-4G resources. They'll need a top-down mode. * No memranges at the bridge-level. Instead we simply add the offset that was pre-calculated in pass 1 to the allocated `base` of the bridge resource. This lowers the computational complexity of pass 2. But there's likely no measurable impact for our usual, shallow device trees. Beside that, there is some heavy refactoring: All the resource printing is factored out into separate functions. This results in one-liners in the actual program code which hopefully will distract less during reading. Some thin functions are manually inlined where it seems to improve readability, and comments are adapted and re-flown to 72 columns (counting from indentation level). TEST=None, so far. Change-Id: I1c27e89916e6e915d4dfe5435fac53fef768bf37 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/device/Kconfig M src/device/Makefile.inc A src/device/resource_allocator_v4.5.c M src/northbridge/amd/agesa/family14/Kconfig M src/northbridge/amd/agesa/family15tn/Kconfig M src/northbridge/amd/agesa/family16kb/Kconfig M src/northbridge/amd/pi/00630F01/Kconfig M src/northbridge/amd/pi/00660F01/Kconfig M src/northbridge/amd/pi/00730F01/Kconfig 9 files changed, 599 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/41956/1 diff --git a/src/device/Kconfig b/src/device/Kconfig index 79ce77d..ee6fb21 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -793,9 +793,16 @@ I2C controller is not (yet) available. The platform code needs to provide bindings to manually toggle I2C lines. -config RESOURCE_ALLOCATOR_V3 +config DEFAULT_RESOURCE_ALLOCATOR_V3 bool - default n + +choice + prompt "Resource allocator" + default RESOURCE_ALLOCATOR_V3 if DEFAULT_RESOURCE_ALLOCATOR_V3 + default RESOURCE_ALLOCATOR_V4 + +config RESOURCE_ALLOCATOR_V3 + bool "v3 (deprecated)" help This config option enables resource allocator v3 which performs top down allocation of resources in a single MMIO window. This is the @@ -803,12 +810,15 @@ chipsets are fixed. DO NOT USE THIS FOR ANY NEW CHIPSETS! config RESOURCE_ALLOCATOR_V4 - bool - default n if RESOURCE_ALLOCATOR_V3 - default y if !RESOURCE_ALLOCATOR_V3 + bool "v4" help This config option enables resource allocator v4 which uses multiple ranges for allocating resources. This allows allocation of resources above 4G boundary as well. +config RESOURCE_ALLOCATOR_V4_5 + bool "v4.5 (experimental)" + +endchoice + endmenu diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc index 2e62d42..1a31c3c 100644 --- a/src/device/Makefile.inc +++ b/src/device/Makefile.inc @@ -62,3 +62,4 @@ ramstage-y += resource_allocator_common.c ramstage-$(CONFIG_RESOURCE_ALLOCATOR_V3) += resource_allocator_v3.c ramstage-$(CONFIG_RESOURCE_ALLOCATOR_V4) += resource_allocator_v4.c +ramstage-$(CONFIG_RESOURCE_ALLOCATOR_V4_5) += resource_allocator_v4.5.c diff --git a/src/device/resource_allocator_v4.5.c b/src/device/resource_allocator_v4.5.c new file mode 100644 index 0000000..6b9e712 --- /dev/null +++ b/src/device/resource_allocator_v4.5.c @@ -0,0 +1,577 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <commonlib/helpers.h> +#include <console/console.h> +#include <device/device.h> +#include <memrange.h> +#include <post.h> + +static const char *resource2str(const struct resource *res) +{ + if (res->flags & IORESOURCE_IO) + return "io"; + if (res->flags & IORESOURCE_PREFETCH) + return "prefmem"; + if (res->flags & IORESOURCE_MEM) + return "mem"; + return "undefined"; +} + +static void print_domain_res(const struct device *dev, + const struct resource *res, const char *suffix) +{ + printk(BIOS_DEBUG, "%s %s: base: %llx size: %llx align: %d gran: %d limit: %llx%s\n", + dev_path(dev), resource2str(res), res->base, res->size, + res->align, res->gran, res->limit, suffix); +} + +#define res_printk(depth, str, ...) printk(BIOS_DEBUG, "%*c"str, depth, ' ', __VA_ARGS__) + +static void print_bridge_res(const struct device *dev, const struct resource *res, + int depth, const char *suffix) +{ + res_printk(depth, "%s %s: size: %llx align: %d gran: %d limit: %llx%s\n", dev_path(dev), + resource2str(res), res->size, res->align, res->gran, res->limit, suffix); +} + +static void print_child_res(const struct device *dev, const struct resource *res, int depth) +{ + res_printk(depth + 1, "%s %02lx * [0x%llx - 0x%llx] %s\n", dev_path(dev), + res->index, res->base, res->base + res->size - 1, resource2str(res)); +} + +static void print_fixed_res(const struct device *dev, + const struct resource *res, const char *prefix) +{ + printk(BIOS_DEBUG, " %s: %s %02lx base %08llx limit %08llx %s (fixed)\n", + prefix, dev_path(dev), res->index, res->base, res->base + res->size - 1, + resource2str(res)); +} + +static void print_assigned_res(const struct device *dev, const struct resource *res) +{ + printk(BIOS_DEBUG, " %s %02lx * [0x%llx - 0x%llx] limit: %llx %s\n", + dev_path(dev), res->index, res->base, res->limit, res->limit, resource2str(res)); +} + +static void print_failed_res(const struct device *dev, const struct resource *res) +{ + printk(BIOS_DEBUG, " %s %02lx * size: 0x%llx limit: %llx %s\n", + dev_path(dev), res->index, res->size, res->limit, resource2str(res)); +} + +static void print_resource_ranges(const struct device *dev, const struct memranges *ranges) +{ + const struct range_entry *r; + + printk(BIOS_INFO, " %s: Resource ranges:\n", dev_path(dev)); + + if (memranges_is_empty(ranges)) + printk(BIOS_INFO, " * EMPTY!!\n"); + + memranges_each_entry(r, ranges) { + printk(BIOS_INFO, " * Base: %llx, Size: %llx, Tag: %lx\n", + range_entry_base(r), range_entry_size(r), range_entry_tag(r)); + } +} + +static bool dev_has_children(const struct device *dev) +{ + const struct bus *bus = dev->link_list; + return bus && bus->children; +} + +static resource_t effective_limit(const struct resource *const res) +{ + /* Always allow bridge resources above 4G. */ + if (res->flags & IORESOURCE_BRIDGE) + return res->limit; + + const resource_t quirk_4g_limit = + res->flags & IORESOURCE_ABOVE_4G ? UINT64_MAX : UINT32_MAX; + return MIN(res->limit, quirk_4g_limit); +} + +/* + * During pass 1, once all the requirements for downstream devices of a + * bridge are gathered, this function calculates the overall resource + * requirement for the bridge. It starts by picking the largest resource + * requirement downstream for the given resource type and works by + * adding requirements in descending order. + * + * Additionally, it takes alignment and limits of the downstream devices + * into consideration and ensures that they get propagated to the bridge + * resource. This is required to guarantee that the upstream bridge/ + * domain honors the limit and alignment requirements for this bridge + * based on the tightest constraints downstream. + * + * Last but not least, it stores the offset inside the bridge resource + * for each child resource in its base field. This simplifies pass 2 + * for resources behind a bridge, as we only have to add offsets to the + * allocated base of the bridge resource. + */ +static void update_bridge_resource(const struct device *bridge, struct resource *bridge_res, + unsigned long type_match, int print_depth) +{ + const unsigned long type_mask = IORESOURCE_TYPE_MASK | IORESOURCE_PREFETCH; + struct bus *bus = bridge->link_list; + const struct device *child; + struct resource *child_res; + resource_t base; + + /* + * `base` keeps track of where the next allocation for child resources + * can take place from within the bridge resource window. Since the + * bridge resource window allocation is not performed yet, we start + * at 0. Base gets updated every time a resource requirement is + * accounted for in the loop below. After scanning all these resources, + * base will indicate the total size requirement for the current bridge + * resource window. + */ + base = 0; + + print_bridge_res(bridge, bridge_res, print_depth, ""); + + child_res = NULL; + while ((child = largest_resource(bus, &child_res, type_mask, type_match))) { + + /* Size 0 resources can be skipped. */ + if (!child_res->size) + continue; + + /* Resources with 0 limit can't be assigned anything. */ + if (!child_res->limit) + continue; + + /* + * Propagate the resource alignment to the bridge resource. The + * condition can only be true for the first (largest) resource. For all + * other child resources, alignment is taken care of by rounding base up. + */ + if (child_res->align > bridge_res->align) + bridge_res->align = child_res->align; + + /* + * Propagate the resource limit to the bridge resource. If a downstream + * device has stricter requirements w.r.t. limits for any resource, that + * constraint needs to be propagated back up to the downstream bridges of + * the domain. This way, the whole bridge resource fulfills the limit. + */ + if (effective_limit(child_res) < bridge_res->limit) + bridge_res->limit = effective_limit(child_res); + + /* + * Alignment value of 0 means that the child resource has no alignment + * requirements and so the base value remains unchanged here. + */ + base = ALIGN_UP(base, POWER_OF_2(child_res->align)); + + /* + * Store the relative offset inside the bridge resource for later + * consumption in allocate_child_resources(). + */ + child_res->base = base; + + print_child_res(child, child_res, print_depth); + + base += child_res->size; + } + + /* + * After all downstream device resources are scanned, `base` represents + * the total size requirement for the current bridge resource window. + * This size needs to be rounded up to the granularity requirement of + * the bridge to ensure that the upstream bridge/domain allocates big + * enough window. + */ + bridge_res->size = ALIGN_UP(base, POWER_OF_2(bridge_res->gran)); + + print_bridge_res(bridge, bridge_res, print_depth, " done"); +} + +/* + * During pass 1, at the bridge level, the resource allocator gathers + * requirements from downstream devices and updates its own resource + * windows for the provided resource type. + */ +static void compute_bridge_resources(const struct device *bridge, unsigned long type_match, + int print_depth) +{ + const unsigned long type_mask = IORESOURCE_TYPE_MASK | IORESOURCE_PREFETCH; + const struct bus *const bus = bridge->link_list; + const struct device *child; + struct resource *res; + + for (res = bridge->resource_list; res != NULL; res = res->next) { + if (!(res->flags & IORESOURCE_BRIDGE)) + continue; + + if ((res->flags & type_mask) != type_match) + continue; + + /* + * Ensure that the resource requirements for all downstream bridges are + * gathered before updating the window for current bridge resource. + */ + for (child = bus->children; child != NULL; child = child->sibling) { + if (!dev_has_children(child)) + continue; + compute_bridge_resources(child, type_match, print_depth + 1); + } + + /* + * Update the window for current bridge resource now that all downstream + * requirements are gathered. + */ + update_bridge_resource(bridge, res, type_match, print_depth); + } +} + +/* + * During pass 1, the resource allocator walks down the entire sub-tree + * of a domain. It gathers resource requirements for every downstream + * bridge by looking at the resource requests of its children. Thus, the + * requirement gathering begins at the leaf devices and is propagated + * back up to the downstream bridges of the domain. + * + * At the domain level, it identifies every downstream bridge and walks + * down that bridge to gather requirements for each resource type i.e. + * i/o, mem and prefmem. Since bridges have separate windows for mem and + * prefmem, requirements for each need to be collected separately. + * + * Domain resource windows are fixed ranges and hence requirement + * gathering does not result in any changes to these fixed ranges. + */ +static void compute_domain_resources(const struct device *domain) +{ + const struct device *child; + const int print_depth = 1; + + if (domain->link_list == NULL) + return; + + for (child = domain->link_list->children; child != NULL; child = child->sibling) { + /* Skip if this is not a bridge or has no children under it. */ + if (!dev_has_children(child)) + continue; + + compute_bridge_resources(child, IORESOURCE_IO, print_depth); + compute_bridge_resources(child, IORESOURCE_MEM, print_depth); + compute_bridge_resources(child, IORESOURCE_MEM | IORESOURCE_PREFETCH, + print_depth); + } +} + +static const struct resource *find_domain_resource(const struct device *domain, + unsigned long type) +{ + const struct resource *res; + + for (res = domain->resource_list; res != NULL; res = res->next) { + if (res->flags & IORESOURCE_FIXED) + continue; + + if ((res->flags & IORESOURCE_TYPE_MASK) == type) + return res; + } + + return NULL; +} + +/* + * Scan the entire tree to identify any fixed resources allocated by + * any device to ensure that the address map for domain resources are + * appropriately updated. + * + * Domains can typically provide a memrange for entire address space. + * So, this function punches holes in the address space for all fixed + * resources that are already defined. Both I/O and normal memory + * resources are added as fixed. Both need to be removed from address + * space where dynamic resource allocations are sourced. + */ +static void avoid_fixed_resources(struct memranges *ranges, const struct device *dev, + unsigned long mask_match) +{ + const struct resource *res; + const struct device *child; + + for (res = dev->resource_list; res != NULL; res = res->next) { + if ((res->flags & mask_match) != mask_match) + continue; + if (!res->size) + continue; + print_fixed_res(dev, res, __func__); + memranges_create_hole(ranges, res->base, res->size); + } + + if (!dev->link_list) + return; + + for (child = dev->link_list->children; child != NULL; child = child->sibling) + avoid_fixed_resources(ranges, child, mask_match); +} + +/* + * This function creates a list of memranges of given type using the + * resource that is provided. It applies additional constraints to + * ensure that the memranges do not overlap any of the fixed resources + * under the domain. The domain typically provides a memrange for the + * entire address space. Thus, it is up to the chipset to add DRAM and + * all other windows which cannot be used for resource allocation as + * fixed resources. + */ +static void setup_resource_ranges(const struct device *const domain, + const struct resource *const res, + const unsigned long type, + struct memranges *const ranges) +{ + const unsigned char alignment = type == IORESOURCE_MEM ? 12 : 0; + const unsigned long mask_match = type | IORESOURCE_FIXED; + + print_domain_res(domain, res, ""); + + memranges_init_empty_with_alignment(ranges, NULL, 0, alignment); + memranges_insert(ranges, res->base, res->limit - res->base + 1, type); + + if (type == IORESOURCE_IO) { + /* + * Don't allow allocations in the VGA I/O range. PCI has special + * cases for that. + */ + memranges_create_hole(ranges, 0x3b0, 0x30); + + /* + * Resource allocator no longer supports the legacy behavior where + * I/O resource allocation is guaranteed to avoid aliases over legacy + * PCI expansion card addresses. + */ + } + + avoid_fixed_resources(ranges, domain, mask_match); + + print_resource_ranges(domain, ranges); +} + +static void cleanup_resource_ranges(const struct device *dev, struct memranges *ranges, + const struct resource *res) +{ + memranges_teardown(ranges); + print_domain_res(dev, res, " done"); +} + +static void assign_resource(struct resource *const res, const resource_t base, + const struct device *const dev) +{ + res->base = base; + res->limit = res->base + res->size - 1; + res->flags |= IORESOURCE_ASSIGNED; + res->flags &= ~IORESOURCE_STORED; + + print_assigned_res(dev, res); +} + +/* + * This is where the actual allocation of resources happens during + * pass 2. We construct a list of memory ranges corresponding to the + * resource of a given type, then look for the biggest unallocated + * resource on the downstream bus. This continues in a descending order + * until all resources of a given type have space allocated within the + * domain's resource window. + */ +static void allocate_toplevel_resources(const struct device *const domain, + const unsigned long type) +{ + const unsigned long type_mask = IORESOURCE_TYPE_MASK; + const struct device *dev; + struct memranges ranges; + struct resource *res; + resource_t base; + + if (!dev_has_children(domain)) + return; + + const struct resource *const domain_res = find_domain_resource(domain, type); + if (!domain_res) + return; + + setup_resource_ranges(domain, domain_res, type, &ranges); + + res = NULL; + while ((dev = largest_resource(domain->link_list, &res, type_mask, type))) { + + if (!res->size) + continue; + + if (!memranges_steal(&ranges, res->limit, res->size, res->align, type, &base)) { + printk(BIOS_ERR, "ERROR: Resource didn't fit!!!\n"); + print_failed_res(dev, res); + continue; + } + + assign_resource(res, base, dev); + } + + cleanup_resource_ranges(domain, &ranges, domain_res); +} + +/* + * Pass 2 of the resource allocator at the bridge level loops through + * all the resources for the bridge and assigns all the base addresses + * of its children's resources of the same type. update_bridge_resource() + * of pass 1 pre-calculated the offsets of these bases inside the bridge + * resource. Now that the bridge resource is allocated, all we have to + * do is to add its final base to these offsets. + * + * Once allocation at the current bridge is complete, resource allocator + * continues walking down the downstream bridges until it hits the leaf + * devices. + */ +static void allocate_bridge_resources(const struct device *bridge) +{ + void assign_resource_cb(void *param, struct device *dev, struct resource *res) + { + /* We have to filter the same resources as update_bridge_resource(). */ + if (!res->size || !res->limit) + return; + + assign_resource(res, *(const resource_t *)param + res->base, dev); + } + + const unsigned long type_mask = IORESOURCE_TYPE_MASK | IORESOURCE_PREFETCH; + struct bus *const bus = bridge->link_list; + struct resource *res; + struct device *child; + + for (res = bridge->resource_list; res != NULL; res = res->next) { + if (!res->size) + continue; + + if (!(res->flags & IORESOURCE_BRIDGE)) + continue; + + if (!(res->flags & IORESOURCE_ASSIGNED)) + continue; + + /* Run assign_resource_cb() for all downstream resources of the same type. */ + search_bus_resources(bus, type_mask, res->flags & type_mask, + assign_resource_cb, &res->base); + } + + for (child = bus->children; child != NULL; child = child->sibling) { + if (!dev_has_children(child)) + continue; + + allocate_bridge_resources(child); + } +} + +/* + * Pass 2 of resource allocator begins at the domain level. Every domain + * has two types of resources - io and mem. For each of these resources, + * this function creates a list of memory ranges that can be used for + * downstream resource allocation. This list is constrained to remove + * any fixed resources in the domain sub-tree of the given resource + * type. It then uses the memory ranges to apply best fit on the + * resource requirements of the downstream devices. + * + * Once resources are allocated to all downstream devices of the domain, + * it walks down each downstream bridge to finish resource assignment + * of its children resources within its own window. + */ +static void allocate_domain_resources(const struct device *domain) +{ + struct device *child; + + /* Resource type I/O */ + allocate_toplevel_resources(domain, IORESOURCE_IO); + + /* + * Resource type Mem: Domain does not distinguish between mem and + * prefmem resources. Thus, the resource allocation at domain level + * considers mem and prefmem together when finding the best fit based + * on the biggest resource requirement. + */ + allocate_toplevel_resources(domain, IORESOURCE_MEM); + + for (child = domain->link_list->children; child; child = child->sibling) { + if (!dev_has_children(child)) + continue; + + /* Continue allocation for all downstream bridges. */ + allocate_bridge_resources(child); + } +} + +/* + * This function forms the guts of the resource allocator. It walks + * through the entire device tree for each domain two times. + * + * Every domain has a fixed set of ranges. These ranges cannot be + * relaxed based on the requirements of the downstream devices. They + * represent the available windows from which resources can be allocated + * to the different devices under the domain. + * + * In order to identify the requirements of downstream devices, resource + * allocator walks in a DFS fashion. It gathers the requirements from + * leaf devices and propagates those back up to their upstream bridges + * until the requirements for all the downstream devices of the domain + * are gathered. This is referred to as pass 1 of the resource allocator. + * + * Once the requirements for all the devices under the domain are + * gathered, the resource allocator walks a second time to allocate + * resources to downstream devices as per the requirements. It always + * picks the biggest resource request as per the type (i/o and mem) to + * allocate space from its fixed window to the immediate downstream + * device of the domain. In order to accomplish best fit for the + * resources, a list of ranges is maintained by each resource type (i/o + * and mem). At the domain level we don't differentiate between mem and + * prefmem. Since they are allocated space from the same window, the + * resource allocator at the domain level ensures that the biggest + * requirement is selected indepedent of the prefetch type. Once the + * resource allocation for all immediate downstream devices is complete + * at the domain level, the resource allocator walks down the subtree + * for each downstream bridge to continue the allocation process at the + * bridge level. Since bridges have either their whole window allocated + * or nothing, we only need to place downstream resources inside these + * windows by re-using offset that were pre-calculated in pass 1. This + * continues until resource allocation is realized for all downstream + * bridges in the domain sub-tree. This is referred to as pass 2 of the + * resource allocator. + * + * Some rules that are followed by the resource allocator: + * - Allocate resource locations for every device as long as + * the requirements can be satisfied. + * - Don't overlap with resources in fixed locations. + * - Don't overlap and follow the rules of bridges -- downstream + * devices of bridges should use parts of the address space + * allocated to the bridge. + */ +void allocate_resources(const struct device *root) +{ + const struct device *child; + + if ((root == NULL) || (root->link_list == NULL)) + return; + + for (child = root->link_list->children; child; child = child->sibling) { + + if (child->path.type != DEVICE_PATH_DOMAIN) + continue; + + post_log_path(child); + + /* Pass 1 - Gather requirements. */ + printk(BIOS_INFO, "==== Resource allocator: %s - Pass 1 (gathering requirements) ===\n", + dev_path(child)); + compute_domain_resources(child); + + /* Pass 2 - Allocate resources as per gathered requirements. */ + printk(BIOS_INFO, "=== Resource allocator: %s - Pass 2 (allocating resources) ===\n", + dev_path(child)); + allocate_domain_resources(child); + + printk(BIOS_INFO, "=== Resource allocator: %s - resource allocation complete ===\n", + dev_path(child)); + } +} diff --git a/src/northbridge/amd/agesa/family14/Kconfig b/src/northbridge/amd/agesa/family14/Kconfig index edd7dcb..80c7a45 100644 --- a/src/northbridge/amd/agesa/family14/Kconfig +++ b/src/northbridge/amd/agesa/family14/Kconfig @@ -2,7 +2,7 @@ config NORTHBRIDGE_AMD_AGESA_FAMILY14 bool - select RESOURCE_ALLOCATOR_V3 + select DEFAULT_RESOURCE_ALLOCATOR_V3 if NORTHBRIDGE_AMD_AGESA_FAMILY14 diff --git a/src/northbridge/amd/agesa/family15tn/Kconfig b/src/northbridge/amd/agesa/family15tn/Kconfig index 8f012d5..d1af645 100644 --- a/src/northbridge/amd/agesa/family15tn/Kconfig +++ b/src/northbridge/amd/agesa/family15tn/Kconfig @@ -2,7 +2,7 @@ config NORTHBRIDGE_AMD_AGESA_FAMILY15_TN bool - select RESOURCE_ALLOCATOR_V3 + select DEFAULT_RESOURCE_ALLOCATOR_V3 if NORTHBRIDGE_AMD_AGESA_FAMILY15_TN diff --git a/src/northbridge/amd/agesa/family16kb/Kconfig b/src/northbridge/amd/agesa/family16kb/Kconfig index 4488f8d..d7bc660 100644 --- a/src/northbridge/amd/agesa/family16kb/Kconfig +++ b/src/northbridge/amd/agesa/family16kb/Kconfig @@ -2,7 +2,7 @@ config NORTHBRIDGE_AMD_AGESA_FAMILY16_KB bool - select RESOURCE_ALLOCATOR_V3 + select DEFAULT_RESOURCE_ALLOCATOR_V3 if NORTHBRIDGE_AMD_AGESA_FAMILY16_KB diff --git a/src/northbridge/amd/pi/00630F01/Kconfig b/src/northbridge/amd/pi/00630F01/Kconfig index 292492e..a3a7cd2 100644 --- a/src/northbridge/amd/pi/00630F01/Kconfig +++ b/src/northbridge/amd/pi/00630F01/Kconfig @@ -2,7 +2,7 @@ config NORTHBRIDGE_AMD_PI_00630F01 bool - select RESOURCE_ALLOCATOR_V3 + select DEFAULT_RESOURCE_ALLOCATOR_V3 if NORTHBRIDGE_AMD_PI_00630F01 diff --git a/src/northbridge/amd/pi/00660F01/Kconfig b/src/northbridge/amd/pi/00660F01/Kconfig index e42ba80..d99a0f5 100644 --- a/src/northbridge/amd/pi/00660F01/Kconfig +++ b/src/northbridge/amd/pi/00660F01/Kconfig @@ -2,7 +2,7 @@ config NORTHBRIDGE_AMD_PI_00660F01 bool - select RESOURCE_ALLOCATOR_V3 + select DEFAULT_RESOURCE_ALLOCATOR_V3 if NORTHBRIDGE_AMD_PI_00660F01 diff --git a/src/northbridge/amd/pi/00730F01/Kconfig b/src/northbridge/amd/pi/00730F01/Kconfig index cb65506..b936543 100644 --- a/src/northbridge/amd/pi/00730F01/Kconfig +++ b/src/northbridge/amd/pi/00730F01/Kconfig @@ -2,7 +2,7 @@ config NORTHBRIDGE_AMD_PI_00730F01 bool - select RESOURCE_ALLOCATOR_V3 + select DEFAULT_RESOURCE_ALLOCATOR_V3 if NORTHBRIDGE_AMD_PI_00730F01 -- To view, visit https://review.coreboot.org/c/coreboot/+/41956 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c27e89916e6e915d4dfe5435fac53fef768bf37 Gerrit-Change-Number: 41956 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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coreboot-gerrit August 2020