coreboot-gerrit August 2020

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Change in coreboot[master]: soc/intel/common: Adds compressed RW blob to RW_A and RW_B
by Sridhar Siricilla (Code Review) 07 Aug '23

07 Aug '23

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44822 ) Change subject: soc/intel/common: Adds compressed RW blob to RW_A and RW_B ...................................................................... soc/intel/common: Adds compressed RW blob to RW_A and RW_B Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Ic4a8797946284359656d3b092fc55812a3de2d37 --- M src/soc/intel/common/block/cse/Makefile.inc 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/44822/1 diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc index 11cc3c2..7ea6fdc 100644 --- a/src/soc/intel/common/block/cse/Makefile.inc +++ b/src/soc/intel/common/block/cse/Makefile.inc @@ -11,4 +11,13 @@ $(CSE_LITE_ME_RW)-file := $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_FILE)) $(CSE_LITE_ME_RW)-name := $(CSE_LITE_ME_RW) $(CSE_LITE_ME_RW)-type := raw +$(CSE_LITE_ME_RW)-compression := lzma + + +CSE_LITE_ME_RW_VER = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_VER_CBFS_NAME)) +regions-for-file-$(CSE_LITE_ME_RW_VER) = FW_MAIN_A,FW_MAIN_B +cbfs-files-y += $(CSE_LITE_ME_RW_VER) +$(CSE_LITE_ME_RW_VER)-file := $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_VER_FILE)) +$(CSE_LITE_ME_RW_VER)-name := $(CSE_LITE_ME_RW_VER) +$(CSE_LITE_ME_RW_VER)-type := raw endif -- To view, visit https://review.coreboot.org/c/coreboot/+/44822 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4a8797946284359656d3b092fc55812a3de2d37 Gerrit-Change-Number: 44822 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [TESTME] mb/bostentech/gbyt4: Add libgfxinit support
by Angel Pons (Code Review) 07 Aug '23

07 Aug '23

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44938 ) Change subject: [TESTME] mb/bostentech/gbyt4: Add libgfxinit support ...................................................................... [TESTME] mb/bostentech/gbyt4: Add libgfxinit support Change-Id: Id729f730f93f5c26b603a5b7a94f671f7fd9bfb7 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/bostentech/gbyt4/Kconfig M src/mainboard/bostentech/gbyt4/Makefile.inc A src/mainboard/bostentech/gbyt4/gma-mainboard.ads 3 files changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/44938/1 diff --git a/src/mainboard/bostentech/gbyt4/Kconfig b/src/mainboard/bostentech/gbyt4/Kconfig index a267840..d5e8bda 100644 --- a/src/mainboard/bostentech/gbyt4/Kconfig +++ b/src/mainboard/bostentech/gbyt4/Kconfig @@ -7,6 +7,7 @@ select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME + select MAINBOARD_HAS_LIBGFXINIT select SUPERIO_ITE_IT8728F config MAINBOARD_DIR diff --git a/src/mainboard/bostentech/gbyt4/Makefile.inc b/src/mainboard/bostentech/gbyt4/Makefile.inc index 11a2a4a..a4fecae 100644 --- a/src/mainboard/bostentech/gbyt4/Makefile.inc +++ b/src/mainboard/bostentech/gbyt4/Makefile.inc @@ -3,3 +3,5 @@ ramstage-y += irqroute.c gpio.c bootblock-y += early_init.c romstage-y += early_init.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/bostentech/gbyt4/gma-mainboard.ads b/src/mainboard/bostentech/gbyt4/gma-mainboard.ads new file mode 100644 index 0000000..c6422a5 --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/gma-mainboard.ads @@ -0,0 +1,15 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (Analog, + others => Disabled); + +end GMA.Mainboard; -- To view, visit https://review.coreboot.org/c/coreboot/+/44938 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id729f730f93f5c26b603a5b7a94f671f7fd9bfb7 Gerrit-Change-Number: 44938 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Mic_Bias voltage changed to 2.9V for Earpods Mic
by Vani Ganji (Code Review) 07 Aug '23

07 Aug '23

Vani Ganji has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35961 ) Change subject: Mic_Bias voltage changed to 2.9V for Earpods Mic ...................................................................... Mic_Bias voltage changed to 2.9V for Earpods Mic Earpods Mic is not working with 2.6Volts and it requires a volatge greater than 2.7Volts. BUG=b:134361881 Change-Id: Iceb62d4940a1d93404dc3f69884c1289f462f587 Signed-off-by: Vani Ganji <vani.ganji(a)intel.com> --- M src/mainboard/google/poppy/variants/atlas/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/35961/1 diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index ac86e79..b42313f 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -347,7 +347,7 @@ register "c_mic_btn_thr" = "0x3e" register "btn_avg" = "4" register "adc_1bit_rpt" = "1" - register "micbias_lvl" = "2600" + register "micbias_lvl" = "2900" register "mic_amp_in_sel" = ""diff"" device i2c 1a on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/35961 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iceb62d4940a1d93404dc3f69884c1289f462f587 Gerrit-Change-Number: 35961 Gerrit-PatchSet: 1 Gerrit-Owner: Vani Ganji <vani.ganji(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mainboard/intel/tgl: Customize PCH VR settings for better Sx power sa...
by Shreesh Chhabbi (Code Review) 07 Aug '23

07 Aug '23

Hello Shreesh Chhabbi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/43992 to review the following change. Change subject: mainboard/intel/tgl: Customize PCH VR settings for better Sx power savings ...................................................................... mainboard/intel/tgl: Customize PCH VR settings for better Sx power savings Change-Id: Ic889d0952b75a636d2186d81fb679f74d50e7048 Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 2 files changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/43992/1 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index b4a121a..1aa1f26 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -151,6 +151,20 @@ }, }" + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX, + .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, + .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL | + FIVR_VOLTAGE_MIN_ACTIVE | + FIVR_VOLTAGE_MIN_RETENTION, + .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL | + FIVR_VOLTAGE_MIN_ACTIVE | + FIVR_VOLTAGE_MIN_RETENTION, + .v1p05_icc_max_ma = 500, + .vnn_sx_voltage_mv = 1250, + }" + device domain 0 on #From EDS(575683) device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index b08cd3c..169433b 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -147,6 +147,20 @@ }, }" + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX, + .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, + .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL | + FIVR_VOLTAGE_MIN_ACTIVE | + FIVR_VOLTAGE_MIN_RETENTION, + .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL | + FIVR_VOLTAGE_MIN_ACTIVE | + FIVR_VOLTAGE_MIN_RETENTION, + .v1p05_icc_max_ma = 500, + .vnn_sx_voltage_mv = 1250, + }" + device domain 0 on #From EDS(575683) device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y -- To view, visit https://review.coreboot.org/c/coreboot/+/43992 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic889d0952b75a636d2186d81fb679f74d50e7048 Gerrit-Change-Number: 43992 Gerrit-PatchSet: 1 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP]mb/volteer: Remove DQ/DQS mappings for LPDDR4
by Ravishankar Sarawadi (Code Review) 07 Aug '23

07 Aug '23

Ravishankar Sarawadi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44748 ) Change subject: [WIP]mb/volteer: Remove DQ/DQS mappings for LPDDR4 ...................................................................... [WIP]mb/volteer: Remove DQ/DQS mappings for LPDDR4 MRC v incorporates algorithm which finds the Dq mapping between CPU and DRAM by using CPGC to issue reads and and walking through setting each bit and reading it back through datatrainfeedback. Only LPDDR4 will be enabling this function at this time. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Change-Id: I70da3d482385fe6b1ccf071af8d8bd8e44d898ca --- M src/mainboard/google/volteer/variants/baseboard/memory.c M src/mainboard/google/volteer/variants/delbin/memory.c M src/mainboard/google/volteer/variants/halvor/memory.c M src/mainboard/google/volteer/variants/malefor/memory.c M src/mainboard/google/volteer/variants/terrador/memory.c M src/mainboard/google/volteer/variants/todor/memory.c M src/mainboard/google/volteer/variants/voxel/memory.c M src/soc/intel/tigerlake/include/soc/meminit.h M src/soc/intel/tigerlake/meminit.c 9 files changed, 0 insertions(+), 565 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/44748/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/memory.c b/src/mainboard/google/volteer/variants/baseboard/memory.c index dafeb3b..910916b 100644 --- a/src/mainboard/google/volteer/variants/baseboard/memory.c +++ b/src/mainboard/google/volteer/variants/baseboard/memory.c @@ -5,54 +5,6 @@ #include <gpio.h> static const struct lpddr4x_cfg baseboard_lpddr4x_memcfg = { - /* DQ CPU<>DRAM map */ - .dq_map = { - [0] = { - { 0, 1, 2, 3, 4, 5, 6, 7, }, /* DDR0_DQ0[7:0] */ - { 12, 13, 14, 15, 11, 10, 9, 8, }, /* DDR0_DQ1[7:0] */ - }, - [1] = { - { 7, 2, 6, 3, 5, 1, 4, 0, }, /* DDR1_DQ0[7:0] */ - { 10, 8, 9, 11, 15, 12, 14, 13, }, /* DDR1_DQ1[7:0] */ - }, - [2] = { - { 3, 2, 1, 0, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ - { 12, 13, 14, 15, 11, 10, 9, 8, }, /* DDR2_DQ1[7:0] */ - }, - [3] = { - { 7, 0, 1, 6, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ - { 15, 14, 8, 9, 10, 12, 11, 13, }, /* DDR3_DQ1[7:0] */ - }, - [4] = { - { 3, 2, 1, 0, 4, 5, 6, 7, }, /* DDR4_DQ0[7:0] */ - { 12, 13, 14, 15, 11, 10, 9, 8, }, /* DDR4_DQ1[7:0] */ - }, - [5] = { - { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ - { 13, 12, 11, 10, 14, 15, 9, 8, }, /* DDR5_DQ1[7:0] */ - }, - [6] = { - { 3, 2, 1, 0, 7, 4, 5, 6, }, /* DDR6_DQ0[7:0] */ - { 15, 14, 13, 12, 8, 9, 10, 11, }, /* DDR6_DQ1[7:0] */ - }, - [7] = { - { 3, 4, 2, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ - { 15, 14, 9, 8, 12, 10, 11, 13, }, /* DDR7_DQ1[7:0] */ - }, - }, - - /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ - [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ - [3] = { 0, 1 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ - [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ - }, - .ect = 1, /* Enable Early Command Training */ }; diff --git a/src/mainboard/google/volteer/variants/delbin/memory.c b/src/mainboard/google/volteer/variants/delbin/memory.c index 9d8ad40..1f93c38 100644 --- a/src/mainboard/google/volteer/variants/delbin/memory.c +++ b/src/mainboard/google/volteer/variants/delbin/memory.c @@ -3,54 +3,6 @@ #include <baseboard/variants.h> static const struct lpddr4x_cfg delbin_memcfg = { - /* DQ byte map */ - .dq_map = { - [0] = { - { 3, 2, 1, 0, 4, 5, 7, 6, }, /* DDR0_DQ0[7:0] */ - { 12, 13, 14, 15, 11, 10, 9, 8 }, /* DDR0_DQ1[7:0] */ - }, - [1] = { - { 0, 7, 1, 6, 2, 5, 3, 4, }, /* DDR1_DQ0[7:0] */ - { 8, 15, 14, 9, 12, 10, 13, 11 }, /* DDR1_DQ1[7:0] */ - }, - [2] = { - { 2, 3, 0, 1, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ - { 12, 13, 15, 14, 11, 10, 9, 8 }, /* DDR2_DQ1[7:0] */ - }, - [3] = { - { 7, 0, 1, 6, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ - { 15, 14, 8, 9, 10, 13, 11, 12 }, /* DDR3_DQ1[7:0] */ - }, - [4] = { - { 4, 5, 2, 3, 7, 6, 0, 1, }, /* DDR4_DQ0[7:0] */ - { 12, 13, 15, 14, 11, 10, 8, 9 }, /* DDR4_DQ1[7:0] */ - }, - [5] = { - { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ - { 12, 13, 11, 10, 14, 15, 9, 8 }, /* DDR5_DQ1[7:0] */ - }, - [6] = { - { 3, 2, 1, 0, 7, 4, 5, 6, }, /* DDR6_DQ0[7:0] */ - { 15, 14, 13, 12, 8, 9, 10, 11 }, /* DDR6_DQ1[7:0] */ - }, - [7] = { - { 2, 4, 3, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ - { 14, 15, 9, 8, 12, 10, 11, 13 }, /* DDR7_DQ1[7:0] */ - }, - }, - - /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ - [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ - [3] = { 0, 1 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ - [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ - }, - .ect = 1, /* Enable Early Command Training */ }; diff --git a/src/mainboard/google/volteer/variants/halvor/memory.c b/src/mainboard/google/volteer/variants/halvor/memory.c index edbb681..cb0bbbae 100644 --- a/src/mainboard/google/volteer/variants/halvor/memory.c +++ b/src/mainboard/google/volteer/variants/halvor/memory.c @@ -3,54 +3,6 @@ #include <baseboard/variants.h> static const struct lpddr4x_cfg halvor_memcfg = { - /* DQ byte map */ - .dq_map = { - [0] = { - { 10, 12, 13, 9, 11, 8, 15, 14,}, /* DDR0_DQ0[7:0] */ - { 3, 0, 1, 5, 4, 7, 6, 2 }, /* DDR0_DQ1[7:0] */ - }, - [1] = { - { 8, 10, 13, 9, 12, 15, 11, 14, }, /* DDR1_DQ0[7:0] */ - { 3, 5, 7, 2, 1, 0, 4, 6 }, /* DDR1_DQ1[7:0] */ - }, - [2] = { - { 1, 3, 0, 2, 5, 4, 7, 6, }, /* DDR2_DQ0[7:0] */ - { 15, 14, 12, 13, 8, 9, 10, 11 }, /* DDR2_DQ1[7:0] */ - }, - [3] = { - { 8, 9, 10, 11, 14, 12, 15, 13, }, /* DDR3_DQ0[7:0] */ - { 5, 6, 7, 4, 2, 3, 1, 0 }, /* DDR3_DQ1[7:0] */ - }, - [4] = { - { 9, 8, 10, 11, 12, 13, 14, 15, }, /* DDR4_DQ0[7:0] */ - { 6, 7, 4, 5, 0, 2, 1, 3 }, /* DDR4_DQ1[7:0] */ - }, - [5] = { - { 0, 1, 3, 2, 7, 4, 5, 6, }, /* DDR5_DQ0[7:0] */ - { 15, 14, 9, 12, 8, 13, 11, 10 }, /* DDR5_DQ1[7:0] */ - }, - [6] = { - { 7, 5, 3, 6, 1, 0, 4, 2, }, /* DDR6_DQ0[7:0] */ - { 12, 14, 15, 13, 8, 11, 9, 10 }, /* DDR6_DQ1[7:0] */ - }, - [7] = { - { 3, 7, 1, 6, 5, 4, 2, 0, }, /* DDR7_DQ0[7:0] */ - { 12, 11, 8, 14, 10, 9, 15, 13 }, /* DDR7_DQ1[7:0] */ - }, - }, - - /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 1, 0 }, /* DDR0_DQS[1:0] */ - [1] = { 1, 0 }, /* DDR1_DQS[1:0] */ - [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ - [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ - [4] = { 1, 0 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ - [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ - }, - .ect = 1, /* Enable Early Command Training */ }; diff --git a/src/mainboard/google/volteer/variants/malefor/memory.c b/src/mainboard/google/volteer/variants/malefor/memory.c index 2c879e0..b1ade9e 100644 --- a/src/mainboard/google/volteer/variants/malefor/memory.c +++ b/src/mainboard/google/volteer/variants/malefor/memory.c @@ -3,54 +3,6 @@ #include <baseboard/variants.h> static const struct lpddr4x_cfg malefor_memcfg = { - /* DQ byte map */ - .dq_map = { - [0] = { - { 3, 1, 0, 2, 4, 6, 7, 5, }, /* DDR0_DQ0[7:0] */ - { 12, 13, 14, 15, 8, 9, 10, 11 }, /* DDR0_DQ1[7:0] */ - }, - [1] = { - { 0, 7, 1, 6, 2, 4, 3, 5, }, /* DDR1_DQ0[7:0] */ - { 8, 15, 14, 9, 13, 10, 12, 11 }, /* DDR1_DQ1[7:0] */ - }, - [2] = { - { 3, 2, 0, 1, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ - { 12, 13, 15, 14, 8, 9, 10, 11 }, /* DDR2_DQ1[7:0] */ - }, - [3] = { - { 6, 0, 1, 7, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ - { 15, 14, 8, 9, 10, 12, 11, 13 }, /* DDR3_DQ1[7:0] */ - }, - [4] = { - { 5, 0, 1, 3, 4, 2, 7, 6, }, /* DDR4_DQ0[7:0] */ - { 11, 14, 13, 12, 8, 9, 15, 10 }, /* DDR4_DQ1[7:0] */ - }, - [5] = { - { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ - { 13, 12, 11, 10, 14, 15, 9, 8 }, /* DDR5_DQ1[7:0] */ - }, - [6] = { - { 3, 2, 1, 0, 5, 4, 7, 6, }, /* DDR6_DQ0[7:0] */ - { 12, 13, 15, 14, 8, 11, 9, 10 }, /* DDR6_DQ1[7:0] */ - }, - [7] = { - { 3, 4, 2, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ - { 15, 14, 9, 8, 12, 10, 11, 13 }, /* DDR7_DQ1[7:0] */ - }, - }, - - /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ - [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ - [3] = { 0, 1 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ - [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ - }, - .ect = 1, /* Enable Early Command Training */ }; diff --git a/src/mainboard/google/volteer/variants/terrador/memory.c b/src/mainboard/google/volteer/variants/terrador/memory.c index 7d95658..a8f5ea8 100644 --- a/src/mainboard/google/volteer/variants/terrador/memory.c +++ b/src/mainboard/google/volteer/variants/terrador/memory.c @@ -3,54 +3,6 @@ #include <baseboard/variants.h> static const struct lpddr4x_cfg terrador_memcfg = { - /* DQ byte map */ - .dq_map = { - [0] = { - { 7, 3, 1, 4, 0, 5, 2, 6, }, /* DDR0_DQ0[7:0] */ - { 13, 14, 8, 10, 9, 15, 11, 12 }, /* DDR0_DQ1[7:0] */ - }, - [1] = { - { 1, 2, 7, 6, 3, 5, 4, 0, }, /* DDR1_DQ0[7:0] */ - { 14, 15, 13, 10, 8, 11, 12, 9 }, /* DDR1_DQ1[7:0] */ - }, - [2] = { - { 11, 15, 10, 9, 8, 12, 13, 14, }, /* DDR2_DQ0[7:0] */ - { 5, 6, 4, 0, 7, 2, 3, 1 }, /* DDR2_DQ1[7:0] */ - }, - [3] = { - { 11, 15, 10, 9, 13, 12, 14, 8, }, /* DDR3_DQ0[7:0] */ - { 0, 5, 6, 4, 1, 2, 7, 3 }, /* DDR3_DQ1[7:0] */ - }, - [4] = { - { 7, 2, 3, 1, 4, 0, 5, 6, }, /* DDR4_DQ0[7:0] */ - { 13, 14, 8, 12, 10, 9, 15, 11 }, /* DDR4_DQ1[7:0] */ - }, - [5] = { - { 7, 3, 2, 1, 6, 4, 0, 5, }, /* DDR5_DQ0[7:0] */ - { 15, 14, 12, 8, 11, 13, 9, 10 }, /* DDR5_DQ1[7:0] */ - }, - [6] = { - { 11, 10, 15, 12, 8, 9, 14, 13, }, /* DDR6_DQ0[7:0] */ - { 6, 0, 5, 4, 3, 2, 7, 1 }, /* DDR6_DQ1[7:0] */ - }, - [7] = { - { 9, 10, 11, 8, 12, 14, 13, 15, }, /* DDR7_DQ0[7:0] */ - { 0, 5, 4, 7, 1, 6, 3, 2 }, /* DDR7_DQ1[7:0] */ - }, - }, - - /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ - [2] = { 1, 0 }, /* DDR2_DQS[1:0] */ - [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 1, 0 }, /* DDR6_DQS[1:0] */ - [7] = { 1, 0 }, /* DDR7_DQS[1:0] */ - }, - .ect = 1, /* Enable Early Command Training */ }; diff --git a/src/mainboard/google/volteer/variants/todor/memory.c b/src/mainboard/google/volteer/variants/todor/memory.c index c8b4ab4..e61f3b8 100644 --- a/src/mainboard/google/volteer/variants/todor/memory.c +++ b/src/mainboard/google/volteer/variants/todor/memory.c @@ -3,54 +3,6 @@ #include <baseboard/variants.h> static const struct lpddr4x_cfg todor_memcfg = { - /* DQ byte map */ - .dq_map = { - [0] = { - { 7, 3, 1, 4, 0, 5, 2, 6, }, /* DDR0_DQ0[7:0] */ - { 13, 14, 8, 10, 9, 15, 11, 12 }, /* DDR0_DQ1[7:0] */ - }, - [1] = { - { 1, 2, 7, 6, 3, 5, 4, 0, }, /* DDR1_DQ0[7:0] */ - { 14, 15, 13, 10, 8, 11, 12, 9 }, /* DDR1_DQ1[7:0] */ - }, - [2] = { - { 11, 15, 10, 9, 8, 12, 13, 14, }, /* DDR2_DQ0[7:0] */ - { 5, 6, 4, 0, 7, 2, 3, 1 }, /* DDR2_DQ1[7:0] */ - }, - [3] = { - { 11, 15, 10, 9, 13, 12, 14, 8, }, /* DDR3_DQ0[7:0] */ - { 0, 5, 6, 4, 1, 2, 7, 3 }, /* DDR3_DQ1[7:0] */ - }, - [4] = { - { 7, 2, 3, 1, 4, 0, 5, 6, }, /* DDR4_DQ0[7:0] */ - { 13, 14, 8, 12, 10, 9, 15, 11 }, /* DDR4_DQ1[7:0] */ - }, - [5] = { - { 7, 3, 2, 1, 6, 4, 0, 5, }, /* DDR5_DQ0[7:0] */ - { 15, 14, 12, 8, 11, 13, 9, 10 }, /* DDR5_DQ1[7:0] */ - }, - [6] = { - { 11, 10, 15, 12, 8, 9, 14, 13, }, /* DDR6_DQ0[7:0] */ - { 6, 0, 5, 4, 3, 2, 7, 1 }, /* DDR6_DQ1[7:0] */ - }, - [7] = { - { 9, 10, 11, 8, 12, 14, 13, 15, }, /* DDR7_DQ0[7:0] */ - { 0, 5, 4, 7, 1, 6, 3, 2 }, /* DDR7_DQ1[7:0] */ - }, - }, - - /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ - [2] = { 1, 0 }, /* DDR2_DQS[1:0] */ - [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 1, 0 }, /* DDR6_DQS[1:0] */ - [7] = { 1, 0 }, /* DDR7_DQS[1:0] */ - }, - .ect = 1, /* Enable Early Command Training */ }; diff --git a/src/mainboard/google/volteer/variants/voxel/memory.c b/src/mainboard/google/volteer/variants/voxel/memory.c index 40b1086..a028ab7 100644 --- a/src/mainboard/google/volteer/variants/voxel/memory.c +++ b/src/mainboard/google/volteer/variants/voxel/memory.c @@ -3,54 +3,6 @@ #include <baseboard/variants.h> static const struct lpddr4x_cfg voxel_memcfg = { - /* DQ byte map */ - .dq_map = { - [0] = { - { 3, 0, 1, 2, 6, 7, 5, 4, }, /* DDR0_DQ0[7:0] */ - { 12, 15, 14, 13, 8, 9, 10, 11 }, /* DDR0_DQ1[7:0] */ - }, - [1] = { - { 12, 15, 13, 14, 10, 8, 11, 9, }, /* DDR1_DQ0[7:0] */ - { 5, 6, 7, 4, 0, 3, 1, 2 }, /* DDR1_DQ1[7:0] */ - }, - [2] = { - { 2, 3, 0, 1, 7, 6, 5, 4, }, /* DDR2_DQ0[7:0] */ - { 12, 14, 15, 13, 10, 9, 8, 11 }, /* DDR2_DQ1[7:0] */ - }, - [3] = { - { 15, 12, 13, 14, 8, 9, 10, 11, }, /* DDR3_DQ0[7:0] */ - { 7, 6, 4, 5, 2, 0, 3, 1 }, /* DDR3_DQ1[7:0] */ - }, - [4] = { - { 6, 5, 4, 7, 0, 3, 2, 1, }, /* DDR4_DQ0[7:0] */ - { 15, 14, 13, 12, 11, 8, 9, 10 }, /* DDR4_DQ1[7:0] */ - }, - [5] = { - { 11, 9, 10, 8, 12, 14, 13, 15, }, /* DDR5_DQ0[7:0] */ - { 1, 0, 2, 3, 6, 7, 5, 4 }, /* DDR5_DQ1[7:0] */ - }, - [6] = { - { 2, 3, 0, 1, 5, 4, 6, 7, }, /* DDR6_DQ0[7:0] */ - { 13, 14, 15, 12, 11, 10, 8, 9 }, /* DDR6_DQ1[7:0] */ - }, - [7] = { - { 14, 13, 15, 12, 9, 8, 10, 11, }, /* DDR7_DQ0[7:0] */ - { 4, 5, 1, 2, 6, 0, 3, 7 }, /* DDR7_DQ1[7:0] */ - }, - }, - - /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 1, 0 }, /* DDR1_DQS[1:0] */ - [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ - [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 1, 0 }, /* DDR5_DQS[1:0] */ - [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ - [7] = { 1, 0 }, /* DDR7_DQS[1:0] */ - }, - .ect = 1, /* Enable Early Command Training */ }; diff --git a/src/soc/intel/tigerlake/include/soc/meminit.h b/src/soc/intel/tigerlake/include/soc/meminit.h index 4a52298..a9bf918 100644 --- a/src/soc/intel/tigerlake/include/soc/meminit.h +++ b/src/soc/intel/tigerlake/include/soc/meminit.h @@ -64,30 +64,6 @@ /* Board-specific memory configuration information */ struct lpddr4x_cfg { /* - * DQ CPU<>DRAM map: - * LPDDR4x memory interface has 2 DQs per channel. Each DQ consists of 8 bits(1 - * byte). Thus, dq_map is represented as DDR[7-0]_DQ[1-0][7:0], where - * DDR[7-0] : LPDDR4x channel # - * DQ[1-0] : DQ # within the channel - * [7:0] : Bits within the DQ - * - * Index of the array represents DQ pin# on the CPU, whereas value in - * the array represents DQ pin# on the memory part. - */ - uint8_t dq_map[LPDDR4X_CHANNELS][LPDDR4X_BYTES_PER_CHANNEL][BITS_PER_BYTE]; - - /* - * DQS CPU<>DRAM map: - * LPDDR4x memory interface has 2 DQS pairs(P/N) per channel. Thus, dqs_map is - * represented as DDR[7-0]_DQS[1:0], where - * DDR[7-0] : LPDDR4x channel # - * DQS[1-0] : DQS # within the channel - * - * Index of the array represents DQS pin# on the CPU, whereas value in - * the array represents DQ pin# on the memory part. - */ - uint8_t dqs_map[LPDDR4X_CHANNELS][LPDDR4X_BYTES_PER_CHANNEL]; - /* * Early Command Training Enable/Disable Control * 1 = enable, 0 = disable */ @@ -97,29 +73,6 @@ /* Board-specific memory configuration information for DDR4 memory variant */ struct mb_ddr4_cfg { /* - * DQ CPU<>DRAM map: - * DDR4 memory interface has 8 DQs per channel. Each DQ consists of 8 bits(1 - * byte). Thus, dq_map is represented as DDR[1-0]_DQ[7-0][7:0], where - * DDR[1-0] : DDR4 channel # - * DQ[7-0] : DQ # within the channel - * [7:0] : Bits within the DQ - * - * Index of the array represents DQ pin# on the CPU, whereas value in - * the array represents DQ pin# on the memory part. - */ - uint8_t dq_map[DDR4_CHANNELS][DDR4_BYTES_PER_CHANNEL][BITS_PER_BYTE]; - /* - * DQS CPU<>DRAM map: - * DDR4 memory interface has 8 DQS pairs per channel. Thus, dqs_map is represented as - * DDR[1-0]_DQS[7-0], where - * DDR[1-0] : DDR4 channel # - * DQS[7-0] : DQS # within the channel - * - * Index of the array represents DQS pin# on the CPU, whereas value in - * the array represents DQS pin# on the memory part. - */ - uint8_t dqs_map[DDR4_CHANNELS][DDR4_BYTES_PER_CHANNEL]; - /* * Indicates whether memory is interleaved. * Set to 1 for an interleaved design, * set to 0 for non-interleaved design. diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c index 0c6f0b0..7093d3d 100644 --- a/src/soc/intel/tigerlake/meminit.c +++ b/src/soc/intel/tigerlake/meminit.c @@ -109,96 +109,6 @@ init_spd_upds(mem_cfg, channel, spd_dimm0, 0); } -static void init_dq_upds(FSP_M_CONFIG *mem_cfg, int byte_pair, const uint8_t *dq_byte0, - const uint8_t *dq_byte1) -{ - uint8_t *dq_upd; - - switch (byte_pair) { - case 0: - dq_upd = mem_cfg->DqMapCpu2DramCh0; - break; - case 1: - dq_upd = mem_cfg->DqMapCpu2DramCh1; - break; - case 2: - dq_upd = mem_cfg->DqMapCpu2DramCh2; - break; - case 3: - dq_upd = mem_cfg->DqMapCpu2DramCh3; - break; - case 4: - dq_upd = mem_cfg->DqMapCpu2DramCh4; - break; - case 5: - dq_upd = mem_cfg->DqMapCpu2DramCh5; - break; - case 6: - dq_upd = mem_cfg->DqMapCpu2DramCh6; - break; - case 7: - dq_upd = mem_cfg->DqMapCpu2DramCh7; - break; - default: - die("Invalid byte_pair: %d\n", byte_pair); - } - - if (dq_byte0 && dq_byte1) { - memcpy(dq_upd, dq_byte0, BITS_PER_BYTE); - memcpy(dq_upd + BITS_PER_BYTE, dq_byte1, BITS_PER_BYTE); - } else { - memset(dq_upd, 0, BITS_PER_BYTE * 2); - } -} - -static inline void init_dq_upds_empty(FSP_M_CONFIG *mem_cfg, int byte_pair) -{ - init_dq_upds(mem_cfg, byte_pair, NULL, NULL); -} - -static void init_dqs_upds(FSP_M_CONFIG *mem_cfg, int byte_pair, uint8_t dqs_byte0, - uint8_t dqs_byte1) -{ - uint8_t *dqs_upd; - - switch (byte_pair) { - case 0: - dqs_upd = mem_cfg->DqsMapCpu2DramCh0; - break; - case 1: - dqs_upd = mem_cfg->DqsMapCpu2DramCh1; - break; - case 2: - dqs_upd = mem_cfg->DqsMapCpu2DramCh2; - break; - case 3: - dqs_upd = mem_cfg->DqsMapCpu2DramCh3; - break; - case 4: - dqs_upd = mem_cfg->DqsMapCpu2DramCh4; - break; - case 5: - dqs_upd = mem_cfg->DqsMapCpu2DramCh5; - break; - case 6: - dqs_upd = mem_cfg->DqsMapCpu2DramCh6; - break; - case 7: - dqs_upd = mem_cfg->DqsMapCpu2DramCh7; - break; - default: - die("Invalid byte_pair: %d\n", byte_pair); - } - - dqs_upd[0] = dqs_byte0; - dqs_upd[1] = dqs_byte1; -} - -static inline void init_dqs_upds_empty(FSP_M_CONFIG *mem_cfg, int byte_pair) -{ - init_dqs_upds(mem_cfg, byte_pair, 0, 0); -} - static void read_spd_from_cbfs(uint8_t index, uintptr_t *data, size_t *len) { struct region_device spd_rdev; @@ -252,51 +162,6 @@ else init_spd_upds_dimm0(mem_cfg, i, spd_data); } - - /* - * LPDDR4x memory interface has 2 DQs per channel. Each DQ consists of 8 bits (1 - * byte). However, FSP UPDs for DQ Map expect a DQ pair (i.e. mapping for 2 bytes) in - * each UPD. - * - * Thus, init_dq_upds() needs to be called for dq pair of each channel. - * DqMapCpu2DramCh0 --> dq_map[CHAN=0][0-1] - * DqMapCpu2DramCh1 --> dq_map[CHAN=1][0-1] - * DqMapCpu2DramCh2 --> dq_map[CHAN=2][0-1] - * DqMapCpu2DramCh3 --> dq_map[CHAN=3][0-1] - * DqMapCpu2DramCh4 --> dq_map[CHAN=4][0-1] - * DqMapCpu2DramCh5 --> dq_map[CHAN=5][0-1] - * DqMapCpu2DramCh6 --> dq_map[CHAN=6][0-1] - * DqMapCpu2DramCh7 --> dq_map[CHAN=7][0-1] - */ - for (i = 0; i < LPDDR4X_CHANNELS; i++) { - if (LPDDR4X_CHANNEL_UNPOPULATED(i, half_populated)) - init_dq_upds_empty(mem_cfg, i); - else - init_dq_upds(mem_cfg, i, board_cfg->dq_map[i][0], - board_cfg->dq_map[i][1]); - } - - /* - * LPDDR4x memory interface has 2 DQS pairs per channel. FSP UPDs for DQS Map expect a - * pair in each UPD. - * - * Thus, init_dqs_upds() needs to be called for dqs pair of each channel. - * DqsMapCpu2DramCh0 --> dqs_map[CHAN=0][0-1] - * DqsMapCpu2DramCh1 --> dqs_map[CHAN=1][0-1] - * DqsMapCpu2DramCh2 --> dqs_map[CHAN=2][0-1] - * DqsMapCpu2DramCh3 --> dqs_map[CHAN=3][0-1] - * DqsMapCpu2DramCh4 --> dqs_map[CHAN=4][0-1] - * DqsMapCpu2DramCh5 --> dqs_map[CHAN=5][0-1] - * DqsMapCpu2DramCh6 --> dqs_map[CHAN=6][0-1] - * DqsMapCpu2DramCh7 --> dqs_map[CHAN=7][0-1] - */ - for (i = 0; i < LPDDR4X_CHANNELS; i++) { - if (LPDDR4X_CHANNEL_UNPOPULATED(i, half_populated)) - init_dqs_upds_empty(mem_cfg, i); - else - init_dqs_upds(mem_cfg, i, board_cfg->dqs_map[i][0], - board_cfg->dqs_map[i][1]); - } } static void read_sodimm_spd(const struct spd_info *info, struct spd_block *blk) @@ -363,7 +228,6 @@ uintptr_t spd_dimm1 = 0; struct spd_block spd_sodimm_blk; unsigned int i; - unsigned int index = 0; /* Early Command Training Enabled */ mem_cfg->ECT = board_cfg->ect; @@ -388,52 +252,6 @@ half_populated, &spd_dimm0, &spd_dimm1); init_spd_upds(mem_cfg, DDR4_FSP_UPD_CHANNEL_IDX(i), spd_dimm0, spd_dimm1); } - - /* - * DDR4 memory interface has 8 DQs per channel. Each DQ consists of 8 bits (1 - * byte). However, FSP UPDs for DQ Map expect a DQ pair (i.e. mapping for 2 bytes) in - * each UPD. - * - * Thus, init_dq_upds() needs to be called for every dq pair of each channel. - * DqMapCpu2DramCh0 --> dq_map[CHAN=0][0-1] - * DqMapCpu2DramCh1 --> dq_map[CHAN=0][2-3] - * DqMapCpu2DramCh2 --> dq_map[CHAN=0][4-5] - * DqMapCpu2DramCh3 --> dq_map[CHAN=0][6-7] - * DqMapCpu2DramCh4 --> dq_map[CHAN=1][0-1] - * DqMapCpu2DramCh5 --> dq_map[CHAN=1][2-3] - * DqMapCpu2DramCh6 --> dq_map[CHAN=1][4-5] - * DqMapCpu2DramCh7 --> dq_map[CHAN=1][6-7] - */ - - /* - * DDR4 memory interface has 8 DQS pairs per channel. FSP UPDs for DQS Map expect a - * pair in each UPD. - * - * Thus, init_dqs_upds() needs to be called for every dqs pair of each channel. - * DqsMapCpu2DramCh0 --> dqs_map[CHAN=0][0-1] - * DqsMapCpu2DramCh1 --> dqs_map[CHAN=0][2-3] - * DqsMapCpu2DramCh2 --> dqs_map[CHAN=0][4-5] - * DqsMapCpu2DramCh3 --> dqs_map[CHAN=0][6-7] - * DqsMapCpu2DramCh4 --> dqs_map[CHAN=1][0-1] - * DqsMapCpu2DramCh5 --> dqs_map[CHAN=1][2-3] - * DqsMapCpu2DramCh6 --> dqs_map[CHAN=1][4-5] - * DqsMapCpu2DramCh7 --> dqs_map[CHAN=1][6-7] - */ - - for (i = 0; i < DDR4_CHANNELS; i++) { - for (int b = 0; b < DDR4_BYTES_PER_CHANNEL; b += 2) { - if (half_populated && (i == 1)) { - init_dq_upds_empty(mem_cfg, index); - init_dqs_upds_empty(mem_cfg, index); - } else { - init_dq_upds(mem_cfg, index, board_cfg->dq_map[i][b], - board_cfg->dq_map[i][b+1]); - init_dqs_upds(mem_cfg, index, board_cfg->dqs_map[i][b], - board_cfg->dqs_map[i][b+1]); - } - index++; - } - } } void meminit_ddr(FSP_M_CONFIG *mem_cfg, const struct ddr_memory_cfg *board_cfg, -- To view, visit https://review.coreboot.org/c/coreboot/+/44748 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70da3d482385fe6b1ccf071af8d8bd8e44d898ca Gerrit-Change-Number: 44748 Gerrit-PatchSet: 1 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-MessageType: newchange

7 24

Change in ...coreboot[master]: intel/skylake: nhlt: Add 24 bit blobs for Max98373
by Jenny Tc (Code Review) 07 Aug '23

07 Aug '23

Jenny Tc has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31635 Change subject: intel/skylake: nhlt: Add 24 bit blobs for Max98373 ...................................................................... intel/skylake: nhlt: Add 24 bit blobs for Max98373 Enable 24 bit nhlt blobs and remove 16 bit blobs. 16 bit and 24 bit blobs cannot be supported together since the OS NHLT parsing relies on container bit format. The container bit format for 16 and 24 bit capture are same (32) and putting both blobs in configs results in selecting the first blob. To enable 24 and 16 bit blobs together, the core nhlt parsing logic has to be changed which would impact SKL and KBL platforms. In order to minimize the impact, the 16 bit blob is removed considering that the machine driver for max98373 is expected to support only format due to topology configuration for 16 and 24 bit. BUG=b:110795132 BRANCH=none TEST=Verify playback after flashing CQ-DEPEND=*806750 Change-Id: I62cc109fb0aca9269736779a6ce80980b0571b78 Signed-off-by: Jenny TC <jenny.tc(a)intel.com> --- M src/soc/intel/skylake/nhlt/Makefile.inc M src/soc/intel/skylake/nhlt/max98373.c 2 files changed, 6 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/31635/1 diff --git a/src/soc/intel/skylake/nhlt/Makefile.inc b/src/soc/intel/skylake/nhlt/Makefile.inc index 5c8bd80..548747a 100644 --- a/src/soc/intel/skylake/nhlt/Makefile.inc +++ b/src/soc/intel/skylake/nhlt/Makefile.inc @@ -21,7 +21,6 @@ DMIC_4CH_48KHZ_32B = dmic-4ch-48khz-32b.bin NAU88L25 = nau88l25-2ch-48khz-24b.bin MAX98357_RENDER = max98357-render-2ch-48khz-24b.bin -MAX98373_RENDER_16B = max98373-render-2ch-48khz-16b.bin MAX98373_RENDER_24B = max98373-render-2ch-48khz-24b.bin MAX98927_RENDER_24B = max98927-render-2ch-48khz-24b.bin MAX98927_RENDER_16B = max98927-render-2ch-48khz-16b.bin diff --git a/src/soc/intel/skylake/nhlt/max98373.c b/src/soc/intel/skylake/nhlt/max98373.c index 0e3a413..a781943 100644 --- a/src/soc/intel/skylake/nhlt/max98373.c +++ b/src/soc/intel/skylake/nhlt/max98373.c @@ -25,35 +25,26 @@ .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, .settings_file = "max98373-render-2ch-48khz-24b.bin", }, - /* 48 KHz 16-bits per sample. */ - { - .num_channels = 2, - .sample_freq_khz = 48, - .container_bits_per_sample = 16, - .valid_bits_per_sample = 16, - .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, - .settings_file = "max98373-render-2ch-48khz-16b.bin", - } }; static const struct nhlt_format_config max98373_capture_formats[] = { - /* 48 KHz 16-bits per sample - Quad Channel. */ + /* 48 KHz 24-bits per sample - Quad Channel. */ { .num_channels = 4, .sample_freq_khz = 48, .container_bits_per_sample = 32, - .valid_bits_per_sample = 16, + .valid_bits_per_sample = 24, .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, - .settings_file = "max98373-render-2ch-48khz-16b.bin", + .settings_file = "max98373-render-2ch-48khz-24b.bin", }, - /* 48 KHz 16-bits per sample - Stereo Channel */ + /* 48 KHz 24-bits per sample - Stereo Channel */ { .num_channels = 2, .sample_freq_khz = 48, .container_bits_per_sample = 32, - .valid_bits_per_sample = 16, + .valid_bits_per_sample = 24, .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, - .settings_file = "max98373-render-2ch-48khz-16b.bin", + .settings_file = "max98373-render-2ch-48khz-24b.bin", }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/31635 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62cc109fb0aca9269736779a6ce80980b0571b78 Gerrit-Change-Number: 31635 Gerrit-PatchSet: 1 Gerrit-Owner: Jenny Tc <jenny.tc(a)intel.com> Gerrit-MessageType: newchange

9 29

Change in coreboot[master]: nb/intel/sandybridge: Cache cbmem and stage cache in romstage
by Arthur Heymans (Code Review) 07 Aug '23

07 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37200 ) Change subject: nb/intel/sandybridge: Cache cbmem and stage cache in romstage ...................................................................... nb/intel/sandybridge: Cache cbmem and stage cache in romstage The compress postcar option will default to 'y' with this. Change-Id: I00de8bc42c5bfbe75cb1fdfd04d5e7ffc74b56e9 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/sandybridge/Kconfig M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_mrc.c 3 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/37200/1 diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 0502b50..1745b98 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -20,6 +20,7 @@ select CPU_INTEL_MODEL_206AX select HAVE_DEBUG_RAM_SETUP select INTEL_GMA_ACPI + select ROMSTAGE_CACHED_CBMEM if NORTHBRIDGE_INTEL_SANDYBRIDGE diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index c13ae37..441844e 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -19,6 +19,7 @@ #include <commonlib/region.h> #include <bootmode.h> #include <cf9_reset.h> +#include <cpu/x86/mtrr.h> #include <string.h> #include <arch/cpu.h> #include <device/mmio.h> @@ -422,6 +423,7 @@ report_memory_config(); + setup_romstage_wb_cbmem_cache(); cbmem_was_inited = !cbmem_recovery(s3resume); if (!fast_boot) save_timings(&ctrl); diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 29c766a..9e70fc1 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -17,6 +17,7 @@ #include <console/usb.h> #include <bootmode.h> #include <cf9_reset.h> +#include <cpu/x86/mtrr.h> #include <string.h> #include <device/device.h> #include <device/pci_ops.h> @@ -451,6 +452,7 @@ hexdump32(BIOS_ERR, mrc_var, sizeof(*mrc_var)/sizeof(u32)); } + setup_romstage_wb_cbmem_cache(); cbmem_was_initted = !cbmem_recovery(s3resume); if (!s3resume) save_mrc_data(&pei_data); -- To view, visit https://review.coreboot.org/c/coreboot/+/37200 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00de8bc42c5bfbe75cb1fdfd04d5e7ffc74b56e9 Gerrit-Change-Number: 37200 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 13

Change in coreboot[master]: drivers/amd/agesa/romstage: Only mark cbmem as UC if needed
by Arthur Heymans (Code Review) 07 Aug '23

07 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37197 ) Change subject: drivers/amd/agesa/romstage: Only mark cbmem as UC if needed ...................................................................... drivers/amd/agesa/romstage: Only mark cbmem as UC if needed Now cbmem is flushed to dram before calling postcar stage. UNTESTED. Change-Id: Iaa0d154e2c5b2052027d07ad26e31f3ff63ae9f3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/amd/agesa/mtrr_fixme.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/37197/1 diff --git a/src/drivers/amd/agesa/mtrr_fixme.c b/src/drivers/amd/agesa/mtrr_fixme.c index bbb9eb0..9e63425 100644 --- a/src/drivers/amd/agesa/mtrr_fixme.c +++ b/src/drivers/amd/agesa/mtrr_fixme.c @@ -51,6 +51,10 @@ if (s3resume) return; + /* We worry about cbmem hitting dram later */ + if (clflush_supported()) + return; + /* For normal path, INIT_POST has returned with all * memory set WB cacheable. But we need CBMEM as UC * to make CAR teardown with invalidation without -- To view, visit https://review.coreboot.org/c/coreboot/+/37197 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa0d154e2c5b2052027d07ad26e31f3ff63ae9f3 Gerrit-Change-Number: 37197 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 16

Change in coreboot[master]: nb/intel/nehalem: Cache cbmem and stage cache in romstage
by Arthur Heymans (Code Review) 07 Aug '23

07 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37201 ) Change subject: nb/intel/nehalem: Cache cbmem and stage cache in romstage ...................................................................... nb/intel/nehalem: Cache cbmem and stage cache in romstage The compress postcar option will default to 'y' with this. Change-Id: I8b495decc4d283e7f91a0cbdab3484165d0cadf6 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/nehalem/Kconfig M src/northbridge/intel/nehalem/raminit.c 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/37201/1 diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index 7b56841..bbea9e7 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -22,6 +22,7 @@ select CACHE_MRC_SETTINGS select HAVE_DEBUG_RAM_SETUP select C_ENVIRONMENT_BOOTBLOCK + select ROMSTAGE_CACHED_CBMEM if NORTHBRIDGE_INTEL_NEHALEM diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index fe5d5c9..0fb9b8d 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -4756,6 +4756,7 @@ udelay(1000); dump_timings(&info); + setup_romstage_wb_cbmem_cache(); cbmem_wasnot_inited = cbmem_recovery(s3resume); if (!s3resume) -- To view, visit https://review.coreboot.org/c/coreboot/+/37201 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b495decc4d283e7f91a0cbdab3484165d0cadf6 Gerrit-Change-Number: 37201 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 8

Change in ...coreboot[master]: WIP: update blobs repo submodule
by Martin Kepplinger (Code Review) 06 Aug '23

06 Aug '23

Martin Kepplinger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33197 Change subject: WIP: update blobs repo submodule ...................................................................... WIP: update blobs repo submodule Change-Id: I12fc447ee78d986f93f4c39bac282cb6a9a73814 Signed-off-by: Martin Kepplinger <martink(a)posteo.de> --- M 3rdparty/blobs 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/33197/1 diff --git a/3rdparty/blobs b/3rdparty/blobs index ca6cfcd..8147d6b 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit ca6cfcdbe1cdeb38c2622ee2e5236cc4657e3377 +Subproject commit 8147d6b601050f6fac6f4c5ccfd8cdadbe3507de -- To view, visit https://review.coreboot.org/c/coreboot/+/33197 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12fc447ee78d986f93f4c39bac282cb6a9a73814 Gerrit-Change-Number: 33197 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Kepplinger <martink(a)posteo.de> Gerrit-MessageType: newchange

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