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Change in coreboot[master]: [WIP]util/inteltool: Add dumping x4x timings
by Arthur Heymans (Code Review) 10 Jun '23

10 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35812 ) Change subject: [WIP]util/inteltool: Add dumping x4x timings ...................................................................... [WIP]util/inteltool: Add dumping x4x timings TODO DQS RX settings. Change-Id: I8816a3eb43b9a27ea09997e9cc0407c519485943 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/inteltool/Makefile M util/inteltool/inteltool.h M util/inteltool/memory.c A util/inteltool/x4x_memory.c 4 files changed, 284 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/35812/1 diff --git a/util/inteltool/Makefile b/util/inteltool/Makefile index cd02fa8..6c7dc80 100644 --- a/util/inteltool/Makefile +++ b/util/inteltool/Makefile @@ -28,7 +28,7 @@ CPPFLAGS += -I$(top)/src/commonlib/include OBJS = inteltool.o pcr.o cpu.o gpio.o gpio_groups.o rootcmplx.o powermgt.o \ - memory.o pcie.o amb.o ivy_memory.o spi.o gfx.o ahci.o \ + memory.o pcie.o amb.o ivy_memory.o spi.o gfx.o ahci.o x4x_memory.o \ OS_ARCH = $(shell uname) ifeq ($(OS_ARCH), Darwin) diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index fc6dc4b..cdd42da 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -400,5 +400,6 @@ int print_ahci(struct pci_dev *ahci); int print_sgx(void); void ivybridge_dump_timings(const char *dump_spd_file); +void x4x_dump_timings(void); #endif diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index e80f1ba..6fe025d 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -200,6 +200,7 @@ case PCI_DEVICE_ID_INTEL_32X0: mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; + x4x_dump_timings(); break; case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN: mchbar_phys = pci_read_long(nb, 0x48); diff --git a/util/inteltool/x4x_memory.c b/util/inteltool/x4x_memory.c new file mode 100644 index 0000000..a00ce82 --- /dev/null +++ b/util/inteltool/x4x_memory.c @@ -0,0 +1,281 @@ +/* + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 or (at your option) any later version of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <inttypes.h> +#include <errno.h> +#include "inteltool.h" + +extern volatile uint8_t *mchbar; + +struct dll_setting { + u8 tap; + u8 pi; + u8 db_en; + u8 db_sel; + u8 clk_delay; + u8 coarse; +}; + +static void print_dll_setting(char *s, const struct dll_setting *dll_setting) +{ + printf("\t%s: %x.%x.%x.%x:%x.%x\n", + s, + dll_setting->coarse, + dll_setting->clk_delay, + dll_setting->tap, + dll_setting->pi, + dll_setting->db_en, + dll_setting->db_sel); +} + + +static uint32_t read_mchbar32(uint32_t addr) +{ + return *(volatile uint32_t *)(mchbar + addr); +} + +static void get_clkset0(u8 channel, struct dll_setting *setting) +{ + u32 reg; + setting->coarse = 0; + reg = read_mchbar32(0x400 * channel + 0x5a0); + setting->clk_delay = (reg >> 14) & 3; + setting->db_sel = (reg >> 6) & 1; + setting->db_en = (reg >> 10) & 1; + reg = read_mchbar32(0x400 * channel + 0x581); + setting->pi = (reg >> 4) & 0xf; + setting->tap = reg & 0xf; +} + +static void get_ctrlset0(u8 channel, struct dll_setting *setting) +{ + u32 reg; + setting->coarse = 0; + reg = read_mchbar32(0x400 * channel + 0x59c); + setting->clk_delay = (reg >> 24) & 3; + setting->db_sel = (reg >> 20) & 1; + setting->db_en = (reg >> 21) & 1; + reg = read_mchbar32(0x400 * channel + 0x584); + setting->pi = (reg >> 4) & 0xf; + setting->tap = reg & 0xf; +} + +static void get_clkset1(u8 channel, struct dll_setting *setting) +{ + u32 reg; + setting->coarse = 0; + reg = read_mchbar32(0x400 * channel + 0x5a0); + setting->clk_delay = (reg >> 16) & 3; + setting->db_sel = (reg >> 7) & 1; + setting->db_en = (reg >> 11) & 1; + reg = read_mchbar32(0x400 * channel + 0x582); + setting->pi = (reg >> 4) & 0xf; + setting->tap = reg & 0xf; +} + +static void get_cmdset(u8 channel, struct dll_setting *setting) +{ + u32 reg; + setting->coarse = 0; + reg = read_mchbar32(0x400 * channel + 0x598); + setting->clk_delay = (reg >> 4) & 3; + reg = read_mchbar32(0x400 * channel + 0x594); + setting->db_sel = (reg >> 5) & 1; + setting->db_en = (reg >> 6) & 1; + reg = read_mchbar32(0x400 * channel + 0x580); + setting->pi = (reg >> 4) & 0xf; + setting->tap = reg & 0xf; +} + +static void get_ctrlset1(u8 channel, struct dll_setting *setting) +{ + u32 reg; + setting->coarse = 0; + reg = read_mchbar32(0x400 * channel + 0x59c); + setting->clk_delay = (reg >> 27) & 3; + setting->db_sel = (reg >> 22) & 1; + setting->db_en = (reg >> 23) & 1; + reg = read_mchbar32(0x400 * channel + 0x585); + setting->pi = (reg >> 4) & 0xf; + setting->tap = reg & 0xf; +} + +static void get_ctrlset2(u8 channel, struct dll_setting *setting) +{ + u32 reg; + setting->coarse = 0; + reg = read_mchbar32(0x400 * channel + 0x598); + setting->clk_delay = (reg >> 14) & 3; + setting->db_sel = (reg >> 12) & 1; + setting->db_en = (reg >> 13) & 1; + reg = read_mchbar32(0x400 * channel + 0x586); + setting->pi = (reg >> 4) & 0xf; + setting->tap = reg & 0xf; +} + +static void get_ctrlset3(u8 channel, struct dll_setting *setting) +{ + u32 reg; + setting->coarse = 0; + reg = read_mchbar32(0x400 * channel + 0x598); + setting->clk_delay = (reg >> 10) & 3; + setting->db_sel = (reg >> 8) & 1; + setting->db_en = (reg >> 9) & 1; + reg = read_mchbar32(0x400 * channel + 0x587); + setting->pi = (reg >> 4) & 0xf; + setting->tap = reg & 0xf; +} + +static void get_dqs(u8 channel, u8 rank, u8 lane, struct dll_setting *setting) +{ + u32 reg; + setting->coarse = (read_mchbar32(0x400 * channel + 0x5fc) >> (lane * 4 +1) & 1); + reg = read_mchbar32(0x400 * channel + rank * 4 + 0x5b4); + setting->db_sel = (reg >> lane) & 1; + setting->db_en = (reg >> (9 + lane)) & 1; + reg = read_mchbar32(0x400 * channel + rank * 4 + 0x5c8); + setting->clk_delay = (reg >> (16 + lane * 2)) & 3; + reg = read_mchbar32(0x400 * channel + rank + lane * 4 + 0x520); + setting->pi = (reg >> 4) & 0xf; + setting->tap = reg & 0xf; +} + +static void get_dq(u8 channel, u8 rank, u8 lane, struct dll_setting *setting) +{ + u32 reg; + setting->coarse = (read_mchbar32(0x400 * channel + 0x5fc) >> (lane * 4) & 1); + reg = read_mchbar32(0x400 * channel + rank * 4 + 0x5a4); + setting->db_sel = (reg >> lane) & 1; + setting->db_en = (reg >> (9 + lane)) & 1; + reg = read_mchbar32(0x400 * channel + rank * 4 + 0x5c8); + setting->clk_delay = (reg >> (lane * 2)) & 3; + reg = read_mchbar32(0x400 * channel + rank + lane * 4 + 0x500); + setting->pi = (reg >> 4) & 0xf; + setting->tap = reg & 0xf; +} + +void x4x_dump_timings(void) +{ + u32 reg = 0; + + printf("\nG45 Memory controller settings\n==============================\n\n"); + printf("Programmed timings:\n"); + switch (read_mchbar32(0xc00) & 0x7) { + case 0: + reg = 1066; + break; + case 2: + reg = 800; + break; + case 4: + reg = 1333; + break; + default: + printf("Unsupported FSB frequency.\n"); + break; + } + if (reg) + printf("\tFSB freq : %dMHZ\n", reg); + + u32 mem_clk = (read_mchbar32(0xc00) & 0x70) >> 4; + switch (mem_clk) { + case 0: + reg = 400; + break; + case 1: + reg = 533; + break; + case 2: + reg = 667; + break; + case 3: + reg = 800; + break; + case 4: + reg = 1066; + break; + case 5: + reg = 1333; + break; + default: + printf("Unsupported MEM frequency.\n"); + break; + } + if (reg) + printf("\tMEM freq : %dMT\n", reg); + + int is_ddr3 = (read_mchbar32(0x1a8) & 4) >> 2; + printf("\tDDR TYPE : %d\n", is_ddr3 ? 3 : 2); + + u8 tcas, tras, twl, twr, trrd, trp, trfc, trcd, twtr, trtp; + + for (int channel = 0; channel < 2; channel++) { + tcas = (read_mchbar32(0x240 + 0x400 * channel) & 0xf) + 3; + tras = read_mchbar32(0x25d + 0x400 * channel) & 0x3f; + twl = is_ddr3 ? (mem_clk - 3 + 5) : (tcas - 1U); + twr = ((read_mchbar32(0x250 + 0x400 * channel) >> 6) & 0x3f) - twl - 4; + trrd = (read_mchbar32(0x252 + 0x400 * channel) >> 17) & 0x1f; + trp = (read_mchbar32(0x252 + 0x400 * channel) >> 13) & 0x1f; + trfc = read_mchbar32(0x252 + 0x400 * channel) & 0x1ff; + trcd = (read_mchbar32(0x256 + 0x400 * channel) >> 12) & 0xf; + twtr = ((read_mchbar32(0x258 + 0x400 * channel) >> 12) & 0x1f) - 4 - twl; + trtp = ((read_mchbar32(0x250 + 0x400 * channel) >> 2) & 0xf) - 2; + + printf("Channel %d\n", channel); + printf("\ttCAS: %d\n", tcas); + printf("\ttRAS: %d\n", tras); + printf("\ttRP : %d\n", trp); + printf("\ttRCD: %d\n", trcd); + printf("\ttWR : %d\n", twr); + printf("\ttRFC: %d\n", trfc); + printf("\ttWTR: %d\n", twtr); + printf("\ttRRD: %d\n", trrd); + printf("\ttRTP: %d\n", trtp); + printf("\ttWL : %d\n", twl); + } + printf("\nProgrammed delays:\n"); + for (int channel = 0; channel < 2; channel++) { + printf("Channel %d\n", channel); + struct dll_setting setting; + char s[20]; + get_clkset0(channel, &setting); + print_dll_setting("clkset0 ", &setting); + get_ctrlset0(channel, &setting); + print_dll_setting("ctrlset0", &setting); + get_clkset1(channel, &setting); + print_dll_setting("clkset1 ", &setting); + get_cmdset(channel, &setting); + print_dll_setting("cmdset ", &setting); + get_ctrlset1(channel, &setting); + print_dll_setting("ctrlset1", &setting); + get_ctrlset2(channel, &setting); + print_dll_setting("ctrlset2", &setting); + get_ctrlset3(channel, &setting); + print_dll_setting("ctrlset3", &setting); + for (int lane = 0; lane < 8; lane++) { + sprintf(s, "DQS%d ", lane); + /* All rank should be programmed the same */ + get_dqs(channel, 0, lane, &setting); + print_dll_setting(s, &setting); + } + for (int lane = 0; lane < 8; lane++) { + sprintf(s, "DQ%d ", lane); + /* All rank should be programmed the same */ + get_dq(channel, 0, lane, &setting); + print_dll_setting(s, &setting); + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/35812 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8816a3eb43b9a27ea09997e9cc0407c519485943 Gerrit-Change-Number: 35812 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: [TEST_ONLY]:mb/google/hatch/variants/baseboard: Update tcc_offset value
by Sumeet R Pawnikar (Code Review) 10 Jun '23

10 Jun '23

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36748 ) Change subject: [TEST_ONLY]:mb/google/hatch/variants/baseboard: Update tcc_offset value ...................................................................... [TEST_ONLY]:mb/google/hatch/variants/baseboard: Update tcc_offset value Update tcc_offset value to 5 degree C to test this on i7 Helios systems. Change-Id: Ie319bf1460a5bdeeb86bdf579a24103cac273295 --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/36748/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index a2831e1..386df3b 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -45,7 +45,7 @@ # Enable HPD for DDI ports B/C register "DdiPortBHpd" = "1" register "DdiPortCHpd" = "1" - register "tcc_offset" = "10" # TCC of 90C + register "tcc_offset" = "5" # TCC of 95C # Unlock GPIO pads register "PchUnlockGpioPads" = "1" # SD card WP pin confguration -- To view, visit https://review.coreboot.org/c/coreboot/+/36748 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie319bf1460a5bdeeb86bdf579a24103cac273295 Gerrit-Change-Number: 36748 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: Start VBOOT in bootblock
by Arthur Heymans (Code Review) 10 Jun '23

10 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36926 ) Change subject: nb/intel/sandybridge: Start VBOOT in bootblock ...................................................................... nb/intel/sandybridge: Start VBOOT in bootblock This also puts romstage in RW fmap regions. Change-Id: Ie79fd70f45d115ead6bb0b238ccea1897ceec2f6 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/sandybridge/Kconfig 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/36926/1 diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 0502b50..2ef6299 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -24,7 +24,8 @@ if NORTHBRIDGE_INTEL_SANDYBRIDGE config VBOOT - select VBOOT_STARTS_IN_ROMSTAGE + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE config USE_NATIVE_RAMINIT bool "Use native raminit" -- To view, visit https://review.coreboot.org/c/coreboot/+/36926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie79fd70f45d115ead6bb0b238ccea1897ceec2f6 Gerrit-Change-Number: 36926 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: [TESTONLY]nb/intel/x4x: force COMMAND 2N mode
by Arthur Heymans (Code Review) 10 Jun '23

10 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36829 ) Change subject: [TESTONLY]nb/intel/x4x: force COMMAND 2N mode ...................................................................... [TESTONLY]nb/intel/x4x: force COMMAND 2N mode Change-Id: I4348ecdcdf07b025dccd68aae2c1d2599cbdd4f2 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/raminit_ddr23.c 1 file changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/36829/1 diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index efdcbb6..3626497 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -234,13 +234,13 @@ /* Default 2N mode */ s->nmode = 2; - if (s->selected_timings.mem_clk <= MEM_CLOCK_1066MHz) - s->nmode = 1; - /* 2N on DDR3 1066 with with 2 dimms per channel */ - if ((s->selected_timings.mem_clk == MEM_CLOCK_1066MHz) && - (BOTH_DIMMS_ARE_POPULATED(s->dimms, 0) || - BOTH_DIMMS_ARE_POPULATED(s->dimms, 1))) - s->nmode = 2; + /* if (s->selected_timings.mem_clk <= MEM_CLOCK_1066MHz) */ + /* s->nmode = 1; */ + /* /\* 2N on DDR3 1066 with with 2 dimms per channel *\/ */ + /* if ((s->selected_timings.mem_clk == MEM_CLOCK_1066MHz) && */ + /* (BOTH_DIMMS_ARE_POPULATED(s->dimms, 0) || */ + /* BOTH_DIMMS_ARE_POPULATED(s->dimms, 1))) */ + /* s->nmode = 2; */ launch1 = ddr3_launch1_tab[s->nmode - 1] [s->selected_timings.mem_clk - MEM_CLOCK_800MHz]; launch2 = ddr3_launch2_tab[s->nmode - 1] -- To view, visit https://review.coreboot.org/c/coreboot/+/36829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4348ecdcdf07b025dccd68aae2c1d2599cbdd4f2 Gerrit-Change-Number: 36829 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: TEST ONLY: DO NOT MERGE
by Casper Chang (Code Review) 10 Jun '23

10 Jun '23

Casper Chang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36766 ) Change subject: TEST ONLY: DO NOT MERGE ...................................................................... TEST ONLY: DO NOT MERGE Change-Id: I53ef63261537acdaf74edc13047a3e5e499e749f --- A src/mainboard/google/kukui/TESTONLY 1 file changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/36766/1 diff --git a/src/mainboard/google/kukui/TESTONLY b/src/mainboard/google/kukui/TESTONLY new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/google/kukui/TESTONLY -- To view, visit https://review.coreboot.org/c/coreboot/+/36766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53ef63261537acdaf74edc13047a3e5e499e749f Gerrit-Change-Number: 36766 Gerrit-PatchSet: 1 Gerrit-Owner: Casper Chang <casper.chang(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8183: Always run full calibration for debug DRAM issue...
by huayang duan (Code Review) 10 Jun '23

10 Jun '23

huayang duan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36906 ) Change subject: soc/mediatek/mt8183: Always run full calibration for debug DRAM issue [DONOT MERGE] Disable fast calibration, that is always run full calibration for debug DRAM bitfilp issue. ...................................................................... soc/mediatek/mt8183: Always run full calibration for debug DRAM issue [DONOT MERGE] Disable fast calibration, that is always run full calibration for debug DRAM bitfilp issue. BUG=b:80501386,b:142358843 BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: I693cfe98ea4317c4b856e9bb1f18046a10fe72f8 --- M src/soc/mediatek/mt8183/memory.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/36906/1 diff --git a/src/soc/mediatek/mt8183/memory.c b/src/soc/mediatek/mt8183/memory.c index 13c3d9a..fafe2a6 100644 --- a/src/soc/mediatek/mt8183/memory.c +++ b/src/soc/mediatek/mt8183/memory.c @@ -170,6 +170,11 @@ if (CONFIG(MT8183_DRAM_DVFS) && !recovery_mode) config |= DRAMC_CONFIG_DVFS; + +printk(BIOS_ERR, "DRAM-K: Force disable Fast Calibration for debug DRAM issue\n"); + +// disable fast calibration for debug DRAM issue +if (0) { /* Load calibration params from flash and run fast calibration */ if (recovery_mode) { printk(BIOS_WARNING, "Skip loading cached calibration data\n"); @@ -195,6 +200,7 @@ printk(BIOS_WARNING, "Failed to read calibration data from flash\n"); } +} /* Run full calibration */ printk(BIOS_INFO, "DRAM-K: Full Calibration\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/36906 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I693cfe98ea4317c4b856e9bb1f18046a10fe72f8 Gerrit-Change-Number: 36906 Gerrit-PatchSet: 1 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: amd/bettong: Enable SATA controller
by Jorge Fernandez (Code Review) 10 Jun '23

10 Jun '23

Jorge Fernandez has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37618 ) Change subject: amd/bettong: Enable SATA controller ...................................................................... amd/bettong: Enable SATA controller A minor typo fixed and the SATA controller is enabled on FCH reset. Change-Id: Ib5a66a99379f53b7376dd69e58bb4c1cb082f20b Signed-off-by: Jorge Fernandez <jorgefm(a)cirsa.com> --- M src/mainboard/amd/bettong/BiosCallOuts.c 1 file changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/37618/1 diff --git a/src/mainboard/amd/bettong/BiosCallOuts.c b/src/mainboard/amd/bettong/BiosCallOuts.c index e983690..3d2aa48 100644 --- a/src/mainboard/amd/bettong/BiosCallOuts.c +++ b/src/mainboard/amd/bettong/BiosCallOuts.c @@ -60,7 +60,7 @@ */ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) { - /* Enable IMC fan control. the recommand way */ + /* Enable IMC fan control. the recommended way */ imc_reg_init(); FchParams->Imc.ImcEnable = TRUE; @@ -87,6 +87,10 @@ FchParams_reset->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); FchParams_reset->FchReset.Xhci1Enable = FALSE; FchParams_reset->EarlyOemGpioTable = oem_bettong_gpio; + + /* SATA configuration */ + FchParams_reset->FchReset.SataEnable = TRUE; + } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); @@ -103,7 +107,6 @@ FchParams_env->Usb.Xhci1Enable = FALSE; FchParams_env->Usb.USB30PortInit = 8; /* 8: If USB3 port is unremoveable. */ - /* sata configuration */ /* SD configuration */ /* Rev F has an on-board eMMC, which only supports SD 2.0 */ if (board_id() == 'F') { -- To view, visit https://review.coreboot.org/c/coreboot/+/37618 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5a66a99379f53b7376dd69e58bb4c1cb082f20b Gerrit-Change-Number: 37618 Gerrit-PatchSet: 1 Gerrit-Owner: Jorge Fernandez Gerrit-MessageType: newchange

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Change in coreboot[master]: [TEST-ONLY] Enable compliance mode for test
by Peichao Li (Code Review) 10 Jun '23

10 Jun '23

Peichao Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37323 ) Change subject: [TEST-ONLY] Enable compliance mode for test ...................................................................... [TEST-ONLY] Enable compliance mode for test BUG=None TEST=compliance mode test Signed-off-by: Peichao Wang <peichao.wang(a)bitland.corp-partner.google.com> Change-Id: Ieb65c2062352ae12b3355381a14d8ab66677febe --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/37323/1 diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 0713ef4..f533d04 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -218,6 +218,9 @@ ignore_gbe_ltr(); } } + + /* enable compliance mode */ + params->PchEnableComplianceMode = 1; /* Audio */ params->PchHdaDspEnable = config->PchHdaDspEnable; -- To view, visit https://review.coreboot.org/c/coreboot/+/37323 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb65c2062352ae12b3355381a14d8ab66677febe Gerrit-Change-Number: 37323 Gerrit-PatchSet: 1 Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [TEST]cpu/x86/mp_init: Park APs in C7
by Nico Huber (Code Review) 10 Jun '23

10 Jun '23

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37007 ) Change subject: [TEST]cpu/x86/mp_init: Park APs in C7 ...................................................................... [TEST]cpu/x86/mp_init: Park APs in C7 Change-Id: I960871450407ade6e8f18e69921ce74aa7fbca24 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/cpu/x86/mp_init.c 1 file changed, 16 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/37007/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 29ae3de..16435fc 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -184,7 +184,22 @@ static void park_this_cpu(void *unused) { - stop_this_cpu(); + /* need some address of write-back memory, use AP's stack for now */ + const struct cpu_info *const info = cpu_info(); + const uintptr_t stack_bottom = ALIGN_DOWN((uintptr_t)&_estack, CONFIG_STACK_SIZE) + - (info->index + 1) * CONFIG_STACK_SIZE; + asm volatile( + "xor %%ecx, %%ecx\n\t" + "xor %%edx, %%edx\n" + "__monitor:\n\t" + "mov %0, %%eax\n\t" + "monitor\n\t" + "mov $0x60, %%eax\n\t" + "mwait\n\t" + "jmp __monitor\n\t" + : + : "r" (stack_bottom) + : "eax", "ecx", "edx"); } /* By the time APs call ap_init() caching has been setup, and microcode has -- To view, visit https://review.coreboot.org/c/coreboot/+/37007 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I960871450407ade6e8f18e69921ce74aa7fbca24 Gerrit-Change-Number: 37007 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: New PCI ID for FCH SATA Controller (AHCI Mode) for AMD driver.
by Name of user not set (Code Review) 10 Jun '23

10 Jun '23

Name of user not set #1002701 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37551 ) Change subject: New PCI ID for FCH SATA Controller (AHCI Mode) for AMD driver. ...................................................................... New PCI ID for FCH SATA Controller (AHCI Mode) for AMD driver. The 1022:7904 FCH SATA Controller is found in the AMD Bettong board. Support is added to configure properly the SATA device in initialization. SATA Controller has different device IDs for different drivers. They are renamed accordingly. Change-Id: Icdede188c82bfe8964c32fe81bdf6a3a6a17096c Signed-off-by: Jorge Fernandez <jorgefm(a)cirsa.com> --- M src/include/device/pci_ids.h M src/soc/amd/common/block/sata/sata.c M src/southbridge/amd/pi/hudson/sata.c 3 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/37551/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 1276994..853e910 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -447,8 +447,8 @@ #define PCI_DEVICE_ID_AMD_CZ_HDA 0x157A #define PCI_DEVICE_ID_AMD_CZ_LPC 0x790E -#define PCI_DEVICE_ID_AMD_CZ_SATA 0x7900 -#define PCI_DEVICE_ID_AMD_CZ_SATA_AHCI 0x7901 +#define PCI_DEVICE_ID_AMD_CZ_SATA_IDE 0x7900 +#define PCI_DEVICE_ID_AMD_CZ_SATA_AHCI_MS 0x7901 #define PCI_DEVICE_ID_AMD_CZ_SATA_AHCI_AMD 0x7904 #define PCI_DEVICE_ID_AMD_CZ_USB_0 0x7907 #define PCI_DEVICE_ID_AMD_CZ_USB_1 0x7908 diff --git a/src/soc/amd/common/block/sata/sata.c b/src/soc/amd/common/block/sata/sata.c index 1cd342e..b276809 100644 --- a/src/soc/amd/common/block/sata/sata.c +++ b/src/soc/amd/common/block/sata/sata.c @@ -28,8 +28,8 @@ }; static const unsigned short pci_device_ids[] = { - PCI_DEVICE_ID_AMD_CZ_SATA, - PCI_DEVICE_ID_AMD_CZ_SATA_AHCI, + PCI_DEVICE_ID_AMD_CZ_SATA_IDE, + PCI_DEVICE_ID_AMD_CZ_SATA_AHCI_MS, PCI_DEVICE_ID_AMD_CZ_SATA_AHCI_AMD, 0 }; diff --git a/src/southbridge/amd/pi/hudson/sata.c b/src/southbridge/amd/pi/hudson/sata.c index 77365ef..5846a45 100644 --- a/src/southbridge/amd/pi/hudson/sata.c +++ b/src/southbridge/amd/pi/hudson/sata.c @@ -68,8 +68,8 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_AMD_SB900_SATA, PCI_DEVICE_ID_AMD_SB900_SATA_AHCI, - PCI_DEVICE_ID_AMD_CZ_SATA, - PCI_DEVICE_ID_AMD_CZ_SATA_AHCI, + PCI_DEVICE_ID_AMD_CZ_SATA_IDE, + PCI_DEVICE_ID_AMD_CZ_SATA_AHCI_MS, PCI_DEVICE_ID_AMD_CZ_SATA_AHCI_AMD, 0 }; -- To view, visit https://review.coreboot.org/c/coreboot/+/37551 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdede188c82bfe8964c32fe81bdf6a3a6a17096c Gerrit-Change-Number: 37551 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002701 Gerrit-MessageType: newchange

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