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Change in coreboot[master]: util/bincfg: Add MAC address example to gbe-ich9m.set
by Evgeny Zinoviev (Code Review) 09 Feb '21

09 Feb '21

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39664 ) Change subject: util/bincfg: Add MAC address example to gbe-ich9m.set ...................................................................... util/bincfg: Add MAC address example to gbe-ich9m.set It's not obvious how to set specific byte of a multi-byte field in the set file. Add an example (and a template) for setting MAC address. Change-Id: Iea983071682ffebd61757497d43c70cc8214043d Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M util/bincfg/gbe-ich9m.set 1 file changed, 9 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/39664/1 diff --git a/util/bincfg/gbe-ich9m.set b/util/bincfg/gbe-ich9m.set index 01f85ab..9c5515e 100644 --- a/util/bincfg/gbe-ich9m.set +++ b/util/bincfg/gbe-ich9m.set @@ -84,5 +84,13 @@ "ssdid" = 0x20ee, "ssvid" = 0x17aa, "did" = 0x10f5, - "vid" = 0x8086 + "vid" = 0x8086, + + # MAC address + "macaddress0" = 0, + "macaddress1" = 0, + "macaddress2" = 0, + "macaddress3" = 0, + "macaddress4" = 0, + "macaddress5" = 0 } -- To view, visit https://review.coreboot.org/c/coreboot/+/39664 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea983071682ffebd61757497d43c70cc8214043d Gerrit-Change-Number: 39664 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newchange

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Change in coreboot[master]: Doc/mb/lenovo/montevina_series: Use Makefile to generate IFD
by Evgeny Zinoviev (Code Review) 09 Feb '21

09 Feb '21

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39762 ) Change subject: Doc/mb/lenovo/montevina_series: Use Makefile to generate IFD ...................................................................... Doc/mb/lenovo/montevina_series: Use Makefile to generate IFD util/bincfg's Makefile already has target that generates flash descriptor. Use it instea. Change-Id: I1756514e1ab7b64de23a98314d8a32e9258e648c Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M Documentation/mainboard/lenovo/montevina_series.md 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/39762/1 diff --git a/Documentation/mainboard/lenovo/montevina_series.md b/Documentation/mainboard/lenovo/montevina_series.md index 62e8796..45f2af4 100644 --- a/Documentation/mainboard/lenovo/montevina_series.md +++ b/Documentation/mainboard/lenovo/montevina_series.md @@ -103,9 +103,11 @@ Then create the flash descriptor: ```console -$ ./bincfg ifd-x200.spec ifd-x200.set ifd.bin +$ make gen-ifd-x200 ``` +It will be saved to the `flashregion_0_fd.bin` file. + #### Configuring coreboot Now configure coreboot. You need to select correct chip size and specify paths @@ -118,7 +120,7 @@ Chipset ---> [*] Add Intel descriptor.bin file - # Note: if you used bincfg, specify path to generated util/bincfg/ifd.bin + # Note: if you used bincfg, specify path to generated util/bincfg/flashregion_0_fd.bin (/path/to/flashregion_0_flashdescriptor.bin) Path and filename of the descriptor.bin file [*] Add gigabit ethernet configuration -- To view, visit https://review.coreboot.org/c/coreboot/+/39762 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1756514e1ab7b64de23a98314d8a32e9258e648c Gerrit-Change-Number: 39762 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation: Use correct MiB units instead of MB
by Evgeny Zinoviev (Code Review) 09 Feb '21

09 Feb '21

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39685 ) Change subject: Documentation: Use correct MiB units instead of MB ...................................................................... Documentation: Use correct MiB units instead of MB Fix a common mistake of using MB where MiB is what actually is meant. 1 MB = (10^3)^2 = 1000000 1 MiB = (2^10)^2 = 1048576 Change-Id: I78327652b6c6526318071a9d4bafd7ec279ea614 Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M Documentation/ifdtool/layout.md M Documentation/mainboard/facebook/monolith.md M Documentation/mainboard/hp/8760w.md M Documentation/mainboard/intel/kblrvp11.md M Documentation/mainboard/lenovo/montevina_series.md M Documentation/mainboard/lenovo/t440p.md M Documentation/mainboard/msi/ms7707/ms7707.md M Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md 8 files changed, 21 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/39685/1 diff --git a/Documentation/ifdtool/layout.md b/Documentation/ifdtool/layout.md index 2513929..77319b8 100644 --- a/Documentation/ifdtool/layout.md +++ b/Documentation/ifdtool/layout.md @@ -19,7 +19,7 @@ | IFD Region | IFD Region name | FMAP Name | Notes | | index | | | | +============+==================+===========+===========================================+ -| 0 | Flash Descriptor | SI_DESC | Always the top 4KB of flash | +| 0 | Flash Descriptor | SI_DESC | Always the top 4 KiB of flash | +------------+------------------+-----------+-------------------------------------------+ | 1 | BIOS | SI_BIOS | This is the region that contains coreboot | +------------+------------------+-----------+-------------------------------------------+ @@ -40,9 +40,9 @@ The ifdtool can be used to manipulate a firmware image with a IFD. This tool will not take into account the FMAP while modifying the image which can lead to unexpected and hard to debug issues with the firmware image. For example if the -ME region is defined at 6 MB in the IFD but the FMAP only allocates 4 MB for the -ME, then when the ME is added by the ifdtool 6 MB will be written which could -overwrite 2 MB of the BIOS. +ME region is defined at 6 MiB in the IFD but the FMAP only allocates 4 MiB for +the ME, then when the ME is added by the ifdtool 6 MiB will be written which +could overwrite 2 MiB of the BIOS. In order to validate that the FMAP and the IFD are compatible the ifdtool provides --validate (-t) option. `ifdtool -t` will read both the IFD and the @@ -75,4 +75,4 @@ FMAP area SI_PDR: offset: 0x007fc000 length: 0x00004000 -``` \ No newline at end of file +``` diff --git a/Documentation/mainboard/facebook/monolith.md b/Documentation/mainboard/facebook/monolith.md index cdd3208..a775395 100644 --- a/Documentation/mainboard/facebook/monolith.md +++ b/Documentation/mainboard/facebook/monolith.md @@ -41,8 +41,8 @@ 00003000:006FFFFF me 00001000:00002fff gbe ``` -3) Use `ifdtool -n <layout_file> <flash_image>` to resize the *bios* region from the default 6MB - to 9 MB, this is required to create sufficient space for LinuxBoot. +3) Use `ifdtool -n <layout_file> <flash_image>` to resize the *bios* region from the default 6 MiB + to 9 MiB, this is required to create sufficient space for LinuxBoot. NOTE: Please make sure only the firmware descriptor (*fd*) region is changed. Older versions of the ifdtool corrupt the *me* region. 4) Use `ifdtool -x <resized_flash_image>` to extract the components. diff --git a/Documentation/mainboard/hp/8760w.md b/Documentation/mainboard/hp/8760w.md index 714745a..7e5c0ca 100644 --- a/Documentation/mainboard/hp/8760w.md +++ b/Documentation/mainboard/hp/8760w.md @@ -33,7 +33,7 @@ ## Flashing instructions -HP EliteBook 8760w has an 8MB SOIC-8 flash chip on the bottom of the +HP EliteBook 8760w has an 8 MiB SOIC-8 flash chip on the bottom of the mainboard. You just need to remove the service cover, and use an SOIC-8 clip to read and flash the chip. diff --git a/Documentation/mainboard/intel/kblrvp11.md b/Documentation/mainboard/intel/kblrvp11.md index 4ccb392..d536bea 100644 --- a/Documentation/mainboard/intel/kblrvp11.md +++ b/Documentation/mainboard/intel/kblrvp11.md @@ -60,7 +60,7 @@ 2. Make sure power supply is disconnected from board. 3. Connect Dediprog SF600 to header at J7H1. 4. Ensure that "currently working on" is in "application memory chip 1" -5. Go to "file" and select the .rom file (16 MB) to program chip1. +5. Go to "file" and select the .rom file (16 MiB) to program chip1. 6. Execute the batch operation to erase and program the chip. ## Technology diff --git a/Documentation/mainboard/lenovo/montevina_series.md b/Documentation/mainboard/lenovo/montevina_series.md index 62e8796..94836d5 100644 --- a/Documentation/mainboard/lenovo/montevina_series.md +++ b/Documentation/mainboard/lenovo/montevina_series.md @@ -44,7 +44,7 @@ ```eval_rst +---------------------------+---------------------------+---------------------------+ -| 4 MB chip | 8 MB chip | 16 MB chip | +| 4 MiB chip | 8 MiB chip | 16 MiB chip | +===========================+===========================+===========================+ | .. code-block:: none | .. code-block:: none | .. code-block:: none | | | | | @@ -88,12 +88,12 @@ $ make ``` -If your flash is not 8 MB, you need to change values of `flcomp_density1` and +If your flash is not 8 MiB, you need to change values of `flcomp_density1` and `flreg1_limit` in the ifd-x200.set file according to following table: ```eval_rst +-----------------+-------+-------+--------+ -| | 4 MB | 8 MB | 16 MB | +| | 4 MiB | 8 MiB | 16 MiB | +=================+=======+=======+========+ | flcomp_density1 | 0x3 | 0x4 | 0x5 | +-----------------+-------+-------+--------+ @@ -114,7 +114,7 @@ ``` Mainboard ---> ROM chip size (8192 KB (8 MB)) # According to your chip - (0x7fd000) Size of CBFS filesystem in ROM # or 0x3fd000 for 4 MB chip / 0x1ffd000 for 16 MB chip + (0x7fd000) Size of CBFS filesystem in ROM # or 0x3fd000 for 4 MiB chip / 0x1ffd000 for 16 MiB chip Chipset ---> [*] Add Intel descriptor.bin file @@ -142,7 +142,7 @@ ```eval_rst +---------------------------------+---------------------------------+ -| 4 MB chip | 8 MB chip | +| 4 MiB chip | 8 MiB chip | +=================================+=================================+ | .. code-block:: none | .. code-block:: none | | | | @@ -159,6 +159,6 @@ On each boot of vendor BIOS `ec` area in flash is checked for having firmware there, and if there is one, it proceedes to update firmware on H8S/2116 (when both external power and main battery are attached). Once update is performed, -first 64 KB of `ec` area is erased. Visit +first 64 KiB of `ec` area is erased. Visit [thinkpad-ec repository](https://github.com/hamishcoleman/thinkpad-ec) to learn more about how to extract EC firmware from vendor updates. diff --git a/Documentation/mainboard/lenovo/t440p.md b/Documentation/mainboard/lenovo/t440p.md index fb01870..ffc5808 100644 --- a/Documentation/mainboard/lenovo/t440p.md +++ b/Documentation/mainboard/lenovo/t440p.md @@ -8,15 +8,15 @@ ## Flashing instructions -T440p has two flash chips, an 8MB W25Q64FV and a 4MB W25Q32FV. To flash +T440p has two flash chips, an 8 MiB W25Q64FV and a 4 MiB W25Q32FV. To flash coreboot, you just need to remove the big door according to the T440 -[Hardware Maintenance Manual] and flash the 4MB chip. +[Hardware Maintenance Manual] and flash the 4 MiB chip. ![T440p flash chip](t440p_flash_chip.jpg) -To access the 8MB chip, you need to remove the base cover. +To access the 8 MiB chip, you need to remove the base cover. -![T440p 8MB flash chip](t440p_all_flash_chips.jpg) +![T440p 8 MiB flash chip](t440p_all_flash_chips.jpg) The flash layout of the OEM firmware is as follows: diff --git a/Documentation/mainboard/msi/ms7707/ms7707.md b/Documentation/mainboard/msi/ms7707/ms7707.md index c27ff60..83b860c 100644 --- a/Documentation/mainboard/msi/ms7707/ms7707.md +++ b/Documentation/mainboard/msi/ms7707/ms7707.md @@ -2,7 +2,7 @@ * MSI MS-7707 V1.1 (Medion OEM Akoya P4385D MSN10014555) * SandyBridge Intel P67 (BD82x6x) -* Winbond 25Q32BV (4MB) +* Winbond 25Q32BV (4 MiB) * Fintek F71808A SuperIO * Intel 82579V Gigabit * NEC uPD720200 USB 3.0 Host Controller diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md index 2cb945a..56ec4be 100644 --- a/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md +++ b/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md @@ -17,7 +17,7 @@ ## De-blobbing - [Intel FSP2.0] can not be removed as long as there is no free replacement -- Intel ME can be cleaned using me_cleaner (~4.5 MB more free space) +- Intel ME can be cleaned using me_cleaner (~4.5 MiB more free space) - Intel Ethernet Controller Firmware can be removed when it's extended functionality is not needed. For more details refer to the respective datasheet (e.g 333016-008 for I210). - Boards with [AST2400] BMC/IPMI: Firmware can be replaced by [OpenBMC] -- To view, visit https://review.coreboot.org/c/coreboot/+/39685 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78327652b6c6526318071a9d4bafd7ec279ea614 Gerrit-Change-Number: 39685 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/apple/macbook21: Use common ACPI code
by Evgeny Zinoviev (Code Review) 09 Feb '21

09 Feb '21

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33104 Change subject: mb/apple/macbook21: Use common ACPI code ...................................................................... mb/apple/macbook21: Use common ACPI code Use common ACPI code from ec/apple to avoid duplication between boards. Change-Id: I790d1353adea432e9697c5edf0dbb7841d308728 Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M src/mainboard/apple/macbook21/acpi/ec.asl 1 file changed, 5 insertions(+), 232 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/33104/1 diff --git a/src/mainboard/apple/macbook21/acpi/ec.asl b/src/mainboard/apple/macbook21/acpi/ec.asl index 0a8ebca..bd56af5 100644 --- a/src/mainboard/apple/macbook21/acpi/ec.asl +++ b/src/mainboard/apple/macbook21/acpi/ec.asl @@ -1,6 +1,8 @@ /* * This file is part of the coreboot project. * + * Copyright (c) 2019 Evgeny Zinoviev <me(a)ch1p.io> + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -11,235 +13,6 @@ * GNU General Public License for more details. */ -Device(EC) -{ - Name(_HID, EISAID("PNP0C09")) - Name(_UID, 0) - - Name(_GPE, 0x17) - Mutex(ECLK, 0) - - OperationRegion(ERAM, EmbeddedControl, 0x00, 0x100) - Field(ERAM, ByteAcc, NoLock, Preserve) - { - Offset(0x01), - LIDS, 1, /* Lid status */ - HPAC, 1, - Offset(0x02), - WKLD, 1, /* Lid wake */ - - Offset(0x20), - SPTR, 8, - SSTS, 8, - SADR, 8, - SCMD, 8, - SBFR, 256, - } - Field(ERAM, ByteAcc, Lock, Preserve) - { - Offset(0x24), - SBDW, 16, - } - - Method(SBPC, 0, NotSerialized) - { - Store(1000, Local0) - While(Local0) - { - If(LEqual(SPTR, 0x00)) - { - Return() - } - - Sleep(1) - Decrement(Local0) - } - } - - Method(SBRW, 2, NotSerialized) - { - Acquire(ECLK, 0xFFFF) - Store(ShiftLeft(Arg0, 0x01), SADR) - Store(Arg1, SCMD) - Store(0x09, SPTR) - SBPC() - Store(SBDW, Local0) - Release(ECLK) - Return(Local0) - } - - Method(SBRB, 2, NotSerialized) - { - Acquire(ECLK, 0xFFFF) - Store(ShiftLeft(Arg0, 0x01), SADR) - Store(Arg1, SCMD) - Store(0x0B, SPTR) - SBPC() - Store(SBFR, Local0) - Release(ECLK) - Return(Local0) - } - - /* LID status change. */ - Method(_Q20, 0, NotSerialized) - { - Notify(LID, 0x80) - } - - /* AC status change. */ - Method(_Q21, 0, NotSerialized) - { - Notify(AC, 0x80) - } - - Method(_CRS, 0) - { - Name(ECMD, ResourceTemplate() - { - IO(Decode16, 0x62, 0x62, 1, 1) - IO(Decode16, 0x66, 0x66, 1, 1) - }) - Return(ECMD) - } - - Method(_INI, 0, NotSerialized) - { - } - - Device(LID) - { - Name(_HID, "PNP0C0D") - - Method(_LID, 0, NotSerialized) - { - return(LIDS) - } - - Method(_PRW, 0, NotSerialized) - { - Return (Package() { 0x1d, 0x03 }) - } - - Method(_PSW, 1, NotSerialized) - { - if (Arg0) { - Store(1, WKLD) - } else { - Store(0, WKLD) - } - } - } - - Device(AC) - { - Name(_HID, "ACPI0003") - Name(_UID, 0x00) - Name(_PCL, Package() { \_SB } ) - - Method(_PSR, 0, NotSerialized) - { - return(HPAC) - } - - Method(_STA, 0, NotSerialized) - { - Return(0x0f) - } - } - - Device(BAT0) - { - Name(_HID, EisaId("PNP0C0A")) - Name(_UID, 0x00) - Name(_PCL, Package() { \_SB }) - - Name(BATS, Package() - { - 0x00, // 0: PowerUnit: Report in mWh - 0xFFFFFFFF, // 1: Design cap - 0xFFFFFFFF, // 2: Last full charge cap - 0x01, // 3: Battery Technology - 10800, // 4: Design Voltage(mV) - 0x00, // 5: Warning design capacity - 200, // 6: Low design capacity - 10, // 7: granularity1 - 10, // 8: granularity2 - "", // 9: Model number - "", // A: Serial number - "", // B: Battery Type - "" // C: OEM information - }) - - Name(BATI, Package() - { - 0, // Battery State - // Bit 0 - discharge - // Bit 1 - charge - // Bit 2 - critical state - 0, // Battery present Rate - 0, // Battery remaining capacity - 0 // Battery present voltage - }) - - Method(_BIF, 0, NotSerialized) - { - Multiply(^^SBRW(0x0B, 0x18), 10, Index(BATS, 0x01)) - Multiply(^^SBRW(0x0B, 0x10), 10, Index(BATS, 0x02)) - Store(^^SBRW(0x0B, 0x19), Index(BATS, 0x04)) - Store(^^SBRB(0x0B, 0x21), Index(BATS, 0x09)) - Store(^^SBRB(0x0B, 0x22), Index(BATS, 0x0B)) - Store(^^SBRB(0x0B, 0x20), Index(BATS, 0x0C)) - - Return(BATS) - } - - Method(_STA, 0, NotSerialized) - { - If(And(^^SBRW(0x0A, 0x01), 0x01)) { - Return(0x1f) - } else { - Return(0x0f) - } - } - - Method(_BST, 0, NotSerialized) - { - /* Check for battery presence. */ - If(LNot(And(^^SBRW(0x0A, 0x01), 0x01))) { - Return(Package(4) { - 0, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF - }) - } - Store(^^SBRW(0x0B, 0x09), Local1) - Store(Local1, Index(BATI, 0x03)) - Store(^^SBRW(0x0B, 0x0A), Local0) - /* Sign-extend Local0. */ - If(And(Local0, 0x8000)) - { - Not(Local0, Local0) - And(Increment(Local0), 0xFFFF, Local0) - } - - Multiply(Local0, Local1, Local0) - Divide(Local0, 1000, , Index(BATI, 1)) - Multiply(^^SBRW(0x0B, 0x0F), 10, Index(BATI, 2)) - If(HPAC) - { - If(LNot(And(^^SBRW(0x0B, 0x16), 0x40))) { - Store(2, Index(BATI, 0)) - } Else { - Store(0, Index(BATI, 0)) - } - } - Else - { - Store(0x01, Index(BATI, 0)) - } - - Return(BATI) - } - } -} +#include <ec/apple/acpi/ec.asl> +#include <ec/apple/acpi/ac_01.asl> +#include <ec/apple/acpi/lid_01.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/33104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I790d1353adea432e9697c5edf0dbb7841d308728 Gerrit-Change-Number: 33104 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/apollolake: Hook up GMA ACPI brightness controls
by Matt DeVillier (Code Review) 08 Feb '21

08 Feb '21

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40593 ) Change subject: soc/intel/apollolake: Hook up GMA ACPI brightness controls ...................................................................... soc/intel/apollolake: Hook up GMA ACPI brightness controls Add struct i915_gpu_controller_info for boards to supply info needed to generate ACPI backlight control SSDT. Hook into soc/common framework by implementing intel_igd_get_controller_info(). Change-Id: Ia62a88b58e7efd90f550000fc5b2cef0cb5fade7 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/apollolake/chip.h M src/soc/intel/apollolake/graphics.c 2 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/40593/1 diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index ac36b70..f69ea11 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -17,6 +17,7 @@ #define _SOC_APOLLOLAKE_CHIP_H_ #include <commonlib/helpers.h> +#include <drivers/intel/gma/i915_gma.h> #include <intelblocks/cfg.h> #include <intelblocks/gspi.h> #include <soc/gpe.h> @@ -192,6 +193,9 @@ * 0:Enable (default), 1:Disable. */ uint8_t disable_xhci_lfps_pm; + + /* i915 struct for GMA backlight control */ + struct i915_gpu_controller_info gfx; }; typedef struct soc_intel_apollolake_config config_t; diff --git a/src/soc/intel/apollolake/graphics.c b/src/soc/intel/apollolake/graphics.c index 797df73..1e3e390 100644 --- a/src/soc/intel/apollolake/graphics.c +++ b/src/soc/intel/apollolake/graphics.c @@ -18,6 +18,7 @@ #include <bootmode.h> #include <cbmem.h> #include <console/console.h> +#include <drivers/intel/gma/i915_gma.h> #include <fsp/util.h> #include <device/device.h> #include <device/pci.h> @@ -27,6 +28,7 @@ #include <drivers/intel/gma/libgfxinit.h> #include <types.h> #include <soc/nvs.h> +#include "chip.h" uintptr_t gma_get_gnvs_aslb(const void *gnvs) @@ -88,3 +90,10 @@ current += sizeof(igd_opregion_t); return acpi_align_current(current); } + +const struct i915_gpu_controller_info * +intel_igd_get_controller_info(struct device *device) +{ + struct soc_intel_apollolake_config *chip = device->chip_info; + return &chip->gfx; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/40593 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia62a88b58e7efd90f550000fc5b2cef0cb5fade7 Gerrit-Change-Number: 40593 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] sb/intel/bd82x6x: Support ME Software Disable Mode
by Evgeny Zinoviev (Code Review) 07 Feb '21

07 Feb '21

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37115 ) Change subject: [WIP] sb/intel/bd82x6x: Support ME Software Disable Mode ...................................................................... [WIP] sb/intel/bd82x6x: Support ME Software Disable Mode AFAIK, ME is supposed to enter Software Temp Disable Mode on the next reboot after receiving the disable command. But my tests on X230 (ME firmware 8.1.1416.40) show that CF9 reset doesn't help here and user must manually perform power off/power on cycle. So for now working algorithm to disable ME is as follows: - run `nvramtool -w me_disable=Enable` - reboot - power off - power on - run `intelmetool -m` to verify that ME is in soft temp disable mode. To enable ME: - run `nvramtool -m me_disable=Disable` - reboot TODO: if it's possible, find a way to perform correct program reset so that user wouldn't have to do one more power off/power on. Change-Id: Ic01526c9731cbef4e8552bbc352133a2415787c2 Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M src/mainboard/lenovo/x230/cmos.default M src/mainboard/lenovo/x230/cmos.layout M src/southbridge/intel/bd82x6x/early_me.c M src/southbridge/intel/bd82x6x/me.h M src/southbridge/intel/bd82x6x/me_8.x.c 5 files changed, 104 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/37115/1 diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default index 979f132..75f27df 100644 --- a/src/mainboard/lenovo/x230/cmos.default +++ b/src/mainboard/lenovo/x230/cmos.default @@ -14,3 +14,4 @@ trackpoint=Enable backlight=Both usb_always_on=Disable +me_disable=Disable diff --git a/src/mainboard/lenovo/x230/cmos.layout b/src/mainboard/lenovo/x230/cmos.layout index 27197fb..755d98b 100644 --- a/src/mainboard/lenovo/x230/cmos.layout +++ b/src/mainboard/lenovo/x230/cmos.layout @@ -73,6 +73,9 @@ # coreboot config options: cpu #424 8 r 0 unused +424 1 e 1 me_disable +425 1 r 0 me_disable_prev +#426 6 r 0 unused # coreboot config options: northbridge 432 3 e 11 gfx_uma_size diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c index f82ed3e..41ca3f6 100644 --- a/src/southbridge/intel/bd82x6x/early_me.c +++ b/src/southbridge/intel/bd82x6x/early_me.c @@ -23,6 +23,7 @@ #include <halt.h> #include <string.h> #include <timestamp.h> +#include <option.h> #include "me.h" #include "pch.h" @@ -236,7 +237,6 @@ printk(BIOS_NOTICE, "ME: Current PM event: 0x%x\n", (me_fws2 & 0xf000000) >> 24); printk(BIOS_NOTICE, "ME: Progress code : 0x%x\n", (me_fws2 & 0xf0000000) >> 28); - /* Return the requested BIOS action */ printk(BIOS_NOTICE, "ME: Requested BIOS Action: %s\n", me_ack_values[(hfs & 0xe) >> 1]); diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h index 203d0c0..e05a178 100644 --- a/src/southbridge/intel/bd82x6x/me.h +++ b/src/southbridge/intel/bd82x6x/me.h @@ -185,6 +185,11 @@ #define MKHI_GLOBAL_RESET 0x0b #define MKHI_FWCAPS_GET_RULE 0x02 +#define MKHI_FWCAPS_SET_RULE 0x03 + +#define MKHI_HMRFPO_ENABLE 0x01 +#define MKHI_HMRFPO_LOCK 0x02 +#define MKHI_HMRFPO_DISABLE 0x04 #define MKHI_MDES_ENABLE 0x09 diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index f13ced9..5d57e02 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -23,6 +23,7 @@ */ #include <arch/acpi.h> +#include <cf9_reset.h> #include <device/mmio.h> #include <device/device.h> #include <device/pci.h> @@ -30,6 +31,7 @@ #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> +#include <pc80/mc146818rtc.h> #include <string.h> #include <delay.h> #include <elog.h> @@ -189,7 +191,7 @@ } static int mei_send_msg(struct mei_header *mei, struct mkhi_header *mkhi, - void *req_data) + void *req_data, bool wait_ready) { struct mei_csr host; unsigned int ndata, n; @@ -247,8 +249,11 @@ host.interrupt_generate = 1; write_host_csr(&host); - /* Make sure ME is ready after sending request data */ - return mei_wait_for_me_ready(); + if (!wait_ready) + return 0; + else + /* Make sure ME is ready after sending request data */ + return mei_wait_for_me_ready(); } static int mei_recv_msg(struct mkhi_header *mkhi, @@ -338,10 +343,12 @@ static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, void *req_data, void *rsp_data, int rsp_bytes) { - if (mei_send_msg(mei, mkhi, req_data) < 0) + if (mei_send_msg(mei, mkhi, req_data, true) < 0) return -1; + if (mei_recv_msg(mkhi, rsp_data, rsp_bytes) < 0) return -1; + return 0; } @@ -513,6 +520,50 @@ } #else /* !__SIMPLE_DEVICE__ */ +static void reset(void) { + struct device *lpc = pcidev_on_root(0x1f, 0); + u32 etr3 = pci_read_config32(lpc, ETR3); + u8 cf9; + + etr3 |= ETR3_CF9GR; + pci_write_config32(lpc, ETR3, etr3); + + cf9 = inb(0xcf9); + cf9 |= 0x0e; + outb(cf9, 0xcf9); + + halt(); +} + +static void enable_soft_temp_disable_mode(void) { + u32 message[2] = { 0x06, 0x01 }; + struct mkhi_header mkhi = { + .group_id = MKHI_GROUP_ID_FWCAPS, + .command = MKHI_FWCAPS_SET_RULE, + }; + struct mei_header mei = { + .is_complete = 1, + .length = sizeof(mkhi) + sizeof(message), + .host_address = MEI_HOST_ADDRESS, + .client_address = MEI_ADDRESS_MKHI, + }; + + printk(BIOS_NOTICE, "ME: %s\n", __FUNCTION__); + + /* + * ME stops responding after receiving the disable command, + * therefore it makes no sence to wait for it + */ + bool wait_ready = false; + + if (mei_send_msg(&mei, &mkhi, &message, wait_ready) < 0) + printk(BIOS_DEBUG, "ME: %s: me_send_msg returned -1 (wait timeout)\n", + __FUNCTION__); +} + +static void disable_soft_temp_disable_mode(struct device *dev) { + pci_write_config32(dev, PCI_ME_H_GS, 0x20000000); +} /* Determine the path that we should take based on ME status */ static me_bios_path intel_me_path(struct device *dev) @@ -675,10 +726,19 @@ { me_bios_path path = intel_me_path(dev); me_bios_payload mbp_data; + u8 me_disable, me_disable_prev; + bool need_reset = false; + struct me_hfs hfs; /* Do initial setup and determine the BIOS path */ printk(BIOS_NOTICE, "ME: BIOS path: %s\n", me_bios_path_values[path]); + get_option(&me_disable, "me_disable"); + get_option(&me_disable_prev, "me_disable_prev"); + + printk(BIOS_DEBUG, "ME: me_disable=%u, me_disable_prev=%u\n", + me_disable, me_disable_prev); + switch (path) { case ME_S3WAKE_BIOS_PATH: intel_me_hide(dev); @@ -710,6 +770,17 @@ } #endif + /* Put ME in Software Temporary Disable Mode, if needed */ + if (me_disable) { + printk(BIOS_DEBUG, "ME: need to disable ME\n"); + enable_soft_temp_disable_mode(); + if (!me_disable_prev) { + printk(BIOS_DEBUG, "ME: me_disable_prev differs, need to reset\n"); + need_reset = true; + break; + } + } + if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) { me_print_fw_version(&mbp_data.fw_version_name); me_print_fwcaps(&mbp_data.fw_caps_sku); @@ -721,12 +792,30 @@ */ break; + case ME_DISABLE_BIOS_PATH: + /* Bring ME out of Softwate Temporary Disable mode, if needed */ + pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS); + if (hfs.operation_mode == ME_HFS_MODE_DIS && !me_disable) { + printk(BIOS_DEBUG, "ME: need to undisable ME\n"); + disable_soft_temp_disable_mode(dev); + if (me_disable_prev) { + printk(BIOS_DEBUG, "ME: me_disable_prev differs, need to reset\n"); + need_reset = true; + } + } + break; + case ME_ERROR_BIOS_PATH: case ME_RECOVERY_BIOS_PATH: - case ME_DISABLE_BIOS_PATH: case ME_FIRMWARE_UPDATE_BIOS_PATH: break; } + + if (me_disable != me_disable_prev) + set_option("me_disable_prev", &me_disable); + + if (need_reset) + reset(); } static struct pci_operations pci_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/37115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic01526c9731cbef4e8552bbc352133a2415787c2 Gerrit-Change-Number: 37115 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newchange

7 60

Change in coreboot[master]: payloads/external/FILO: Pass Libpayloads path on the clean target
by Arthur Heymans (Code Review) 06 Feb '21

06 Feb '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36461 ) Change subject: payloads/external/FILO: Pass Libpayloads path on the clean target ...................................................................... payloads/external/FILO: Pass Libpayloads path on the clean target Change-Id: If5f8f4ecce317e54cd4b5688553cc38220f6e6df Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M payloads/external/FILO/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/36461/1 diff --git a/payloads/external/FILO/Makefile b/payloads/external/FILO/Makefile index a89ea2a..ffb4e1f 100644 --- a/payloads/external/FILO/Makefile +++ b/payloads/external/FILO/Makefile @@ -44,7 +44,7 @@ $(MAKE) && $(MAKE) DESTDIR=../external/FILO/filo/build install clean: - test -d filo && $(MAKE) -C filo clean || exit 0 + test -d filo && $(MAKE) -C filo clean LIBCONFIG_PATH=../../../libpayload || exit 0 distclean: rm -rf filo -- To view, visit https://review.coreboot.org/c/coreboot/+/36461 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5f8f4ecce317e54cd4b5688553cc38220f6e6df Gerrit-Change-Number: 36461 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: sb/intel/bd82x6x: Drop unneeded files from SMM
by Angel Pons (Code Review) 06 Feb '21

06 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42052 ) Change subject: sb/intel/bd82x6x: Drop unneeded files from SMM ...................................................................... sb/intel/bd82x6x: Drop unneeded files from SMM We also drop all `__unused` function attributes on these files. Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical. Change-Id: I37219bddd2ad9b56711508a3d28056863123d769 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/Makefile.inc M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me_8.x.c 3 files changed, 6 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/42052/1 diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index cf9bf50..f83d303 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -25,7 +25,7 @@ ramstage-$(CONFIG_ELOG) += elog.c -smm-y += smihandler.c me.c me_8.x.c pch.c me_common.c +smm-y += smihandler.c pch.c me_common.c romstage-y += early_smbus.c me_status.c romstage-y += early_rcba.c diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index dd3ecd7..38cdb48 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -29,7 +29,7 @@ #endif /* Get ME firmware version */ -static int __unused mkhi_get_fw_version(void) +static int mkhi_get_fw_version(void) { struct me_fw_version version; struct mkhi_header mkhi = { @@ -66,7 +66,7 @@ } /* Get ME Firmware Capabilities */ -static int __unused mkhi_get_fwcaps(void) +static int mkhi_get_fwcaps(void) { u32 rule_id = 0; struct me_fwcaps cap; @@ -109,8 +109,6 @@ return 0; } -#ifndef __SIMPLE_DEVICE__ - /* Determine the path that we should take based on ME status */ static me_bios_path intel_me_path(struct device *dev) { @@ -236,5 +234,3 @@ .vendor = PCI_VENDOR_ID_INTEL, .device = 0x1c3a, }; - -#endif /* __SIMPLE_DEVICE__ */ diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 78f2817..5659f7a 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -34,7 +34,7 @@ name, state ? " en" : "dis"); } -static void __unused me_print_fw_version(mbp_fw_version_name *vers_name) +static void me_print_fw_version(mbp_fw_version_name *vers_name) { if (!vers_name->major_version) { printk(BIOS_ERR, "ME: mbp missing version report\n"); @@ -72,7 +72,7 @@ } /* Get ME Firmware Capabilities */ -static void __unused me_print_fwcaps(mbp_fw_caps *caps_section) +static void me_print_fwcaps(mbp_fw_caps *caps_section) { mefwcaps_sku *cap = &caps_section->fw_capabilities; if (!caps_section->available) { @@ -99,8 +99,6 @@ print_cap("Wireless LAN (WLAN)", cap->wlan); } -#ifndef __SIMPLE_DEVICE__ - /* Determine the path that we should take based on ME status */ static me_bios_path intel_me_path(struct device *dev) { @@ -242,8 +240,6 @@ .device = 0x1e3a, }; -#endif /* !__SIMPLE_DEVICE__ */ - /****************************************************************************** * */ static u32 me_to_host_words_pending(void) @@ -260,7 +256,7 @@ * mbp seems to be following its own flow, let's retrieve it in a dedicated * function. */ -static int __unused intel_me_read_mbp(me_bios_payload *mbp_data) +static int intel_me_read_mbp(me_bios_payload *mbp_data) { mbp_header mbp_hdr; mbp_item_header mbp_item_hdr; -- To view, visit https://review.coreboot.org/c/coreboot/+/42052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37219bddd2ad9b56711508a3d28056863123d769 Gerrit-Change-Number: 42052 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 11

Change in coreboot[master]: sb/intel/bd82x6x: Deduplicate ME finalization function
by Angel Pons (Code Review) 06 Feb '21

06 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42050 ) Change subject: sb/intel/bd82x6x: Deduplicate ME finalization function ...................................................................... sb/intel/bd82x6x: Deduplicate ME finalization function Both functions are identical, so we might as well drop one copy. Change-Id: Ifd24f01dab2b5a6b7d154a8e2b1a69c233a0e727 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me.h M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/bd82x6x/me_common.c 4 files changed, 39 insertions(+), 78 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/42050/1 diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index d2a3480..7910623 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -111,57 +111,20 @@ #ifdef __SIMPLE_DEVICE__ -static void intel_me7_finalize_smm(void) -{ - struct me_hfs hfs; - u32 reg32; - u16 reg16; - - update_mei_base_address(); - - /* S3 path will have hidden this device already */ - if (!is_mei_base_address_valid()) - return; - - /* Make sure ME is in a mode that expects EOP */ - reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS); - memcpy(&hfs, &reg32, sizeof(u32)); - - /* Abort and leave device alone if not normal mode */ - if (hfs.fpt_bad || - hfs.working_state != ME_HFS_CWS_NORMAL || - hfs.operation_mode != ME_HFS_MODE_NORMAL) - return; - - /* Try to send EOP command so ME stops accepting other commands */ - mkhi_end_of_post(); - - /* Make sure IO is disabled */ - reg16 = pci_read_config16(PCH_ME_DEV, PCI_COMMAND); - reg16 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config16(PCH_ME_DEV, PCI_COMMAND, reg16); - - /* Hide the PCI device */ - RCBA32_OR(FD2, PCH_DISABLE_MEI1); -} - void intel_me_finalize_smm(void) { u32 did = pci_read_config32(PCH_ME_DEV, PCI_VENDOR_ID); switch (did) { case 0x1c3a8086: - intel_me7_finalize_smm(); - break; case 0x1e3a8086: - intel_me8_finalize_smm(); + me_finalize_smm(); break; default: printk(BIOS_ERR, "No finalize handler for ME %08x.\n", did); } } -#else +#else /* !__SIMPLE_DEVICE__ */ /* Determine the path that we should take based on ME status */ static me_bios_path intel_me_path(struct device *dev) diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h index a55a1f2..8fee899 100644 --- a/src/southbridge/intel/bd82x6x/me.h +++ b/src/southbridge/intel/bd82x6x/me.h @@ -245,6 +245,7 @@ int mkhi_end_of_post(void); void update_mei_base_address(void); bool is_mei_base_address_valid(void); +void me_finalize_smm(void); int intel_mei_setup(struct device *dev); int intel_me_extend_valid(struct device *dev); void intel_me_hide(struct device *dev); @@ -258,7 +259,6 @@ int intel_early_me_init_done(u8 status); void intel_me_finalize_smm(void); -void intel_me8_finalize_smm(void); typedef struct { u32 major_version : 16; diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 1a331e9..78f2817 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -99,44 +99,7 @@ print_cap("Wireless LAN (WLAN)", cap->wlan); } -#ifdef __SIMPLE_DEVICE__ - -void intel_me8_finalize_smm(void) -{ - struct me_hfs hfs; - u32 reg32; - u16 reg16; - - update_mei_base_address(); - - /* S3 path will have hidden this device already */ - if (!is_mei_base_address_valid()) - return; - - /* Make sure ME is in a mode that expects EOP */ - reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS); - memcpy(&hfs, &reg32, sizeof(u32)); - - /* Abort and leave device alone if not normal mode */ - if (hfs.fpt_bad || - hfs.working_state != ME_HFS_CWS_NORMAL || - hfs.operation_mode != ME_HFS_MODE_NORMAL) - return; - - /* Try to send EOP command so ME stops accepting other commands */ - mkhi_end_of_post(); - - /* Make sure IO is disabled */ - reg16 = pci_read_config16(PCH_ME_DEV, PCI_COMMAND); - reg16 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config16(PCH_ME_DEV, PCI_COMMAND, reg16); - - /* Hide the PCI device */ - RCBA32_OR(FD2, PCH_DISABLE_MEI1); -} - -#else /* !__SIMPLE_DEVICE__ */ +#ifndef __SIMPLE_DEVICE__ /* Determine the path that we should take based on ME status */ static me_bios_path intel_me_path(struct device *dev) diff --git a/src/southbridge/intel/bd82x6x/me_common.c b/src/southbridge/intel/bd82x6x/me_common.c index 83e7fe6..9088d44 100644 --- a/src/southbridge/intel/bd82x6x/me_common.c +++ b/src/southbridge/intel/bd82x6x/me_common.c @@ -361,6 +361,41 @@ return mei_base_address && mei_base_address != (u32 *)0xfffffff0; } +void me_finalize_smm(void) +{ + struct me_hfs hfs; + u32 reg32; + u16 reg16; + + update_mei_base_address(); + + /* S3 path will have hidden this device already */ + if (!is_mei_base_address_valid()) + return; + + /* Make sure ME is in a mode that expects EOP */ + reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS); + memcpy(&hfs, &reg32, sizeof(u32)); + + /* Abort and leave device alone if not normal mode */ + if (hfs.fpt_bad || + hfs.working_state != ME_HFS_CWS_NORMAL || + hfs.operation_mode != ME_HFS_MODE_NORMAL) + return; + + /* Try to send EOP command so ME stops accepting other commands */ + mkhi_end_of_post(); + + /* Make sure IO is disabled */ + reg16 = pci_read_config16(PCH_ME_DEV, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + pci_write_config16(PCH_ME_DEV, PCI_COMMAND, reg16); + + /* Hide the PCI device */ + RCBA32_OR(FD2, PCH_DISABLE_MEI1); +} + #else /* Prepare ME for MEI messages */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd24f01dab2b5a6b7d154a8e2b1a69c233a0e727 Gerrit-Change-Number: 42050 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: sb/intel/bd82x6x: Relocate intel_me_finalize_smm()
by Angel Pons (Code Review) 06 Feb '21

06 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42051 ) Change subject: sb/intel/bd82x6x: Relocate intel_me_finalize_smm() ...................................................................... sb/intel/bd82x6x: Relocate intel_me_finalize_smm() This allows us to reduce the scope of three functions. Change-Id: Ib08c0eb4b01e10aa38efac434ff23a488e9e2787 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me.h M src/southbridge/intel/bd82x6x/me_common.c 3 files changed, 18 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/42051/1 diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 7910623..dd3ecd7 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -109,22 +109,7 @@ return 0; } -#ifdef __SIMPLE_DEVICE__ - -void intel_me_finalize_smm(void) -{ - u32 did = pci_read_config32(PCH_ME_DEV, PCI_VENDOR_ID); - switch (did) { - case 0x1c3a8086: - case 0x1e3a8086: - me_finalize_smm(); - break; - default: - printk(BIOS_ERR, "No finalize handler for ME %08x.\n", did); - } -} - -#else /* !__SIMPLE_DEVICE__ */ +#ifndef __SIMPLE_DEVICE__ /* Determine the path that we should take based on ME status */ static me_bios_path intel_me_path(struct device *dev) diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h index 8fee899..29d5749 100644 --- a/src/southbridge/intel/bd82x6x/me.h +++ b/src/southbridge/intel/bd82x6x/me.h @@ -243,9 +243,7 @@ void *req_data, void *rsp_data, int rsp_bytes); int mkhi_end_of_post(void); -void update_mei_base_address(void); -bool is_mei_base_address_valid(void); -void me_finalize_smm(void); +void intel_me_finalize_smm(void); int intel_mei_setup(struct device *dev); int intel_me_extend_valid(struct device *dev); void intel_me_hide(struct device *dev); @@ -258,8 +256,6 @@ int intel_early_me_uma_size(void); int intel_early_me_init_done(u8 status); -void intel_me_finalize_smm(void); - typedef struct { u32 major_version : 16; u32 minor_version : 16; diff --git a/src/southbridge/intel/bd82x6x/me_common.c b/src/southbridge/intel/bd82x6x/me_common.c index 9088d44..59c0b38 100644 --- a/src/southbridge/intel/bd82x6x/me_common.c +++ b/src/southbridge/intel/bd82x6x/me_common.c @@ -351,17 +351,17 @@ #ifdef __SIMPLE_DEVICE__ -void update_mei_base_address(void) +static inline void update_mei_base_address(void) { mei_base_address = (u32 *)(pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); } -bool is_mei_base_address_valid(void) +static inline bool is_mei_base_address_valid(void) { return mei_base_address && mei_base_address != (u32 *)0xfffffff0; } -void me_finalize_smm(void) +static void me_finalize_smm(void) { struct me_hfs hfs; u32 reg32; @@ -396,6 +396,19 @@ RCBA32_OR(FD2, PCH_DISABLE_MEI1); } +void intel_me_finalize_smm(void) +{ + u32 did = pci_read_config32(PCH_ME_DEV, PCI_VENDOR_ID); + switch (did) { + case 0x1c3a8086: + case 0x1e3a8086: + me_finalize_smm(); + break; + default: + printk(BIOS_ERR, "No finalize handler for ME %08x.\n", did); + } +} + #else /* Prepare ME for MEI messages */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42051 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib08c0eb4b01e10aa38efac434ff23a488e9e2787 Gerrit-Change-Number: 42051 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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coreboot-gerrit June 2020