Change in coreboot[master]: cpu/smm/ssm_stub: Add x86_64 support
by Patrick Rudolph (Code Review) 08 Apr '21
by Patrick Rudolph (Code Review) 08 Apr '21
08 Apr '21
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37392 )
Change subject: cpu/smm/ssm_stub: Add x86_64 support
......................................................................
cpu/smm/ssm_stub: Add x86_64 support
Enable long mode in SMM handler.
x86_32 isn't affected from this change.
* Enter long mode
* Add 64bit entry to GDT
* Use x86_64 SysV ABI calling conventions for C code entry
* Change smm_module_params' cpu to size_t as 'push' is native integer
Tested on Lenovo T410 with additional x86_64 patches.
Change-Id: I26300492e4be62ddd5d80525022c758a019d63a1
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/cpu/x86/smm/smm_stub.S
M src/include/cpu/x86/smm.h
2 files changed, 25 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/37392/1
diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S
index f0e55f9..3feee9b 100644
--- a/src/cpu/x86/smm/smm_stub.S
+++ b/src/cpu/x86/smm/smm_stub.S
@@ -90,6 +90,10 @@
/* gdt selector 0x10, flat data segment */
.word 0xffff, 0x0000
.byte 0x00, 0x93, 0xcf, 0x00
+
+ /* gdt selector 0x18, flat code segment (64-bit) */
+ .word 0xffff, 0x0000
+ .byte 0x00, 0x9b, 0xaf, 0x00
smm_relocate_gdt_end:
.align 4
@@ -172,11 +176,30 @@
/* Align stack to 16 bytes. Another 32 bytes are pushed below. */
andl $0xfffffff0, %esp
+#ifdef __x86_64__
+ /* entry64.inc preserves ebx, esi, edi */
+ mov %ecx, %edi
+#include <cpu/x86/64bit/entry64.inc>
+ mov %edi, %ecx
+
+#endif
+
/* Call into the c-based SMM relocation function with the platform
* parameters. Equivalent to:
* struct arg = { c_handler_params, cpu_num, smm_runtime, canary };
* c_handler(&arg)
*/
+#ifdef __x86_64__
+ push %rbx /* uintptr_t *canary */
+ push $(smm_runtime)
+ push %rcx /* int cpu */
+ push c_handler_arg /* void *arg */
+
+ mov %rsp, %rdi /* *arg */
+
+ movl c_handler, %eax
+ call *%rax
+#else
push $0x0 /* Padding */
push $0x0 /* Padding */
push $0x0 /* Padding */
@@ -187,7 +210,7 @@
push %esp /* smm_module_params *arg (allocated on stack). */
mov c_handler, %eax
call *%eax
-
+#endif
/* Retrieve fxsave location. */
mov -4(%ebp), %edi
test %edi, %edi
diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h
index cf107b1..0de08b6 100644
--- a/src/include/cpu/x86/smm.h
+++ b/src/include/cpu/x86/smm.h
@@ -75,7 +75,7 @@
struct smm_module_params {
void *arg;
- int cpu;
+ size_t cpu;
const struct smm_runtime *runtime;
/* A canary value that has been placed at the end of the stack.
* If (uintptr_t)canary != *canary then a stack overflow has occurred.
--
To view, visit https://review.coreboot.org/c/coreboot/+/37392
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I26300492e4be62ddd5d80525022c758a019d63a1
Gerrit-Change-Number: 37392
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-MessageType: newchange
9
36
07 Apr '21
Thomas Heijligen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33582
Change subject: libpayload: nvme driver
......................................................................
libpayload: nvme driver
Change-Id: Ie75b1dc743dac3426c230c57ee23b771ba3a6e0c
Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com>
---
M payloads/libpayload/drivers/Makefile.inc
M payloads/libpayload/drivers/storage/Kconfig
A payloads/libpayload/drivers/storage/nvme.c
M payloads/libpayload/drivers/storage/storage.c
A payloads/libpayload/include/storage/nvme.h
M payloads/libpayload/include/storage/storage.h
M payloads/libpayload/include/x86/arch/io.h
A payloads/libpayload/sample/nvme_test.c
8 files changed, 429 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/33582/1
diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc
index 40e587c..676dbd3 100644
--- a/payloads/libpayload/drivers/Makefile.inc
+++ b/payloads/libpayload/drivers/Makefile.inc
@@ -77,6 +77,7 @@
libc-$(CONFIG_LP_STORAGE) += storage/storage.c
libc-$(CONFIG_LP_STORAGE_AHCI) += storage/ahci.c
libc-$(CONFIG_LP_STORAGE_AHCI) += storage/ahci_common.c
+libc-$(CONFIG_LP_STORAGE_NVME) += storage/nvme.c
ifeq ($(CONFIG_LP_STORAGE_ATA),y)
libc-$(CONFIG_LP_STORAGE_ATA) += storage/ata.c
libc-$(CONFIG_LP_STORAGE_ATA) += storage/ahci_ata.c
diff --git a/payloads/libpayload/drivers/storage/Kconfig b/payloads/libpayload/drivers/storage/Kconfig
index 04e9a29..3eabf6a 100644
--- a/payloads/libpayload/drivers/storage/Kconfig
+++ b/payloads/libpayload/drivers/storage/Kconfig
@@ -57,3 +57,10 @@
help
If this option is selected only AHCI controllers which are known
to work will be used.
+
+config STORAGE_NVME
+ bool "Support for NVMe devices"
+ depends on STORAGE && PCI
+ default y
+ help
+ Select this option if you want support for NVMe devices
diff --git a/payloads/libpayload/drivers/storage/nvme.c b/payloads/libpayload/drivers/storage/nvme.c
new file mode 100644
index 0000000..871759d
--- /dev/null
+++ b/payloads/libpayload/drivers/storage/nvme.c
@@ -0,0 +1,331 @@
+#include <libpayload.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <pci.h>
+#include <pci/pci.h>
+#include <storage/nvme.h>
+#include <storage/storage.h>
+
+#define PCI_CLASS_CODE_NVME 0x0108
+
+// NVME Controller Configuration
+#define NVME_CC_EN (1 << 0)
+#define NVME_CC_CSS (0 << 4)
+#define NVME_CC_MPS (0 << 7)
+#define NVME_CC_AMS (0 << 11)
+#define NVME_CC_SHN (0 << 14)
+#define NVME_CC_IOSQES (6 << 16)
+#define NVME_CC_IOCQES (4 << 20)
+
+#define NVME_QUEUE_SIZE 2
+#define NVME_SQ_ENTRY_SIZE 64
+#define NVME_CQ_ENTRY_SIZE 16
+
+struct nvme_s_queue_entry {
+ uint32_t dw[16];
+};
+
+struct nvme_c_queue_entry {
+ uint32_t dw[4];
+};
+
+enum nvme_queue {
+ NVME_ADMIN_QUEUE = 0,
+ NVME_IO_QUEUE = 2,
+ ads = 0,
+ adc = 1,
+ ios = 2,
+ ioc = 3,
+};
+
+static storage_poll_t nvme_poll(struct storage_dev *dev);
+static void nvme_detach_device(struct storage_dev *dev);
+static ssize_t nvme_read_blocks512(struct storage_dev *dev, lba_t start, size_t count, unsigned char *buf);
+
+static int create_admin_queues(struct nvme_dev *nvme);
+static int create_io_submission_queue(struct nvme_dev *nvme);
+static int create_io_completion_queue(struct nvme_dev *nvme);
+static void delete_admin_queues(struct nvme_dev *nvme);
+static void delete_io_submission_queue(struct nvme_dev *nvme);
+static void delete_io_completion_queue(struct nvme_dev *nvme);
+static int nvme_cmd(struct nvme_dev *nvme, enum nvme_queue q, const struct nvme_s_queue_entry *cmd);
+static int read(struct nvme_dev *nvme, void *buffer, uint64_t base, uint16_t count);
+
+
+static storage_poll_t nvme_poll(struct storage_dev *dev)
+{
+ return POLL_MEDIUM_PRESENT;
+}
+
+static void nvme_detach_device(struct storage_dev *dev)
+{
+ //nvme_free(dev->driver_struct);
+ // FIXME remove from list
+}
+
+static ssize_t nvme_read_blocks512(struct storage_dev *dev, lba_t start, size_t count, unsigned char *buf)
+{
+ void *buffer = memalign(0x1000, count * 512);
+ if (!buffer)
+ return 0;
+
+ for (int i = 0; i < count; i++) {
+ if (read((struct nvme_dev*)dev, buffer+(i*512), start + i, 1)) {
+ free(buffer);
+ return 0;
+ }
+ }
+
+ memcpy(buf, buffer, count * 512);
+ free(buffer);
+ return count;
+}
+
+static int read(struct nvme_dev *nvme, void *buffer, uint64_t base, uint16_t count)
+{
+ if (count == 0)
+ return -1;
+
+ struct nvme_s_queue_entry e = {
+ .dw[0] = 0x02,
+ .dw[1] = 0x1,
+ .dw[6] = virt_to_phys(buffer),
+ .dw[10] = base,
+ .dw[11] = base >> 32,
+ .dw[12] = count - 1,
+ };
+ return nvme_cmd(nvme, ios, &e);
+}
+
+static void delete_io_submission_queue(struct nvme_dev *nvme)
+{
+ // TODO
+}
+
+static int create_io_submission_queue(struct nvme_dev *nvme)
+{
+ void *sq_buffer = memalign(0x1000, NVME_SQ_ENTRY_SIZE * NVME_QUEUE_SIZE);
+ if (!sq_buffer) {
+ printf("NVMe ERROR: Faild to allocate memory for io submission queue.\n");
+ return -1;
+ }
+ memset(sq_buffer, 0, NVME_SQ_ENTRY_SIZE * NVME_QUEUE_SIZE);
+
+ struct nvme_s_queue_entry e = {
+ .dw[0] = 0x01,
+ .dw[6] = virt_to_phys(sq_buffer),
+ .dw[10] = (NVME_QUEUE_SIZE << 16) | ios >> 1,
+ .dw[11] = (1 << 16) | 1,
+ };
+
+ int res = nvme_cmd(nvme, NVME_ADMIN_QUEUE, &e);
+ if (res) {
+ printf("NVMe ERROR: nvme_cmd returned with %i.\n", res);
+ free(sq_buffer);
+ return res;
+ }
+
+ uint8_t cap_dstrd = (read64(nvme->config) >> 32) & 0xf;
+ nvme->queue[ios].base = sq_buffer;
+ nvme->queue[ios].bell = nvme->config + 0x1000 + (ios * (4 << cap_dstrd));
+ nvme->queue[ios].idx = 0;
+ return 0;
+}
+
+static void delete_io_completion_queue(struct nvme_dev *nvme)
+{
+ // TODO
+}
+
+static int create_io_completion_queue(struct nvme_dev *nvme)
+{
+ void *const cq_buffer = memalign(0x1000, NVME_CQ_ENTRY_SIZE * NVME_QUEUE_SIZE);
+ if (!cq_buffer) {
+ printf("NVMe ERROR: Faild to allocate memory for io competion queue.\n");
+ return -1;
+ }
+ memset(cq_buffer, 0, NVME_CQ_ENTRY_SIZE * NVME_QUEUE_SIZE);
+
+ const struct nvme_s_queue_entry e = {
+ .dw[0] = 0x05,
+ .dw[6] = virt_to_phys(cq_buffer),
+ .dw[10] = (NVME_QUEUE_SIZE << 16) | ioc >> 1,
+ .dw[11] = 1,
+ };
+
+ int res = nvme_cmd(nvme, NVME_ADMIN_QUEUE, &e);
+ if (res) {
+ printf("NVMe ERROR: nvme_cmd returned with %i.\n", res);
+ free(cq_buffer);
+ return res;
+ }
+
+ uint8_t cap_dstrd = (read64(nvme->config) >> 32) & 0xf;
+ nvme->queue[ioc].base = cq_buffer;
+ nvme->queue[ioc].bell = nvme->config + 0x1000 + (ioc * (4 << cap_dstrd));
+ nvme->queue[ioc].idx = 0;
+ nvme->queue[ioc].round = 0;
+
+ return 0;
+}
+
+static int nvme_cmd(struct nvme_dev *nvme, enum nvme_queue q, const struct nvme_s_queue_entry *cmd)
+{
+ int sq = q, cq = q+1;
+
+ void *s_entry = nvme->queue[sq].base + (nvme->queue[sq].idx * NVME_SQ_ENTRY_SIZE);
+ memcpy(s_entry, cmd, NVME_SQ_ENTRY_SIZE);
+ write32(nvme->queue[sq].bell, nvme->queue[sq].idx + 1);
+ nvme->queue[sq].idx = (nvme->queue[sq].idx + 1) & 1;
+
+ struct nvme_c_queue_entry *c_entry = nvme->queue[cq].base + (nvme->queue[cq].idx * NVME_CQ_ENTRY_SIZE);
+ while (((c_entry->dw[3] >> 16 ) & 0x1) == nvme->queue[cq].round)
+ ; // FIXME timeout
+ write32(nvme->queue[cq].bell, nvme->queue[cq].idx + 1);
+ nvme->queue[cq].idx = (nvme->queue[cq].idx + 1) & 1;
+ if (nvme->queue[cq].idx == 0)
+ nvme->queue[cq].round = (nvme->queue[cq].round + 1) & 1;
+ return c_entry->dw[3] >> 17;
+}
+
+static void delete_admin_queues(struct nvme_dev *nvme)
+{
+ free(nvme->queue[ads].base);
+ free(nvme->queue[adc].base);
+ // TODO clean nvme admin queue struct ???
+}
+
+static int create_admin_queues(struct nvme_dev *nvme)
+{
+ uint8_t cap_dstrd = (read64(nvme->config) >> 32) & 0xf;
+ write32(nvme->config + 0x24, NVME_QUEUE_SIZE << 16 | NVME_QUEUE_SIZE);
+
+ void *sq_buffer = memalign(0x1000, NVME_SQ_ENTRY_SIZE * NVME_QUEUE_SIZE);
+ if (!sq_buffer) {
+ printf("NVMe ERROR: faild to allocated memory for admin submission queue\n");
+ return -1;
+ }
+ memset(sq_buffer, 0, NVME_SQ_ENTRY_SIZE * NVME_QUEUE_SIZE);
+ write64(nvme->config + 0x28, virt_to_phys(sq_buffer));
+
+ nvme->queue[ads].base = sq_buffer;
+ nvme->queue[ads].bell = nvme->config + 0x1000 + (ads * (4 << cap_dstrd));
+ nvme->queue[ads].idx = 0;
+
+ void *cq_buffer = memalign(0x1000, NVME_CQ_ENTRY_SIZE * NVME_QUEUE_SIZE);
+ if (!cq_buffer) {
+ printf("NVMe ERROR: Faild to allocate memory for admin completion queue\n");
+ free(cq_buffer);
+ return -1;
+ }
+ memset(cq_buffer, 0, NVME_CQ_ENTRY_SIZE * NVME_QUEUE_SIZE);
+ write64(nvme->config + 0x30, virt_to_phys(cq_buffer));
+
+ nvme->queue[adc].base = cq_buffer;
+ nvme->queue[adc].bell = nvme->config + 0x1000 + (adc * (4 << cap_dstrd));
+ nvme->queue[adc].idx = 0;
+ nvme->queue[adc].round = 0;
+
+ return 0;
+}
+
+static void nvme_init(pcidev_t dev)
+{
+ printf("NVMe init (Device %02x:%02x.%02x)\n", PCI_BUS(dev), PCI_SLOT(dev), PCI_FUNC(dev));
+
+ void *pci_bar0 = phys_to_virt(pci_read_config32(dev, 0x10) & ~0x3ff);
+
+ if ( !(((read64(pci_bar0) >> 37 ) & 0xff) == 0x01)) {
+ printf("NVMe ERROR: PCIe device does not support the NVMe command set\n");
+ return;
+ }
+
+ struct nvme_dev *nvme = malloc(sizeof(*nvme));
+ if (!nvme) {
+ printf("NVMe ERROR: Faild to allocate buffer for nvme driver struct\n");
+ return;
+ }
+ nvme->storage_dev.port_type = PORT_TYPE_NVME;
+ nvme->storage_dev.poll = nvme_poll;
+ nvme->storage_dev.read_blocks512 = nvme_read_blocks512;
+ nvme->storage_dev.write_blocks512 = NULL; // not implemented
+ nvme->storage_dev.detach_device = nvme_detach_device;
+ nvme->config = pci_bar0;
+
+ uint32_t cc = 0;
+ write32(nvme->config + 0x1c, 0);
+
+ int status, timeout = (read64(nvme->config) >> 24 & 0xff) * 500;
+ do {
+ status = read32(nvme->config + 0x1c) & 0x3;
+ if (status == 0x2) {
+ printf("NVMe ERROR: Faild to disable controller. FATAL ERROR\n");
+ goto abort;
+ }
+ if (timeout < 0) {
+ printf("NVMe ERROR: Faild to disable controller. Timeout.\n");
+ goto abort;
+ }
+ timeout -= 10;
+ mdelay(10);
+ } while (status != 0x0);
+
+ if (create_admin_queues(nvme))
+ goto abort;
+
+ cc = NVME_CC_EN | NVME_CC_CSS | NVME_CC_MPS | NVME_CC_AMS |NVME_CC_SHN
+ | NVME_CC_IOSQES | NVME_CC_IOCQES;
+ write32(nvme->config + 0x14, cc);
+
+ timeout = (read64(nvme->config) >> 24 & 0xff) * 500;
+ do {
+ status = read32(nvme->config + 0x1c) & 0x3;
+ if (status == 0x2) {
+ printf("NVMe ERROR: Faild to disable controller. FATAL ERROR\n");
+ goto abort;
+ }
+ if (timeout < 0) {
+ printf("NVMe ERROR: Faild to disable controller. Timeout.\n");
+ goto abort;
+ }
+ timeout -= 10;
+ mdelay(10);
+ } while (status != 0x1);
+
+ uint16_t command = pci_read_config16(dev, PCI_COMMAND);
+ pci_write_config16(dev, PCI_COMMAND, command | PCI_COMMAND_MASTER);
+
+ if (create_io_completion_queue(nvme))
+ goto abort;
+ if (create_io_submission_queue(nvme))
+ goto abort;
+
+ storage_attach_device((storage_dev_t*)nvme);
+ printf("NVMe init done.\n");
+ return;
+
+abort:
+ delete_io_submission_queue(nvme);
+ delete_io_completion_queue(nvme);
+ delete_admin_queues(nvme);
+ free(nvme);
+ printf("failed\n");
+ return;
+}
+
+void nvme_initialize(void)
+{
+ int bus, dev, func;
+ uint16_t class;
+
+ for (bus = 0; bus < 256; ++bus) {
+ for (dev = 0; dev < 32; ++dev) {
+ for (func = 0; func < 8; ++func) {
+ class = pci_read_config16(PCI_DEV(bus, dev, func), 0xa);
+ if (class == PCI_CLASS_CODE_NVME)
+ nvme_init(PCI_DEV(bus, dev, func));
+ }
+ }
+ }
+}
diff --git a/payloads/libpayload/drivers/storage/storage.c b/payloads/libpayload/drivers/storage/storage.c
index a7141ee..55cb60d 100644
--- a/payloads/libpayload/drivers/storage/storage.c
+++ b/payloads/libpayload/drivers/storage/storage.c
@@ -31,6 +31,9 @@
#if CONFIG(LP_STORAGE_AHCI)
# include <storage/ahci.h>
#endif
+#if CONFIG(LP_STORAGE_NVME)
+#include <storage/nvme.h>
+#endif
#include <storage/storage.h>
@@ -113,4 +116,7 @@
#if CONFIG(LP_STORAGE_AHCI)
ahci_initialize();
#endif
+#if CONFIG(LP_STORAGE_NVME)
+ nvme_initialize();
+#endif
}
diff --git a/payloads/libpayload/include/storage/nvme.h b/payloads/libpayload/include/storage/nvme.h
new file mode 100644
index 0000000..090c6d0
--- /dev/null
+++ b/payloads/libpayload/include/storage/nvme.h
@@ -0,0 +1,22 @@
+#ifndef _STORAGE_NVME_H
+#define _STORAGE_NVME_H
+
+#include <stdint.h>
+#include "storage.h"
+
+struct nvme_dev {
+ storage_dev_t storage_dev;
+
+ void *config;
+ void *admin_s_queue;
+ struct {
+ void *base;
+ uint32_t *bell;
+ uint16_t idx; // bool pos 0 or 1
+ uint16_t round; // bool round 0 or 1+0xd
+ } queue[4];
+};
+
+void nvme_initialize(void);
+
+#endif /* _STORAGE_NVME_H */
diff --git a/payloads/libpayload/include/storage/storage.h b/payloads/libpayload/include/storage/storage.h
index 2dc70b0..d1f998e 100644
--- a/payloads/libpayload/include/storage/storage.h
+++ b/payloads/libpayload/include/storage/storage.h
@@ -45,6 +45,7 @@
PORT_TYPE_IDE = (1 << 0),
PORT_TYPE_SATA = (1 << 1),
PORT_TYPE_USB = (1 << 2),
+ PORT_TYPE_NVME = (1 << 3),
} storage_port_t;
typedef enum {
diff --git a/payloads/libpayload/include/x86/arch/io.h b/payloads/libpayload/include/x86/arch/io.h
index c417ce0..46836d9 100644
--- a/payloads/libpayload/include/x86/arch/io.h
+++ b/payloads/libpayload/include/x86/arch/io.h
@@ -64,6 +64,11 @@
return *((volatile uint32_t *)(addr));
}
+static inline __attribute__((always_inline)) uint64_t read64(const volatile void *addr)
+{
+ return *((volatile uint64_t *)(addr));
+}
+
static inline __attribute__((always_inline)) void write8(volatile void *addr, uint8_t value)
{
*((volatile uint8_t *)(addr)) = value;
@@ -79,6 +84,11 @@
*((volatile uint32_t *)(addr)) = value;
}
+static inline __attribute__((always_inline)) void write64(volatile void *addr, uint64_t value)
+{
+ *((volatile uint64_t *)(addr)) = value;
+}
+
static inline unsigned int inl(int port)
{
unsigned long val;
diff --git a/payloads/libpayload/sample/nvme_test.c b/payloads/libpayload/sample/nvme_test.c
new file mode 100644
index 0000000..d2bdf10
--- /dev/null
+++ b/payloads/libpayload/sample/nvme_test.c
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/* Example file for libpayload. */
+
+#include <libpayload-config.h>
+#include <libpayload.h>
+#include <storage/storage.h>
+
+#define STORAGE_ID 0
+
+int main(void)
+{
+ printf("---------- TEST PROGRAM BEGIN ----------\n");
+ storage_initialize();
+
+ void *buffer = memalign(0x1000, 0x2000);
+ storage_read_blocks512(STORAGE_ID, 0, 15, buffer);
+ printf("\nbuffer content:\n");
+ //hexdump(buffer,0x2000);
+
+ printf("----------- TEST PROGRAM END -----------\n");
+ halt();
+ return 0;
+}
--
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Gerrit-Change-Id: Ie75b1dc743dac3426c230c57ee23b771ba3a6e0c
Gerrit-Change-Number: 33582
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7
28
Change in coreboot[master]: nb/intel/i440bx: Enable bootblock console
by Keith Hui (Code Review) 06 Apr '21
by Keith Hui (Code Review) 06 Apr '21
06 Apr '21
Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41461 )
Change subject: nb/intel/i440bx: Enable bootblock console
......................................................................
nb/intel/i440bx: Enable bootblock console
Change-Id: Ie59593d3e3e0c455ffd3813980d1c2fe801c3c18
Signed-off-by: Keith Hui <buurin(a)gmail.com>
---
M src/northbridge/intel/i440bx/Kconfig
1 file changed, 0 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/41461/1
diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig
index 8a6783e..d51cc0c 100644
--- a/src/northbridge/intel/i440bx/Kconfig
+++ b/src/northbridge/intel/i440bx/Kconfig
@@ -4,7 +4,6 @@
bool
select NO_MMCONF_SUPPORT
select HAVE_DEBUG_RAM_SETUP
- select NO_BOOTBLOCK_CONSOLE
config SDRAMPWR_4DIMM
bool
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ie59593d3e3e0c455ffd3813980d1c2fe801c3c18
Gerrit-Change-Number: 41461
Gerrit-PatchSet: 1
Gerrit-Owner: Keith Hui <buurin(a)gmail.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newchange
4
4
Change in coreboot[master]: mb/asus/p2b: Add option table support
by Keith Hui (Code Review) 06 Apr '21
by Keith Hui (Code Review) 06 Apr '21
06 Apr '21
Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41560 )
Change subject: mb/asus/p2b: Add option table support
......................................................................
mb/asus/p2b: Add option table support
Just do it already.
The two SCSI-specific options for p2b-{ls,ds} will be wired up in a
followup. They will be ignored by other boards without the hardware.
Change-Id: Ia43d502219d7c23d21f49d651113e3d653c6e9f4
Signed-off-by: Keith Hui <buurin(a)gmail.com>
---
M src/mainboard/asus/p2b/Kconfig
A src/mainboard/asus/p2b/cmos.default
A src/mainboard/asus/p2b/cmos.layout
3 files changed, 83 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/41560/1
diff --git a/src/mainboard/asus/p2b/Kconfig b/src/mainboard/asus/p2b/Kconfig
index f21de71..762207c 100644
--- a/src/mainboard/asus/p2b/Kconfig
+++ b/src/mainboard/asus/p2b/Kconfig
@@ -17,6 +17,7 @@
select SUPERIO_WINBOND_W83977TF
select HAVE_PIRQ_TABLE
select BOARD_ROMSIZE_KB_256
+ select HAVE_OPTION_TABLE
select SDRAMPWR_4DIMM if BOARD_ASUS_P2B_LS || BOARD_ASUS_P3B_F
select HAVE_ACPI_TABLES if BOARD_ASUS_P2B || BOARD_ASUS_P2B_LS
select BASE_ASUS_P2B_D if BOARD_ASUS_P2B_D || BOARD_ASUS_P2B_DS
diff --git a/src/mainboard/asus/p2b/cmos.default b/src/mainboard/asus/p2b/cmos.default
new file mode 100644
index 0000000..447726f
--- /dev/null
+++ b/src/mainboard/asus/p2b/cmos.default
@@ -0,0 +1,8 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+boot_option=Fallback
+debug_level=Debug
+nmi=Enable
+udma_enable=Enable
+scsi_lvd_term=Enable
+scsi_se_term=Enable
diff --git a/src/mainboard/asus/p2b/cmos.layout b/src/mainboard/asus/p2b/cmos.layout
new file mode 100644
index 0000000..5fd379f
--- /dev/null
+++ b/src/mainboard/asus/p2b/cmos.layout
@@ -0,0 +1,74 @@
+entries
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 3 boot_option
+388 4 h 0 reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395 4 e 4 debug_level
+
+# -----------------------------------------------------------------
+# coreboot config options: southbridge
+
+# Non Maskable Interrupt(NMI) support, which is an interrupt that may
+# occur on a RAM or unrecoverable error.
+408 1 e 1 nmi
+
+#409 2 e 5 power_on_after_fail
+411 1 e 1 udma_enable
+
+# -----------------------------------------------------------------
+# p2b-[ld]s config options: onboard SCSI termination
+# Controls PIIX4 GPO22 (Ultra2-68) and GPO23 (SCSI-50)
+412 1 e 1 scsi_se_term
+413 1 e 2 scsi_lvd_term
+
+# -----------------------------------------------------------------
+# TODO: raminit config options
+#415 1 e 6 ram_timing
+#416 1 e 5 srp_timing
+#417 1 e 5 srcd_timing
+#418 1 e 5 cas_latency
+
+enumerations
+#ID value text
+
+# Generic on/off enum
+1 0 Disable
+1 1 Enable
+# Inverted on/off enum
+2 0 Enable
+2 1 Disable
+
+# boot_option
+3 0 Fallback
+3 1 Normal
+
+# debug_level
+4 0 Emergency
+4 1 Alert
+4 2 Critical
+4 3 Error
+4 4 Warning
+4 5 Notice
+4 6 Info
+4 7 Debug
+4 8 Spew
+
+#5 0 3
+#5 1 2
+
+#6 0 Auto
+#6 1 Manual
+
+checksums
+
+checksum 592 975 976
+
+
--
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Gerrit-Change-Id: Ia43d502219d7c23d21f49d651113e3d653c6e9f4
Gerrit-Change-Number: 41560
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5
7
Change in coreboot[master]: sb/intel/i82371eb: Claim less I/O ports in ACPI
by Keith Hui (Code Review) 06 Apr '21
by Keith Hui (Code Review) 06 Apr '21
06 Apr '21
Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41093 )
Change subject: sb/intel/i82371eb: Claim less I/O ports in ACPI
......................................................................
sb/intel/i82371eb: Claim less I/O ports in ACPI
To avoid resource conflicts, this change leaves unclaimed:
- PM and SMBus ports (claimed by MBRS device written in SSDT)
- Ports 0x2e-0x2f (After reviewing Asus P3B-F OEM firmware)
Change-Id: Id5adb37d047621d7c8faf81607ceea4cbcac3d34
Signed-off-by: Keith Hui <buurin(a)gmail.com>
---
M src/southbridge/intel/i82371eb/acpi/i82371eb.asl
1 file changed, 4 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/41093/1
diff --git a/src/southbridge/intel/i82371eb/acpi/i82371eb.asl b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl
index 8b60edb..45e7a5e 100644
--- a/src/southbridge/intel/i82371eb/acpi/i82371eb.asl
+++ b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl
@@ -31,15 +31,13 @@
{
Name (BUF1, ResourceTemplate ()
{
- /* PM register ports */
- IO (Decode16, 0x0000, 0x0000, 0x01, 0x40, _Y06)
- /* SMBus register ports */
- IO (Decode16, 0x0000, 0x0000, 0x01, 0x10, _Y07)
/* PIIX4E ports */
/* Aliased DMA ports */
IO (Decode16, 0x0010, 0x0010, 0x01, 0x10, )
/* Aliased PIC ports */
- IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E, )
+ /* Do not claim 0x2e-0x2f, per P3B-F vendor DSDT */
+ IO (Decode16, 0x0022, 0x0022, 0x01, 0x0C, )
+ IO (Decode16, 0x0030, 0x0030, 0x01, 0x10, )
/* Aliased timer ports */
IO (Decode16, 0x0050, 0x0050, 0x01, 0x04, )
IO (Decode16, 0x0062, 0x0062, 0x01, 0x02, )
@@ -49,18 +47,10 @@
IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E, )
IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10, )
IO (Decode16, 0x0294, 0x0294, 0x01, 0x04, )
+ /* W83977TF/EF Super I/O config ports */
IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x02, )
IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02, )
})
- CreateWordField (BUF1, _Y06._MIN, PMLO)
- CreateWordField (BUF1, _Y06._MAX, PMRL)
- CreateWordField (BUF1, _Y07._MIN, SBLO)
- CreateWordField (BUF1, _Y07._MAX, SBRL)
-
- And (\_SB.PCI0.PX43.PM00, 0xFFFE, PMLO)
- And (\_SB.PCI0.PX43.SB00, 0xFFFE, SBLO)
- Store (PMLO, PMRL)
- Store (SBLO, SBRL)
Return (BUF1)
}
}
--
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Gerrit-Change-Id: Id5adb37d047621d7c8faf81607ceea4cbcac3d34
Gerrit-Change-Number: 41093
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Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
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4
18
29 Mar '21
jitao shi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33106
Change subject: WIP: temp for dispaly conflick
......................................................................
WIP: temp for dispaly conflick
Temp
squlash patches
google/krane: Add Panel TV101WUM-NL6 support.
google/kukui: Elaborate panel support for Kukui family boards.
google/kukui: Enable config for coreboot display
mediatek/mt8183: add dsi driver for mt8183
google/kukui: Enable display on internal panel
mediatek/mt8183: Add display driver
Change-Id: I09d127ab491bca98f3a9c9b7d4ad4b09674c963d
---
D 3rdparty/blobs
M src/mainboard/google/kukui/Kconfig
M src/mainboard/google/kukui/Makefile.inc
A src/mainboard/google/kukui/display.c
A src/mainboard/google/kukui/display.h
M src/mainboard/google/kukui/mainboard.c
A src/mainboard/google/kukui/panel_krane.c
A src/mainboard/google/kukui/panel_kukui.c
M src/soc/mediatek/mt8183/Makefile.inc
A src/soc/mediatek/mt8183/ddp.c
A src/soc/mediatek/mt8183/dsi.c
M src/soc/mediatek/mt8183/include/soc/addressmap.h
A src/soc/mediatek/mt8183/include/soc/ddp.h
A src/soc/mediatek/mt8183/include/soc/dsi.h
14 files changed, 2,372 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/33106/1
diff --git a/3rdparty/blobs b/3rdparty/blobs
deleted file mode 160000
index ca6cfcd..0000000
--- a/3rdparty/blobs
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit ca6cfcdbe1cdeb38c2622ee2e5236cc4657e3377
diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig
index 6831d1e..5893722 100644
--- a/src/mainboard/google/kukui/Kconfig
+++ b/src/mainboard/google/kukui/Kconfig
@@ -37,6 +37,9 @@
select EC_GOOGLE_CHROMEEC_SPI
select MAINBOARD_HAS_SPI_TPM_CR50 if VBOOT
select MAINBOARD_HAS_TPM2 if VBOOT
+ select MAINBOARD_HAS_NATIVE_VGA_INIT
+ select MAINBOARD_FORCE_NATIVE_VGA_INIT
+ select HAVE_LINEAR_FRAMEBUFFER
config MAINBOARD_DIR
string
diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc
index a0556c1..8a023a5 100644
--- a/src/mainboard/google/kukui/Makefile.inc
+++ b/src/mainboard/google/kukui/Makefile.inc
@@ -22,6 +22,9 @@
ramstage-y += boardid.c
ramstage-y += chromeos.c
+ramstage-y += display.c
+ramstage-$(CONFIG_BOARD_GOOGLE_KUKUI) += panel_kukui.c
+ramstage-$(CONFIG_BOARD_GOOGLE_KRANE) += panel_krane.c
ramstage-y += mainboard.c
ramstage-y += memlayout.ld
ramstage-y += reset.c
diff --git a/src/mainboard/google/kukui/display.c b/src/mainboard/google/kukui/display.c
new file mode 100644
index 0000000..c7f7f91
--- /dev/null
+++ b/src/mainboard/google/kukui/display.c
@@ -0,0 +1,127 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Huaqin Telecom Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <edid.h>
+#include <gpio.h>
+#include <soc/auxadc.h>
+#include <soc/ddp.h>
+#include <soc/dsi.h>
+#include <soc/gpio.h>
+#include <boardid.h>
+
+#include "display.h"
+#include "gpio.h"
+
+static void _display_startup(struct edid *edid,
+ struct lcm_init_table *init_table,
+ u32 init_table_size)
+{
+ int ret = 0;
+ u32 mipi_dsi_flags;
+
+ if ((edid == NULL) || (init_table == NULL)) {
+ printk(BIOS_ERR, "%s: wrong parameters\n", __func__);
+ return;
+ }
+
+ mipi_dsi_flags = MIPI_DSI_MODE_VIDEO |
+ MIPI_DSI_MODE_VIDEO_SYNC_PULSE | MIPI_DSI_MODE_LPM;
+
+ edid_set_framebuffer_bits_per_pixel(edid, 32, 0);
+
+ mtk_ddp_init();
+ ret = mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4,
+ false, edid, init_table, init_table_size);
+
+ if (ret < 0) {
+ printk(BIOS_ERR, "dsi init fail\n");
+ return;
+ }
+
+ mtk_ddp_mode_set(edid);
+
+ set_vbe_mode_info_valid(edid, (uintptr_t)0);
+}
+
+static struct edid *get_edid(struct board_display_intf *intf)
+{
+ struct panel_info *info = intf->cur_panel_info;
+
+ if (info)
+ return info->edid;
+ return NULL;
+}
+
+static struct lcm_init_table *get_panel_init_table(struct board_display_intf
+ *intf, u32 *table_size)
+{
+ struct panel_info *info = intf->cur_panel_info;
+
+ if (info) {
+ *table_size = info->table_size;
+ return info->init_table;
+ }
+
+ *table_size = 0;
+ return NULL;
+}
+
+static const char *get_panel_name(struct board_display_intf *intf)
+{
+ struct panel_info *info = intf->cur_panel_info;
+
+ if (info)
+ return info->panel_name;
+ return NULL;
+}
+
+/* Exported Functions */
+
+struct board_display_intf *get_current_display_intf(void)
+{
+ return &panel_display_intf;
+}
+
+int update_panel_info(struct board_display_intf *intf)
+{
+ int i;
+ union panel_id id = intf->get_panel_id(intf);
+
+ if (intf->is_panel_id_valid(id)) {
+ for (i = 0; i < intf->all_panel_info_size; ++i) {
+ if (id.value == intf->all_panel_info[i].disp_id.value) {
+ intf->cur_panel_info = &intf->all_panel_info[i];
+ return 0;
+ }
+ }
+ }
+ return -1;
+}
+
+void display_startup(struct board_display_intf *intf)
+{
+ struct edid *edid;
+ u32 init_table_size;
+ struct lcm_init_table *init_table;
+
+ edid = get_edid(intf);
+ init_table = get_panel_init_table(intf, &init_table_size);
+ printk(BIOS_INFO, "%s: name:%s init_table_size:%d\n",
+ __func__, get_panel_name(intf), init_table_size);
+ _display_startup(edid, init_table, init_table_size);
+}
diff --git a/src/mainboard/google/kukui/display.h b/src/mainboard/google/kukui/display.h
new file mode 100644
index 0000000..d7b8bd9
--- /dev/null
+++ b/src/mainboard/google/kukui/display.h
@@ -0,0 +1,99 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Huaqin Telecom Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MAINBOARD_GOOGLE_DISPLAY_H__
+#define __MAINBOARD_GOOGLE_DISPLAY_H__
+
+#include <soc/dsi.h>
+#include <soc/gpio.h>
+
+#define MAKE_AS_A_STRING(arg) #arg
+
+enum kukui_panel_id {
+ PANEL_KUKUI_FIRST = 0,
+ PANEL_KUKUI_INNOLUX = 0,
+ PANEL_KUKUI_P097PFG_SSD2858,
+ PANEL_KUKUI_UNKNOWN,
+ PANEL_KUKUI_COUNT,
+ PANEL_KUKUI_UNINITIALIZED
+};
+
+enum krane_panel_id {
+ PANEL_KRANE_FIRST = 0,
+ PANEL_KRANE_BOE_TV101WUM_NL6,
+ PANEL_KRANE_UNKNOWN,
+ PANEL_KRANE_COUNT,
+ PANEL_KRANE_UNINITIALIZED
+};
+
+
+union panel_id {
+ enum kukui_panel_id kukui_panel;
+ enum krane_panel_id krane_panel;
+ int value;
+};
+
+struct panel_info {
+ union panel_id disp_id; /* the ID for panel */
+ const char *panel_name; /* display panel name */
+ int voltage; /* voltage of LCM_ID */
+ struct edid *edid; /* edid info of this panel */
+ struct lcm_init_table *init_table; /* init command table */
+ u32 table_size; /* init command table size */
+};
+
+#define PANEL(_panel_id, _voltage, _edid, _init_table) \
+ { \
+ .disp_id = {_panel_id},\
+ .panel_name = MAKE_AS_A_STRING(_panel_id),\
+ .voltage = _voltage,\
+ .edid = &_edid,\
+ .init_table = _init_table,\
+ .table_size = ARRAY_SIZE(_init_table)} \
+
+
+struct board_display_intf {
+ const char *board; /* board name */
+ struct panel_info *all_panel_info; /* all supported panel info */
+ u32 all_panel_info_size; /* num of supported panel */
+ /*
+ * Runtime member
+ */
+ struct panel_info *cur_panel_info; /* detected panel info */
+ /*
+ * board related functions
+ */
+
+ union panel_id (*get_panel_id)(struct board_display_intf *intf);
+ bool (*is_panel_id_valid)(union panel_id id);
+ int (*backlight)(struct board_display_intf *intf);
+ int (*power)(struct board_display_intf *intf);
+};
+
+/*
+ * Exported functions
+ */
+
+struct board_display_intf *get_current_display_intf(void);
+int update_panel_info(struct board_display_intf *intf);
+void display_startup(struct board_display_intf *intf);
+
+
+/*
+ * Panel Interface for boards
+ */
+extern struct board_display_intf panel_display_intf;
+
+#endif
diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c
index 7a31909..4e7c20b 100644
--- a/src/mainboard/google/kukui/mainboard.c
+++ b/src/mainboard/google/kukui/mainboard.c
@@ -13,8 +13,17 @@
* GNU General Public License for more details.
*/
+#include <boardid.h>
+#include <bootmode.h>
+#include <console/console.h>
+#include <delay.h>
#include <device/device.h>
#include <soc/bl31_plat_params.h>
+#include "display.h"
+#include <edid.h>
+#include <gpio.h>
+#include <soc/ddp.h>
+#include <soc/dsi.h>
#include <soc/gpio.h>
#include <soc/mmu_operations.h>
#include <soc/mtcmos.h>
@@ -70,6 +79,28 @@
static void mainboard_init(struct device *dev)
{
+ struct board_display_intf *cur_disp_intf = NULL;
+
+ if (display_init_required()) {
+ printk(BIOS_INFO, "Starting display init.\n");
+
+ cur_disp_intf = get_current_display_intf();
+ if (cur_disp_intf && !update_panel_info(cur_disp_intf)) {
+ mtcmos_display_power_on();
+ mtcmos_protect_display_bus();
+
+ cur_disp_intf->backlight(cur_disp_intf);
+ cur_disp_intf->power(cur_disp_intf);
+ display_startup(cur_disp_intf);
+ } else {
+ printk(BIOS_ERR,
+ "%s: Can't find correct display interface\n",
+ __func__);
+ }
+
+ } else
+ printk(BIOS_ERR, "Skipping display init.\n");
+
configure_emmc();
configure_usb();
configure_audio();
diff --git a/src/mainboard/google/kukui/panel_krane.c b/src/mainboard/google/kukui/panel_krane.c
new file mode 100644
index 0000000..b6fa9a5
--- /dev/null
+++ b/src/mainboard/google/kukui/panel_krane.c
@@ -0,0 +1,409 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Huaqin Telecom Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <edid.h>
+#include <gpio.h>
+#include <soc/auxadc.h>
+#include <soc/ddp.h>
+#include <soc/dsi.h>
+#include <soc/gpio.h>
+#include <boardid.h>
+
+#include "display.h"
+#include "gpio.h"
+
+static struct edid krane_boe_tv101wum_nl6_edid = {
+ .panel_bits_per_color = 8,
+ .panel_bits_per_pixel = 24,
+ .mode = {
+ .name = "1200x1920@60Hz",
+ .pixel_clock = 159425,
+ .lvds_dual_channel = 0,
+ .refresh = 60,
+ .ha = 1200, .hbl = 164, .hso = 100, .hspw = 24, .hborder = 0,
+ .va = 1920, .vbl = 28, .vso = 10, .vspw = 4, .vborder = 0,
+ .phsync = '-', .pvsync = '-',
+ .x_mm = 135, .y_mm = 216,
+ },
+};
+
+struct lcm_init_table boe_tv101wum_nl6_init_cmd[] = {
+ {INIT_DCS_CMD, 1, { 0x10 } },
+ {DELAY_CMD, 34, {} },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x05 } },
+ {INIT_DCS_CMD, 2, { 0xB1, 0xE5 } },
+ {INIT_DCS_CMD, 2, { 0xB3, 0x52 } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xB3, 0x88 } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x04 } },
+ {INIT_DCS_CMD, 2, { 0xB8, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xB6, 0x03 } },
+ {INIT_DCS_CMD, 2, { 0xBA, 0x8B } },
+ {INIT_DCS_CMD, 2, { 0xBF, 0x1A } },
+ {INIT_DCS_CMD, 2, { 0xC0, 0x0F } },
+ {INIT_DCS_CMD, 2, { 0xC2, 0x0C } },
+ {INIT_DCS_CMD, 2, { 0xC3, 0x02 } },
+ {INIT_DCS_CMD, 2, { 0xC4, 0x0C } },
+ {INIT_DCS_CMD, 2, { 0xC5, 0x02 } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x01 } },
+ {INIT_DCS_CMD, 2, { 0xE0, 0x26 } },
+ {INIT_DCS_CMD, 2, { 0xE1, 0x26 } },
+ {INIT_DCS_CMD, 2, { 0xDC, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xDD, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCC, 0x26 } },
+ {INIT_DCS_CMD, 2, { 0xCD, 0x26 } },
+ {INIT_DCS_CMD, 2, { 0xC8, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xC9, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xD2, 0x03 } },
+ {INIT_DCS_CMD, 2, { 0xD3, 0x03 } },
+ {INIT_DCS_CMD, 2, { 0xE6, 0x04 } },
+ {INIT_DCS_CMD, 2, { 0xE7, 0x04 } },
+ {INIT_DCS_CMD, 2, { 0xC4, 0x09 } },
+ {INIT_DCS_CMD, 2, { 0xC5, 0x09 } },
+ {INIT_DCS_CMD, 2, { 0xD8, 0x0A } },
+ {INIT_DCS_CMD, 2, { 0xD9, 0x0A } },
+ {INIT_DCS_CMD, 2, { 0xC2, 0x0B } },
+ {INIT_DCS_CMD, 2, { 0xC3, 0x0B } },
+ {INIT_DCS_CMD, 2, { 0xD6, 0x0C } },
+ {INIT_DCS_CMD, 2, { 0xD7, 0x0C } },
+ {INIT_DCS_CMD, 2, { 0xC0, 0x05 } },
+ {INIT_DCS_CMD, 2, { 0xC1, 0x05 } },
+ {INIT_DCS_CMD, 2, { 0xD4, 0x06 } },
+ {INIT_DCS_CMD, 2, { 0xD5, 0x06 } },
+ {INIT_DCS_CMD, 2, { 0xCA, 0x07 } },
+ {INIT_DCS_CMD, 2, { 0xCB, 0x07 } },
+ {INIT_DCS_CMD, 2, { 0xDE, 0x08 } },
+ {INIT_DCS_CMD, 2, { 0xDF, 0x08 } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x02 } },
+ {INIT_DCS_CMD, 2, { 0xC0, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xC1, 0x0D } },
+ {INIT_DCS_CMD, 2, { 0xC2, 0x17 } },
+ {INIT_DCS_CMD, 2, { 0xC3, 0x26 } },
+ {INIT_DCS_CMD, 2, { 0xC4, 0x31 } },
+ {INIT_DCS_CMD, 2, { 0xC5, 0x1C } },
+ {INIT_DCS_CMD, 2, { 0xC6, 0x2C } },
+ {INIT_DCS_CMD, 2, { 0xC7, 0x33 } },
+ {INIT_DCS_CMD, 2, { 0xC8, 0x31 } },
+ {INIT_DCS_CMD, 2, { 0xC9, 0x37 } },
+ {INIT_DCS_CMD, 2, { 0xCA, 0x37 } },
+ {INIT_DCS_CMD, 2, { 0xCB, 0x37 } },
+ {INIT_DCS_CMD, 2, { 0xCC, 0x39 } },
+ {INIT_DCS_CMD, 2, { 0xCD, 0x2E } },
+ {INIT_DCS_CMD, 2, { 0xCE, 0x2F } },
+ {INIT_DCS_CMD, 2, { 0xCF, 0x2F } },
+ {INIT_DCS_CMD, 2, { 0xD0, 0x07 } },
+ {INIT_DCS_CMD, 2, { 0xD2, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xD3, 0x0D } },
+ {INIT_DCS_CMD, 2, { 0xD4, 0x17 } },
+ {INIT_DCS_CMD, 2, { 0xD5, 0x26 } },
+ {INIT_DCS_CMD, 2, { 0xD6, 0x31 } },
+ {INIT_DCS_CMD, 2, { 0xD7, 0x3F } },
+ {INIT_DCS_CMD, 2, { 0xD8, 0x3F } },
+ {INIT_DCS_CMD, 2, { 0xD9, 0x3F } },
+ {INIT_DCS_CMD, 2, { 0xDA, 0x3F } },
+ {INIT_DCS_CMD, 2, { 0xDB, 0x37 } },
+ {INIT_DCS_CMD, 2, { 0xDC, 0x37 } },
+ {INIT_DCS_CMD, 2, { 0xDD, 0x37 } },
+ {INIT_DCS_CMD, 2, { 0xDE, 0x39 } },
+ {INIT_DCS_CMD, 2, { 0xDF, 0x2E } },
+ {INIT_DCS_CMD, 2, { 0xE0, 0x2F } },
+ {INIT_DCS_CMD, 2, { 0xE1, 0x2F } },
+ {INIT_DCS_CMD, 2, { 0xE2, 0x07 } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x03 } },
+ {INIT_DCS_CMD, 2, { 0xC8, 0x0B } },
+ {INIT_DCS_CMD, 2, { 0xC9, 0x07 } },
+ {INIT_DCS_CMD, 2, { 0xC3, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xE7, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xC5, 0x2A } },
+ {INIT_DCS_CMD, 2, { 0xDE, 0x2A } },
+ {INIT_DCS_CMD, 2, { 0xCA, 0x43 } },
+ {INIT_DCS_CMD, 2, { 0xC9, 0x07 } },
+ {INIT_DCS_CMD, 2, { 0xE4, 0xC0 } },
+ {INIT_DCS_CMD, 2, { 0xE5, 0x0D } },
+ {INIT_DCS_CMD, 2, { 0xCB, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x06 } },
+ {INIT_DCS_CMD, 2, { 0xB8, 0xA5 } },
+ {INIT_DCS_CMD, 2, { 0xC0, 0xA5 } },
+ {INIT_DCS_CMD, 2, { 0xC7, 0x0F } },
+ {INIT_DCS_CMD, 2, { 0xD5, 0x32 } },
+ {INIT_DCS_CMD, 2, { 0xB8, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xC0, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xBC, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x07 } },
+ {INIT_DCS_CMD, 2, { 0xB1, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xB2, 0x02 } },
+ {INIT_DCS_CMD, 2, { 0xB3, 0x0F } },
+ {INIT_DCS_CMD, 2, { 0xB4, 0x25 } },
+ {INIT_DCS_CMD, 2, { 0xB5, 0x39 } },
+ {INIT_DCS_CMD, 2, { 0xB6, 0x4E } },
+ {INIT_DCS_CMD, 2, { 0xB7, 0x72 } },
+ {INIT_DCS_CMD, 2, { 0xB8, 0x97 } },
+ {INIT_DCS_CMD, 2, { 0xB9, 0xDC } },
+ {INIT_DCS_CMD, 2, { 0xBA, 0x22 } },
+ {INIT_DCS_CMD, 2, { 0xBB, 0xA4 } },
+ {INIT_DCS_CMD, 2, { 0xBC, 0x2B } },
+ {INIT_DCS_CMD, 2, { 0xBD, 0x2F } },
+ {INIT_DCS_CMD, 2, { 0xBE, 0xA9 } },
+ {INIT_DCS_CMD, 2, { 0xBF, 0x25 } },
+ {INIT_DCS_CMD, 2, { 0xC0, 0x61 } },
+ {INIT_DCS_CMD, 2, { 0xC1, 0x97 } },
+ {INIT_DCS_CMD, 2, { 0xC2, 0xB2 } },
+ {INIT_DCS_CMD, 2, { 0xC3, 0xCD } },
+ {INIT_DCS_CMD, 2, { 0xC4, 0xD9 } },
+ {INIT_DCS_CMD, 2, { 0xC5, 0xE7 } },
+ {INIT_DCS_CMD, 2, { 0xC6, 0xF4 } },
+ {INIT_DCS_CMD, 2, { 0xC7, 0xFA } },
+ {INIT_DCS_CMD, 2, { 0xC8, 0xFC } },
+ {INIT_DCS_CMD, 2, { 0xC9, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCA, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCB, 0x16 } },
+ {INIT_DCS_CMD, 2, { 0xCC, 0xAF } },
+ {INIT_DCS_CMD, 2, { 0xCD, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xCE, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x08 } },
+ {INIT_DCS_CMD, 2, { 0xB1, 0x04 } },
+ {INIT_DCS_CMD, 2, { 0xB2, 0x05 } },
+ {INIT_DCS_CMD, 2, { 0xB3, 0x11 } },
+ {INIT_DCS_CMD, 2, { 0xB4, 0x24 } },
+ {INIT_DCS_CMD, 2, { 0xB5, 0x39 } },
+ {INIT_DCS_CMD, 2, { 0xB6, 0x4F } },
+ {INIT_DCS_CMD, 2, { 0xB7, 0x72 } },
+ {INIT_DCS_CMD, 2, { 0xB8, 0x98 } },
+ {INIT_DCS_CMD, 2, { 0xB9, 0xDC } },
+ {INIT_DCS_CMD, 2, { 0xBA, 0x23 } },
+ {INIT_DCS_CMD, 2, { 0xBB, 0xA6 } },
+ {INIT_DCS_CMD, 2, { 0xBC, 0x2C } },
+ {INIT_DCS_CMD, 2, { 0xBD, 0x30 } },
+ {INIT_DCS_CMD, 2, { 0xBE, 0xAA } },
+ {INIT_DCS_CMD, 2, { 0xBF, 0x26 } },
+ {INIT_DCS_CMD, 2, { 0xC0, 0x62 } },
+ {INIT_DCS_CMD, 2, { 0xC1, 0x9B } },
+ {INIT_DCS_CMD, 2, { 0xC2, 0xB5 } },
+ {INIT_DCS_CMD, 2, { 0xC3, 0xCF } },
+ {INIT_DCS_CMD, 2, { 0xC4, 0xDB } },
+ {INIT_DCS_CMD, 2, { 0xC5, 0xE8 } },
+ {INIT_DCS_CMD, 2, { 0xC6, 0xF5 } },
+ {INIT_DCS_CMD, 2, { 0xC7, 0xFA } },
+ {INIT_DCS_CMD, 2, { 0xC8, 0xFC } },
+ {INIT_DCS_CMD, 2, { 0xC9, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCA, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCB, 0x16 } },
+ {INIT_DCS_CMD, 2, { 0xCC, 0xAF } },
+ {INIT_DCS_CMD, 2, { 0xCD, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xCE, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x09 } },
+ {INIT_DCS_CMD, 2, { 0xB1, 0x04 } },
+ {INIT_DCS_CMD, 2, { 0xB2, 0x02 } },
+ {INIT_DCS_CMD, 2, { 0xB3, 0x16 } },
+ {INIT_DCS_CMD, 2, { 0xB4, 0x24 } },
+ {INIT_DCS_CMD, 2, { 0xB5, 0x3B } },
+ {INIT_DCS_CMD, 2, { 0xB6, 0x4F } },
+ {INIT_DCS_CMD, 2, { 0xB7, 0x73 } },
+ {INIT_DCS_CMD, 2, { 0xB8, 0x99 } },
+ {INIT_DCS_CMD, 2, { 0xB9, 0xE0 } },
+ {INIT_DCS_CMD, 2, { 0xBA, 0x26 } },
+ {INIT_DCS_CMD, 2, { 0xBB, 0xAD } },
+ {INIT_DCS_CMD, 2, { 0xBC, 0x36 } },
+ {INIT_DCS_CMD, 2, { 0xBD, 0x3A } },
+ {INIT_DCS_CMD, 2, { 0xBE, 0xAE } },
+ {INIT_DCS_CMD, 2, { 0xBF, 0x2A } },
+ {INIT_DCS_CMD, 2, { 0xC0, 0x66 } },
+ {INIT_DCS_CMD, 2, { 0xC1, 0x9E } },
+ {INIT_DCS_CMD, 2, { 0xC2, 0xB8 } },
+ {INIT_DCS_CMD, 2, { 0xC3, 0xD1 } },
+ {INIT_DCS_CMD, 2, { 0xC4, 0xDD } },
+ {INIT_DCS_CMD, 2, { 0xC5, 0xE9 } },
+ {INIT_DCS_CMD, 2, { 0xC6, 0xF6 } },
+ {INIT_DCS_CMD, 2, { 0xC7, 0xFA } },
+ {INIT_DCS_CMD, 2, { 0xC8, 0xFC } },
+ {INIT_DCS_CMD, 2, { 0xC9, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCA, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCB, 0x16 } },
+ {INIT_DCS_CMD, 2, { 0xCC, 0xAF } },
+ {INIT_DCS_CMD, 2, { 0xCD, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xCE, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x0A } },
+ {INIT_DCS_CMD, 2, { 0xB1, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xB2, 0x02 } },
+ {INIT_DCS_CMD, 2, { 0xB3, 0x0F } },
+ {INIT_DCS_CMD, 2, { 0xB4, 0x25 } },
+ {INIT_DCS_CMD, 2, { 0xB5, 0x39 } },
+ {INIT_DCS_CMD, 2, { 0xB6, 0x4E } },
+ {INIT_DCS_CMD, 2, { 0xB7, 0x72 } },
+ {INIT_DCS_CMD, 2, { 0xB8, 0x97 } },
+ {INIT_DCS_CMD, 2, { 0xB9, 0xDC } },
+ {INIT_DCS_CMD, 2, { 0xBA, 0x22 } },
+ {INIT_DCS_CMD, 2, { 0xBB, 0xA4 } },
+ {INIT_DCS_CMD, 2, { 0xBC, 0x2B } },
+ {INIT_DCS_CMD, 2, { 0xBD, 0x2F } },
+ {INIT_DCS_CMD, 2, { 0xBE, 0xA9 } },
+ {INIT_DCS_CMD, 2, { 0xBF, 0x25 } },
+ {INIT_DCS_CMD, 2, { 0xC0, 0x61 } },
+ {INIT_DCS_CMD, 2, { 0xC1, 0x97 } },
+ {INIT_DCS_CMD, 2, { 0xC2, 0xB2 } },
+ {INIT_DCS_CMD, 2, { 0xC3, 0xCD } },
+ {INIT_DCS_CMD, 2, { 0xC4, 0xD9 } },
+ {INIT_DCS_CMD, 2, { 0xC5, 0xE7 } },
+ {INIT_DCS_CMD, 2, { 0xC6, 0xF4 } },
+ {INIT_DCS_CMD, 2, { 0xC7, 0xFA } },
+ {INIT_DCS_CMD, 2, { 0xC8, 0xFC } },
+ {INIT_DCS_CMD, 2, { 0xC9, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCA, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCB, 0x16 } },
+ {INIT_DCS_CMD, 2, { 0xCC, 0xAF } },
+ {INIT_DCS_CMD, 2, { 0xCD, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xCE, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x0B } },
+ {INIT_DCS_CMD, 2, { 0xB1, 0x04 } },
+ {INIT_DCS_CMD, 2, { 0xB2, 0x05 } },
+ {INIT_DCS_CMD, 2, { 0xB3, 0x11 } },
+ {INIT_DCS_CMD, 2, { 0xB4, 0x24 } },
+ {INIT_DCS_CMD, 2, { 0xB5, 0x39 } },
+ {INIT_DCS_CMD, 2, { 0xB6, 0x4F } },
+ {INIT_DCS_CMD, 2, { 0xB7, 0x72 } },
+ {INIT_DCS_CMD, 2, { 0xB8, 0x98 } },
+ {INIT_DCS_CMD, 2, { 0xB9, 0xDC } },
+ {INIT_DCS_CMD, 2, { 0xBA, 0x23 } },
+ {INIT_DCS_CMD, 2, { 0xBB, 0xA6 } },
+ {INIT_DCS_CMD, 2, { 0xBC, 0x2C } },
+ {INIT_DCS_CMD, 2, { 0xBD, 0x30 } },
+ {INIT_DCS_CMD, 2, { 0xBE, 0xAA } },
+ {INIT_DCS_CMD, 2, { 0xBF, 0x26 } },
+ {INIT_DCS_CMD, 2, { 0xC0, 0x62 } },
+ {INIT_DCS_CMD, 2, { 0xC1, 0x9B } },
+ {INIT_DCS_CMD, 2, { 0xC2, 0xB5 } },
+ {INIT_DCS_CMD, 2, { 0xC3, 0xCF } },
+ {INIT_DCS_CMD, 2, { 0xC4, 0xDB } },
+ {INIT_DCS_CMD, 2, { 0xC5, 0xE8 } },
+ {INIT_DCS_CMD, 2, { 0xC6, 0xF5 } },
+ {INIT_DCS_CMD, 2, { 0xC7, 0xFA } },
+ {INIT_DCS_CMD, 2, { 0xC8, 0xFC } },
+ {INIT_DCS_CMD, 2, { 0xC9, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCA, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCB, 0x16 } },
+ {INIT_DCS_CMD, 2, { 0xCC, 0xAF } },
+ {INIT_DCS_CMD, 2, { 0xCD, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xCE, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x0C } },
+ {INIT_DCS_CMD, 2, { 0xB1, 0x04 } },
+ {INIT_DCS_CMD, 2, { 0xB2, 0x02 } },
+ {INIT_DCS_CMD, 2, { 0xB3, 0x16 } },
+ {INIT_DCS_CMD, 2, { 0xB4, 0x24 } },
+ {INIT_DCS_CMD, 2, { 0xB5, 0x3B } },
+ {INIT_DCS_CMD, 2, { 0xB6, 0x4F } },
+ {INIT_DCS_CMD, 2, { 0xB7, 0x73 } },
+ {INIT_DCS_CMD, 2, { 0xB8, 0x99 } },
+ {INIT_DCS_CMD, 2, { 0xB9, 0xE0 } },
+ {INIT_DCS_CMD, 2, { 0xBA, 0x26 } },
+ {INIT_DCS_CMD, 2, { 0xBB, 0xAD } },
+ {INIT_DCS_CMD, 2, { 0xBC, 0x36 } },
+ {INIT_DCS_CMD, 2, { 0xBD, 0x3A } },
+ {INIT_DCS_CMD, 2, { 0xBE, 0xAE } },
+ {INIT_DCS_CMD, 2, { 0xBF, 0x2A } },
+ {INIT_DCS_CMD, 2, { 0xC0, 0x66 } },
+ {INIT_DCS_CMD, 2, { 0xC1, 0x9E } },
+ {INIT_DCS_CMD, 2, { 0xC2, 0xB8 } },
+ {INIT_DCS_CMD, 2, { 0xC3, 0xD1 } },
+ {INIT_DCS_CMD, 2, { 0xC4, 0xDD } },
+ {INIT_DCS_CMD, 2, { 0xC5, 0xE9 } },
+ {INIT_DCS_CMD, 2, { 0xC6, 0xF6 } },
+ {INIT_DCS_CMD, 2, { 0xC7, 0xFA } },
+ {INIT_DCS_CMD, 2, { 0xC8, 0xFC } },
+ {INIT_DCS_CMD, 2, { 0xC9, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCA, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCB, 0x16 } },
+ {INIT_DCS_CMD, 2, { 0xCC, 0xAF } },
+ {INIT_DCS_CMD, 2, { 0xCD, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xCE, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xB3, 0x08 } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x04 } },
+ {INIT_DCS_CMD, 2, { 0xB8, 0x68 } },
+ {DELAY_CMD, 10, {} },
+ {INIT_DCS_CMD, 1, { 0x11 } },
+ {DELAY_CMD, 120, {} },
+ {INIT_DCS_CMD, 1, { 0x29 } },
+ {DELAY_CMD, 20, {} },
+
+};
+
+struct panel_info krane_panel_info[] = {
+ PANEL(PANEL_KRANE_BOE_TV101WUM_NL6,
+ 74000,
+ krane_boe_tv101wum_nl6_edid,
+ boe_tv101wum_nl6_init_cmd),
+ {{PANEL_KRANE_UNKNOWN}, "PANEL_KRANE_UNKNOWN",
+ 0, NULL, NULL, 0},
+};
+
+static union panel_id krane_get_panel_id(struct board_display_intf *intf)
+{
+ return (union panel_id)PANEL_KRANE_BOE_TV101WUM_NL6;
+};
+
+static bool krane_is_panel_id_valid(union panel_id id)
+{
+ if (id.value < PANEL_KRANE_UNKNOWN)
+ return true;
+ return false;
+};
+
+static int krane_backlight(struct board_display_intf *intf)
+{
+ gpio_output(GPIO(PERIPHERAL_EN13), 1);
+ gpio_output(GPIO(DISP_PWM), 1); /* DISP_PWM0 */
+
+ return 0;
+};
+
+static int krane_power(struct board_display_intf *intf)
+{
+ if (board_id() < 2) {
+ /* board from p1 */
+ gpio_output(GPIO(LCM_RST), 0);
+ udelay(100);
+ gpio_output(GPIO(LCM_RST), 1);
+ mdelay(20);
+ } else {
+ /* board from p2 */
+ gpio_output(GPIO(LCM_RST), 0);
+ udelay(1500);
+ gpio_output(GPIO(SIM2_SRST), 1);
+ mdelay(5);
+ gpio_output(GPIO(PERIPHERAL_EN9), 1);
+ gpio_output(GPIO(MISC_BSI_CK_3), 1);
+ mdelay(100);
+ gpio_output(GPIO(LCM_RST), 1);
+ mdelay(10);
+ }
+
+ return 0;
+
+};
+
+struct board_display_intf panel_display_intf = {
+ .board = "krane",
+ .all_panel_info = krane_panel_info,
+ .all_panel_info_size = ARRAY_SIZE(krane_panel_info),
+ .cur_panel_info = NULL,
+ .get_panel_id = &krane_get_panel_id,
+ .is_panel_id_valid = &krane_is_panel_id_valid,
+ .backlight = &krane_backlight,
+ .power = &krane_power,
+};
diff --git a/src/mainboard/google/kukui/panel_kukui.c b/src/mainboard/google/kukui/panel_kukui.c
new file mode 100644
index 0000000..be76aa4
--- /dev/null
+++ b/src/mainboard/google/kukui/panel_kukui.c
@@ -0,0 +1,194 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Huaqin Telecom Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <edid.h>
+#include <gpio.h>
+#include <soc/auxadc.h>
+#include <soc/ddp.h>
+#include <soc/dsi.h>
+#include <soc/gpio.h>
+#include <boardid.h>
+
+#include "display.h"
+#include "gpio.h"
+
+static struct edid kukui_innolux_edid = {
+ .panel_bits_per_color = 8,
+ .panel_bits_per_pixel = 24,
+ .mode = {
+ .name = "768x1024@60Hz",
+ .pixel_clock = 56900,
+ .lvds_dual_channel = 0,
+ .refresh = 60,
+ .ha = 768, .hbl = 120, .hso = 40, .hspw = 40, .hborder = 0,
+ .va = 1024, .vbl = 44, .vso = 20, .vspw = 4, .vborder = 0,
+ .phsync = '-', .pvsync = '-',
+ .x_mm = 120, .y_mm = 160,
+ },
+};
+
+static struct lcm_init_table lcm_init_cmd[] = {
+ {INIT_DCS_CMD, 1, {MIPI_DCS_EXIT_SLEEP_MODE} },
+ {DELAY_CMD, 120, {} },
+ {INIT_DCS_CMD, 1, {MIPI_DCS_SET_DISPLAY_ON} },
+ {DELAY_CMD, 120, {} },
+};
+
+static struct edid kukui_p097pfg_ssd2858_edid = {
+ .panel_bits_per_color = 8,
+ .panel_bits_per_pixel = 24,
+ .mode = {
+ .name = "1536x2048@60Hz",
+ .pixel_clock = 211660,
+ .lvds_dual_channel = 0,
+ .refresh = 60,
+ .ha = 1536, .hbl = 160, .hso = 140, .hspw = 10, .hborder = 0,
+ .va = 2048, .vbl = 32, .vso = 20, .vspw = 2, .vborder = 0,
+ .phsync = '-', .pvsync = '-',
+ .x_mm = 147, .y_mm = 196,
+ },
+};
+
+struct lcm_init_table lcm_p097pfg_ssd2858_init_cmd[] = {
+ /* SSD2858 config */
+ {INIT_GENENIC_CMD, 2, {0xff, 0x00} },
+ /* LOCKCNT=0x1f4, MRX=0, POSTDIV=1 (/2} }, MULT=0x49
+ * 27 Mhz => 985.5 Mhz
+ */
+ {INIT_GENENIC_CMD, 6, {0x00, 0x08, 0x01, 0xf4, 0x01, 0x49} },
+ /* MTXDIV=1, SYSDIV=3 (=> 4) */
+ {INIT_GENENIC_CMD, 6, {0x00, 0x0c, 0x00, 0x00, 0x00, 0x03} },
+ /* MTXVPF=24bpp, MRXLS=4 lanes, MRXVB=bypass, MRXECC=1, MRXEOT=1
+ * MRXEE=1
+ */
+ {INIT_GENENIC_CMD, 6, {0x00, 0x14, 0x0c, 0x3d, 0x80, 0x0f} },
+ {INIT_GENENIC_CMD, 6, {0x00, 0x20, 0x15, 0x92, 0x56, 0x7d} },
+ {INIT_GENENIC_CMD, 6, {0x00, 0x24, 0x00, 0x00, 0x30, 0x00} },
+
+ {INIT_GENENIC_CMD, 6, {0x10, 0x08, 0x01, 0x20, 0x08, 0x45} },
+ {INIT_GENENIC_CMD, 6, {0x10, 0x1c, 0x00, 0x00, 0x00, 0x00} },
+ {INIT_GENENIC_CMD, 6, {0x20, 0x0c, 0x00, 0x00, 0x00, 0x04} },
+ /* Pixel clock 985.5 Mhz * 0x49/0x4b = 959 Mhz */
+ {INIT_GENENIC_CMD, 6, {0x20, 0x10, 0x00, 0x4b, 0x00, 0x49} },
+ {INIT_GENENIC_CMD, 6, {0x20, 0xa0, 0x00, 0x00, 0x00, 0x00} },
+ /* EOT=1, LPE = 0, LSOUT=4 lanes, LPD=25 */
+ {INIT_GENENIC_CMD, 6, {0x60, 0x08, 0x00, 0xd9, 0x00, 0x08} },
+ {INIT_GENENIC_CMD, 6, {0x60, 0x14, 0x01, 0x00, 0x01, 0x06} },
+ /* DSI0 enable (default: probably not needed) */
+ {INIT_GENENIC_CMD, 6, {0x60, 0x80, 0x00, 0x00, 0x00, 0x0f} },
+ /* DSI1 enable */
+ {INIT_GENENIC_CMD, 6, {0x60, 0xa0, 0x00, 0x00, 0x00, 0x0f} },
+
+ /* HSA=0x18, VSA=0x02, HBP=0x50, VBP=0x0c */
+ {INIT_GENENIC_CMD, 6, {0x60, 0x0c, 0x0c, 0x50, 0x02, 0x18} },
+ /* VACT= 0x800 (2048} }, VFP= 0x14, HFP=0x50 */
+ {INIT_GENENIC_CMD, 6, {0x60, 0x10, 0x08, 0x00, 0x14, 0x50} },
+ /* HACT=0x300 (768) */
+ {INIT_GENENIC_CMD, 6, {0x60, 0x84, 0x00, 0x00, 0x03, 0x00} },
+ {INIT_GENENIC_CMD, 6, {0x60, 0xa4, 0x00, 0x00, 0x03, 0x00} },
+
+ /* Take panel out of sleep. */
+ {INIT_GENENIC_CMD, 2, {0xff, 0x01} },
+ {INIT_DCS_CMD, 1, {0x11} },
+ {DELAY_CMD, 120, {} },
+ {INIT_DCS_CMD, 1, {0x29} },
+ {DELAY_CMD, 20, {} },
+ {INIT_GENENIC_CMD, 2, {0xff, 0x00} },
+
+ {DELAY_CMD, 120, {} },
+ {INIT_DCS_CMD, 1, {0x11} },
+ {DELAY_CMD, 120, {} },
+ {INIT_DCS_CMD, 1, {0x29} },
+ {DELAY_CMD, 20, {} },
+};
+
+struct panel_info kukui_panel_info[] = {
+ PANEL(PANEL_KUKUI_INNOLUX,
+ 74000,
+ kukui_innolux_edid,
+ lcm_init_cmd),
+ PANEL(PANEL_KUKUI_P097PFG_SSD2858,
+ 212000,
+ kukui_p097pfg_ssd2858_edid,
+ lcm_p097pfg_ssd2858_init_cmd),
+ {{PANEL_KUKUI_UNKNOWN}, "PANEL_KUKUI_UNKNOWN",
+ 0, NULL, NULL, 0},
+};
+
+static union panel_id kukui_get_panel_id(struct board_display_intf *intf)
+{
+ if (board_id() < 2)
+ return (union panel_id)PANEL_KUKUI_INNOLUX;
+ else
+ return (union panel_id)PANEL_KUKUI_P097PFG_SSD2858;
+};
+
+static bool kukui_is_panel_id_valid(union panel_id id)
+{
+ if (id.value < PANEL_KUKUI_UNKNOWN)
+ return true;
+ return false;
+};
+
+static int kukui_backlight(struct board_display_intf *intf)
+{
+ gpio_output(GPIO(PERIPHERAL_EN13), 1);
+ gpio_output(GPIO(DISP_PWM), 1); /* DISP_PWM0 */
+
+ return 0;
+};
+
+static int kukui_power(struct board_display_intf *intf)
+{
+ if (board_id() < 2) {
+ /* board from p1 */
+ gpio_output(GPIO(LCM_RST), 0);
+ udelay(100);
+ gpio_output(GPIO(LCM_RST), 1);
+ mdelay(20);
+ } else {
+ /* board from p2 */
+ gpio_output(GPIO(LCM_RST), 0);
+ gpio_output(GPIO(BPI_BUS3), 0);
+ gpio_output(GPIO(MISC_BSI_CK_3), 1);
+ gpio_output(GPIO(PERIPHERAL_EN9), 1);
+ gpio_output(GPIO(SIM2_SRST), 1);
+ gpio_output(GPIO(SIM2_SIO), 1);
+ gpio_output(GPIO(BPI_OLAT1), 1);
+ gpio_output(GPIO(SIM2_SCLK), 1);
+ mdelay(20);
+ gpio_output(GPIO(LCM_RST), 1);
+ mdelay(20);
+ gpio_output(GPIO(BPI_BUS3), 1);
+ mdelay(20);
+ }
+
+ return 0;
+
+};
+
+struct board_display_intf panel_display_intf = {
+ .board = "kukui",
+ .all_panel_info = kukui_panel_info,
+ .all_panel_info_size = ARRAY_SIZE(kukui_panel_info),
+ .cur_panel_info = NULL,
+ .get_panel_id = &kukui_get_panel_id,
+ .is_panel_id_valid = &kukui_is_panel_id_valid,
+ .backlight = &kukui_backlight,
+ .power = &kukui_power,
+};
diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc
index ce498c1..0afa335 100644
--- a/src/soc/mediatek/mt8183/Makefile.inc
+++ b/src/soc/mediatek/mt8183/Makefile.inc
@@ -42,6 +42,8 @@
ramstage-y += auxadc.c
ramstage-y += ../common/cbmem.c emi.c
+ramstage-y += ddp.c
+ramstage-y += dsi.c
ramstage-y += ../common/gpio.c gpio.c
ramstage-y += ../common/mmu_operations.c mmu_operations.c
ramstage-y += ../common/mtcmos.c mtcmos.c
diff --git a/src/soc/mediatek/mt8183/ddp.c b/src/soc/mediatek/mt8183/ddp.c
new file mode 100644
index 0000000..d845981
--- /dev/null
+++ b/src/soc/mediatek/mt8183/ddp.c
@@ -0,0 +1,202 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <delay.h>
+#include <device/mmio.h>
+#include <edid.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stddef.h>
+#include <soc/addressmap.h>
+#include <soc/ddp.h>
+
+#define RDMA_FIFO_PSEUDO_SIZE(bytes) (((bytes) / 16) << 16)
+#define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16)
+
+static void disp_config_main_path_connection(void)
+{
+ write32(&mmsys_cfg->disp_ovl0_mout_en, OVL0_MOUT_EN_OVL0_2L);
+ write32(&mmsys_cfg->disp_ovl0_2l_mout_en, OVL0_2L_MOUT_EN_DISP_PATH0);
+ write32(&mmsys_cfg->disp_path0_sel_in, DISP_PATH0_SEL_IN_OVL0_2L);
+ write32(&mmsys_cfg->disp_rdma0_sout_sel_in, RDMA0_SOUT_SEL_IN_COLOR);
+ write32(&mmsys_cfg->disp_dither0_mout_en, DITHER0_MOUT_EN_DISP_DSI0);
+ write32(&mmsys_cfg->dsi0_sel_in, DSI0_SEL_IN_DITHER0_MOUT);
+}
+
+static void disp_config_main_path_mutex(void)
+{
+ write32(&disp_mutex->mutex[0].mod, MUTEX_MOD_MAIN_PATH);
+
+ /* Clock source from DSI0 */
+ write32(&disp_mutex->mutex[0].ctl,
+ MUTEX_SOF_DSI0 | (MUTEX_SOF_DSI0 << 6));
+ write32(&disp_mutex->mutex[0].en, BIT(0));
+}
+
+static void ovl_set_roi(u32 idx, u32 width, u32 height, u32 color)
+{
+ write32(&disp_ovl[idx]->roi_size, height << 16 | width);
+ write32(&disp_ovl[idx]->roi_bgclr, color);
+}
+
+static void ovl_layer_enable(u32 idx)
+{
+ write32(&disp_ovl[idx]->rdma[0].ctrl, BIT(0));
+ write32(&disp_ovl[idx]->rdma[0].mem_gmc_setting, RDMA_MEM_GMC);
+
+ setbits_le32(&disp_ovl[idx]->src_con, BIT(0));
+}
+
+static void ovl_bgclr_in_sel(u32 idx)
+{
+ setbits_le32(&disp_ovl[idx]->datapath_con, BIT(2));
+}
+
+static void rdma_start(u32 idx)
+{
+ setbits_le32(&disp_rdma[idx]->global_con, RDMA_ENGINE_EN);
+}
+
+static void rdma_config(u32 idx, u32 width, u32 height, u32 vrefresh)
+{
+ u32 threshold;
+ u32 reg;
+ u32 fifo_size;
+
+ clrsetbits_le32(&disp_rdma[idx]->size_con_0, 0x1FFF, width);
+ clrsetbits_le32(&disp_rdma[idx]->size_con_1, 0xFFFFF, height);
+
+ /*
+ * Enable FIFO underflow since DSI and DPI can't be blocked. Keep the
+ * FIFO pseudo size reset default of 8 KiB. Set the output threshold to
+ * 6 microseconds with 7/6 overhead to account for blanking, and with a
+ * pixel depth of 4 bytes:
+ */
+ fifo_size = RDMA_FIFO_SIZE_0 * KiB;
+
+ threshold = width * height * vrefresh * 4 * 7 / 1000000;
+
+ if (threshold > fifo_size)
+ threshold = fifo_size;
+
+ reg = RDMA_FIFO_UNDERFLOW_EN |
+ RDMA_FIFO_PSEUDO_SIZE(fifo_size) |
+ RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);
+
+ write32(&disp_rdma[idx]->fifo_con, reg);
+}
+
+static void color_start(u32 width, u32 height)
+{
+ write32(&disp_color->width, width);
+ write32(&disp_color->height, height);
+ write32(&disp_color->cfg_main, COLOR_BYPASS_ALL | COLOR_SEQ_SEL);
+ write32(&disp_color->start, BIT(0));
+}
+
+static void aal_start(u32 width, u32 height)
+{
+ write32(&disp_aal->size, height << 16 | width);
+ write32(&disp_aal->en, PQ_EN);
+}
+
+static void ccorr_start(u32 width, u32 height)
+{
+ write32(&disp_ccorr->size, height << 16 | width);
+ write32(&disp_ccorr->cfg, PQ_RELAY_MODE);
+ write32(&disp_ccorr->en, PQ_EN);
+}
+
+static void dither_start(u32 width, u32 height)
+{
+ write32(&disp_dither->size, height << 16 | width);
+ write32(&disp_dither->cfg, PQ_RELAY_MODE);
+ write32(&disp_dither->en, PQ_EN);
+}
+
+static void gamma_start(u32 width, u32 height)
+{
+ write32(&disp_gamma->size, height << 16 | width);
+ write32(&disp_gamma->en, PQ_EN);
+}
+
+static void ovl_layer_config(u32 idx, u32 fmt, u32 bpp, u32 width, u32 height)
+{
+ write32(&disp_ovl[idx]->layer[0].con, fmt << 12);
+ write32(&disp_ovl[idx]->layer[0].src_size, height << 16 | width);
+ write32(&disp_ovl[idx]->layer[0].pitch, (width * bpp) & 0xFFFF);
+
+ ovl_layer_enable(idx);
+}
+
+static void main_disp_path_setup(u32 width, u32 height, u32 vrefresh)
+{
+ u32 idx = 0;
+
+ /* Setup OVL */
+ for (idx = 0; idx < MAIN_PATH_OVL_NR; idx++) {
+ u32 color = 0;
+
+ if (idx == 0)
+ color = 0xFF0000FF;
+
+ ovl_set_roi(idx, width, height, color);
+ }
+
+ idx = 0;
+ rdma_config(idx, width, height, vrefresh);
+ color_start(width, height);
+ ccorr_start(width, height);
+ aal_start(width, height);
+ gamma_start(width, height);
+ dither_start(width, height);
+ disp_config_main_path_connection();
+ disp_config_main_path_mutex();
+}
+
+static void disp_clock_on(void)
+{
+ clrbits_le32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_DISP_ALL);
+
+ clrbits_le32(&mmsys_cfg->mmsys_cg_con1, CG_CON1_DISP_DSI0 |
+ CG_CON1_DISP_DSI0_INTERFACE);
+}
+
+static void disp_m4u_port_off(void)
+{
+ write32((void *)(SMI_LARB0 + SMI_LARB_NON_SEC_CON), 0);
+}
+
+void mtk_ddp_init(void)
+{
+ disp_clock_on();
+ disp_m4u_port_off();
+}
+
+void mtk_ddp_mode_set(const struct edid *edid)
+{
+ u32 fmt = OVL_INFMT_RGBA8888;
+ u32 bpp = edid->framebuffer_bits_per_pixel / 8;
+ u32 idx = 0;
+ u32 width = edid->mode.ha;
+ u32 height = edid->mode.va;
+ u32 vrefresh = edid->mode.refresh;
+
+ main_disp_path_setup(width, height, vrefresh);
+ rdma_start(idx);
+ ovl_layer_config(idx, fmt, bpp, width, height);
+ ovl_bgclr_in_sel(idx+1);
+}
diff --git a/src/soc/mediatek/mt8183/dsi.c b/src/soc/mediatek/mt8183/dsi.c
new file mode 100644
index 0000000..3bfada7
--- /dev/null
+++ b/src/soc/mediatek/mt8183/dsi.c
@@ -0,0 +1,485 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/mmio.h>
+#include <console/console.h>
+#include <delay.h>
+#include <soc/addressmap.h>
+#include <soc/dsi.h>
+#include <timer.h>
+
+static void dsi_write32(void *a, uint32_t v)
+{
+ write32(a, v);
+}
+
+static void dsi_clrsetbits_le32(void *a, uint32_t m, uint32_t v)
+{
+ clrsetbits_le32(a, m, v);
+}
+
+static void dsi_clrbits_le32(void *a, uint32_t m)
+{
+ clrbits_le32(a, m);
+}
+
+static void dsi_setbits_le32(void *a, uint32_t m)
+{
+ setbits_le32(a, m);
+}
+
+static int mtk_dsi_phy_clk_setting(u32 format, u32 lanes,
+ const struct edid *edid)
+{
+ unsigned int txdiv, txdiv0, txdiv1;
+ u64 pcw;
+ int data_rate;
+ u32 bpp;
+
+ switch (format) {
+ case MIPI_DSI_FMT_RGB565:
+ bpp = 16;
+ break;
+ case MIPI_DSI_FMT_RGB666:
+ case MIPI_DSI_FMT_RGB666_PACKED:
+ bpp = 18;
+ break;
+ case MIPI_DSI_FMT_RGB888:
+ default:
+ bpp = 24;
+ break;
+ }
+
+ data_rate = (u64)(edid->mode.pixel_clock * 1000 * bpp) / lanes;
+
+ printk(BIOS_INFO, "data_rate: %u bps\n", data_rate);
+
+ if (data_rate >= 2000000000) {
+ txdiv = 1;
+ txdiv0 = 0;
+ txdiv1 = 0;
+ } else if (data_rate >= 1000000000) {
+ txdiv = 2;
+ txdiv0 = 1;
+ txdiv1 = 0;
+ } else if (data_rate >= 500000000) {
+ txdiv = 4;
+ txdiv0 = 2;
+ txdiv1 = 0;
+ } else if (data_rate > 250000000) {
+ txdiv = 8;
+ txdiv0 = 3;
+ txdiv1 = 0;
+ } else if (data_rate >= 125000000) {
+ txdiv = 16;
+ txdiv0 = 4;
+ txdiv1 = 0;
+ } else {
+ printk(BIOS_ERR, "data rate (%u) must be >=50. Please check "
+ "pixel clock (%u), bpp (%u), number of lanes (%u)\n",
+ data_rate, edid->mode.pixel_clock, bpp,
+ lanes);
+ return -1;
+ }
+
+ dsi_clrbits_le32(mipi_tx + MIPITX_PLL_CON4, BIT(11) | BIT(10));
+
+ dsi_setbits_le32(mipi_tx + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON);
+ udelay(30);
+ dsi_clrbits_le32(mipi_tx + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN);
+
+ pcw = (u64)((data_rate / 1000000) * (1 << txdiv0) * (1 << txdiv1));
+ pcw <<= 24;
+ pcw /= 26;
+
+ dsi_write32(mipi_tx + MIPITX_PLL_CON0, pcw);
+ dsi_clrsetbits_le32(mipi_tx + MIPITX_PLL_CON1, RG_DSI_PLL_POSDIV,
+ txdiv0 << 8);
+ udelay(30);
+ dsi_setbits_le32(mipi_tx + MIPITX_PLL_CON1, RG_DSI_PLL_EN);
+
+ /* BG_LPF_EN / BG_CORE_EN */
+ dsi_write32(mipi_tx + MIPITX_LANE_CON, 0x3FFF0180);
+ udelay(40);
+ dsi_write32(mipi_tx + MIPITX_LANE_CON, 0x3FFF00c0);
+
+ /* Switch OFF each Lane */
+ dsi_clrbits_le32(mipi_tx + MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN);
+ dsi_clrbits_le32(mipi_tx + MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN);
+ dsi_clrbits_le32(mipi_tx + MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN);
+ dsi_clrbits_le32(mipi_tx + MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN);
+ dsi_clrbits_le32(mipi_tx + MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN);
+
+ dsi_setbits_le32(mipi_tx + MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN);
+
+ return data_rate;
+}
+
+static void mtk_dsi_phy_timconfig(u32 data_rate,
+ struct mtk_phy_timing *phy_timing)
+{
+ u32 timcon0, timcon1, timcon2, timcon3;
+
+ timcon0 = phy_timing->lpx | phy_timing->da_hs_prepare << 8 |
+ phy_timing->da_hs_zero << 16 | phy_timing->da_hs_trail << 24;
+ timcon1 = phy_timing->ta_go | phy_timing->ta_sure << 8 |
+ phy_timing->ta_get << 16 | phy_timing->da_hs_exit << 24;
+ timcon2 = 1 << 8 | phy_timing->clk_hs_zero << 16 |
+ phy_timing->clk_hs_trail << 24;
+ timcon3 = phy_timing->clk_hs_prepare | phy_timing->clk_hs_post << 8 |
+ phy_timing->clk_hs_exit << 16;
+
+ dsi_write32(&dsi->dsi_phy_timecon0, timcon0);
+ dsi_write32(&dsi->dsi_phy_timecon1, timcon1);
+ dsi_write32(&dsi->dsi_phy_timecon2, timcon2);
+ dsi_write32(&dsi->dsi_phy_timecon3, timcon3);
+}
+
+static void mtk_dsi_reset(void)
+{
+ dsi_write32(&dsi->dsi_con_ctrl, 1);
+ dsi_write32(&dsi->dsi_con_ctrl, 0);
+}
+
+static void mtk_dsi_clk_hs_mode_enable(void)
+{
+ dsi_setbits_le32(&dsi->dsi_phy_lccon, 1);
+}
+
+static void mtk_dsi_set_mode(u32 mode_flags)
+{
+ u32 tmp_reg1 = 0;
+
+ if (mode_flags & MIPI_DSI_MODE_VIDEO) {
+ tmp_reg1 = SYNC_PULSE_MODE;
+
+ if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
+ tmp_reg1 = BURST_MODE;
+
+ if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
+ tmp_reg1 = SYNC_PULSE_MODE;
+ }
+
+ dsi_write32(&dsi->dsi_mode_ctrl, tmp_reg1);
+}
+
+static void mtk_dsi_phy_timing_calc(u32 format, u32 lanes,
+ const struct edid *edid,
+ struct mtk_phy_timing *phy_timing)
+{
+ u32 ui, cycle_time, data_rate;
+ u32 bit_per_pixel;
+
+ switch (format) {
+ case MIPI_DSI_FMT_RGB565:
+ bit_per_pixel = 16;
+ break;
+ case MIPI_DSI_FMT_RGB666:
+ case MIPI_DSI_FMT_RGB666_PACKED:
+ bit_per_pixel = 18;
+ break;
+ case MIPI_DSI_FMT_RGB888:
+ default:
+ bit_per_pixel = 24;
+ break;
+ }
+
+ data_rate = edid->mode.pixel_clock * bit_per_pixel / lanes;
+
+ ui = 1000 / (data_rate / 1000) + 1U;
+ cycle_time = 8000 / (data_rate / 1000) + 1U;
+
+ phy_timing->lpx = DIV_ROUND_UP(60, cycle_time);
+ phy_timing->da_hs_prepare = DIV_ROUND_UP((40 + 5 * ui), cycle_time);
+ phy_timing->da_hs_zero = DIV_ROUND_UP((180 + 6 * ui), cycle_time);
+ phy_timing->da_hs_trail = DIV_ROUND_UP(((4 * ui) + 80), cycle_time);
+
+ if (phy_timing->da_hs_zero > phy_timing->da_hs_prepare)
+ phy_timing->da_hs_zero -= phy_timing->da_hs_prepare;
+
+ phy_timing->ta_go = 4U * phy_timing->lpx;
+ phy_timing->ta_sure = 3U * phy_timing->lpx / 2U;
+ phy_timing->ta_get = 5U * phy_timing->lpx;
+ phy_timing->da_hs_exit = 2U * phy_timing->lpx;
+
+ phy_timing->clk_hs_zero = DIV_ROUND_UP(0x150U, cycle_time);
+ phy_timing->clk_hs_trail = DIV_ROUND_UP(0x64U, cycle_time) + 0xaU;
+
+ phy_timing->clk_hs_prepare = DIV_ROUND_UP(0x40U, cycle_time);
+ phy_timing->clk_hs_post = DIV_ROUND_UP(80U + 52U * ui, cycle_time);
+ phy_timing->clk_hs_exit = 2U * phy_timing->lpx;
+}
+
+static void mtk_dsi_rxtx_control(u32 mode_flags, u32 lanes)
+{
+ u32 tmp_reg = 0;
+
+ switch (lanes) {
+ case 1:
+ tmp_reg = 1 << 2;
+ break;
+ case 2:
+ tmp_reg = 3 << 2;
+ break;
+ case 3:
+ tmp_reg = 7 << 2;
+ break;
+ case 4:
+ default:
+ tmp_reg = 0xf << 2;
+ break;
+ }
+
+ tmp_reg |= (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6;
+ tmp_reg |= (mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3;
+
+ dsi_write32(&dsi->dsi_txrx_ctrl, tmp_reg);
+}
+
+static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format,
+ const struct edid *edid,
+ struct mtk_phy_timing *phy_timing,
+ u32 lanes)
+{
+ u32 hsync_active_byte;
+ u32 hbp_byte;
+ u32 hfp_byte, tmp_hfp_byte;
+ u32 vbp_byte;
+ u32 vfp_byte;
+ u32 bpp;
+ u32 packet_fmt;
+ u32 hactive;
+ u32 data_phy_cycles;
+
+ if (format == MIPI_DSI_FMT_RGB565)
+ bpp = 2;
+ else
+ bpp = 3;
+
+ vbp_byte = edid->mode.vbl - edid->mode.vso - edid->mode.vspw -
+ edid->mode.vborder;
+ vfp_byte = edid->mode.vso - edid->mode.vborder;
+
+ dsi_write32(&dsi->dsi_vsa_nl, edid->mode.vspw);
+ dsi_write32(&dsi->dsi_vbp_nl, vbp_byte);
+ dsi_write32(&dsi->dsi_vfp_nl, vfp_byte);
+ dsi_write32(&dsi->dsi_vact_nl, edid->mode.va);
+
+ if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
+ hbp_byte = (edid->mode.hbl - edid->mode.hso - edid->mode.hspw -
+ edid->mode.hborder) * bpp - 10;
+ else
+ hbp_byte = (edid->mode.hbl - edid->mode.hso -
+ edid->mode.hborder) * bpp - 10;
+
+ hsync_active_byte = edid->mode.hspw * bpp - 10;
+
+ data_phy_cycles = phy_timing->lpx + phy_timing->da_hs_prepare +
+ phy_timing->da_hs_zero + phy_timing->da_hs_exit + 2;
+
+ tmp_hfp_byte = (edid->mode.hso - edid->mode.hborder) * bpp;
+
+ if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
+ if (tmp_hfp_byte > data_phy_cycles * lanes + 18) {
+ hfp_byte = tmp_hfp_byte - data_phy_cycles * lanes - 18;
+ } else {
+ printk(BIOS_ERR, "HFP less than d-phy, FPS will under 60Hz\n");
+ hfp_byte = tmp_hfp_byte;
+ }
+ } else {
+ if (tmp_hfp_byte > data_phy_cycles * lanes + 12) {
+ hfp_byte = tmp_hfp_byte - data_phy_cycles * lanes - 12;
+ } else {
+ printk(BIOS_ERR, "HFP less than d-phy, FPS will under 60Hz\n");
+ hfp_byte = tmp_hfp_byte;
+ }
+ }
+
+ dsi_write32(&dsi->dsi_hsa_wc, hsync_active_byte);
+ dsi_write32(&dsi->dsi_hbp_wc, hbp_byte);
+ dsi_write32(&dsi->dsi_hfp_wc, hfp_byte);
+
+ switch (format) {
+ case MIPI_DSI_FMT_RGB888:
+ packet_fmt = PACKED_PS_24BIT_RGB888;
+ break;
+ case MIPI_DSI_FMT_RGB666:
+ packet_fmt = LOOSELY_PS_18BIT_RGB666;
+ break;
+ case MIPI_DSI_FMT_RGB666_PACKED:
+ packet_fmt = PACKED_PS_18BIT_RGB666;
+ break;
+ case MIPI_DSI_FMT_RGB565:
+ packet_fmt = PACKED_PS_16BIT_RGB565;
+ break;
+ default:
+ packet_fmt = PACKED_PS_24BIT_RGB888;
+ break;
+ }
+
+ hactive = edid->mode.ha;
+ packet_fmt |= (hactive * bpp) & DSI_PS_WC;
+
+ dsi_write32(&dsi->dsi_psctrl, 0x2c << 24 | packet_fmt);
+ dsi_write32(&dsi->dsi_size_con, edid->mode.va << 16 | hactive);
+}
+
+static void mtk_dsi_start(void)
+{
+ dsi_clrbits_le32(&dsi->dsi_start, 1);
+ dsi_setbits_le32(&dsi->dsi_start, 1);
+}
+
+static void mtk_dsi_cmdq(u8 *data, u8 len, u32 type)
+{
+ struct stopwatch sw;
+ u8 *tx_buf = data;
+ u8 cmdq_size;
+ u32 reg_val, cmdq_mask, i, config, cmdq_off, intsta_0;
+
+ while (read32(&dsi->dsi_intsta) & (1 << 31)) {
+ printk(BIOS_ERR, "%s wait dsi no busy\n", __func__);
+ mdelay(20);
+ }
+
+ dsi_write32(&dsi->dsi_intsta, 0);
+
+ if (MTK_DSI_HOST_IS_READ(type))
+ config = BTA;
+ else
+ config = (len > 2) ? LONG_PACKET : SHORT_PACKET;
+
+ if (len > 2) {
+ cmdq_size = 1 + (len + 3) / 4;
+ cmdq_off = 4;
+ cmdq_mask = CONFIG | DATA_ID | DATA_0 | DATA_1;
+ reg_val = (len << 16) | (type << 8) | config;
+ } else {
+ cmdq_size = 1;
+ cmdq_off = 2;
+ cmdq_mask = CONFIG | DATA_ID;
+ reg_val = (type << 8) | config;
+ }
+
+ for (i = 0; i < 0x20; i = i + 4)
+ dsi_write32((void *)DSI_BASE + 0x200 + i, 0);
+
+ for (i = 0; i < len; i++) {
+ dsi_clrsetbits_le32((void *)DSI_BASE + 0x200 +
+ ((cmdq_off + i) & (0xfffffffc)),
+ (0xff << (((i + cmdq_off) & 3) * 8)),
+ tx_buf[i] << (((i + cmdq_off) & 3) * 8));
+ }
+
+ dsi_clrsetbits_le32(&dsi->dsi_cmdq0, cmdq_mask, reg_val);
+ dsi_clrsetbits_le32(&dsi->dsi_cmdq_size, CMDQ_SIZE, cmdq_size);
+ mtk_dsi_start();
+
+ stopwatch_init_usecs_expire(&sw, 400);
+ do {
+ intsta_0 = read32(&dsi->dsi_intsta);
+ if (intsta_0 & CMD_DONE_INT_FLAG)
+ break;
+ udelay(4);
+ } while (!stopwatch_expired(&sw));
+
+ if (!(intsta_0 & CMD_DONE_INT_FLAG))
+ printk(BIOS_ERR, "dsi send cmd time-out(400uS)\n");
+}
+
+static void push_table(struct lcm_init_table *init_cmd, u32 count)
+{
+ u32 cmd, i;
+ u32 type;
+
+ for (i = 0; i < count; i++) {
+ cmd = init_cmd[i].cmd;
+
+ switch (cmd) {
+ case DELAY_CMD:
+ mdelay(init_cmd[i].len);
+ break;
+
+ case END_OF_TABLE:
+ break;
+
+ case INIT_DCS_CMD:
+ switch (init_cmd[i].len) {
+ case 0:
+ return;
+
+ case 1:
+ type = MIPI_DSI_DCS_SHORT_WRITE;
+ break;
+
+ case 2:
+ type = MIPI_DSI_DCS_SHORT_WRITE_PARAM;
+ break;
+
+ default:
+ type = MIPI_DSI_DCS_LONG_WRITE;
+ break;
+ }
+ mtk_dsi_cmdq(init_cmd[i].data, init_cmd[i].len, type);
+ break;
+
+ case INIT_GENENIC_CMD:
+ default:
+ switch (init_cmd[i].len) {
+ case 0:
+ type = MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM;
+ break;
+ case 1:
+ type = MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM;
+ break;
+ case 2:
+ type = MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM;
+ break;
+ default:
+ type = MIPI_DSI_GENERIC_LONG_WRITE;
+ break;
+ }
+ mtk_dsi_cmdq(init_cmd[i].data, init_cmd[i].len, type);
+ break;
+ }
+ }
+}
+
+int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, bool dual,
+ const struct edid *edid, struct lcm_init_table *init_cmd,
+ u32 count)
+{
+ int data_rate;
+ struct mtk_phy_timing phy_timing;
+
+ mtk_dsi_phy_timing_calc(format, lanes, edid, &phy_timing);
+
+ data_rate = mtk_dsi_phy_clk_setting(format, lanes, edid);
+
+ if (data_rate < 0)
+ return -1;
+
+ dsi_write32(&dsi->dsi_force_commit, 3);
+ mtk_dsi_reset();
+ mtk_dsi_phy_timconfig(data_rate, &phy_timing);
+ mtk_dsi_rxtx_control(mode_flags, lanes);
+ mtk_dsi_config_vdo_timing(mode_flags, format, edid, &phy_timing, lanes);
+ mtk_dsi_clk_hs_mode_enable();
+ push_table(init_cmd, count);
+ mtk_dsi_set_mode(mode_flags);
+ mtk_dsi_start();
+
+ return 0;
+}
diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h
index d41b2b9..75202dd 100644
--- a/src/soc/mediatek/mt8183/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h
@@ -47,12 +47,27 @@
IOCFG_RT_BASE = IO_PHYS + 0x01C50000,
IOCFG_RM_BASE = IO_PHYS + 0x01D20000,
IOCFG_RB_BASE = IO_PHYS + 0x01D30000,
+ MIPITX_BASE = IO_PHYS + 0x01E50000,
IOCFG_LB_BASE = IO_PHYS + 0x01E70000,
IOCFG_LM_BASE = IO_PHYS + 0x01E80000,
IOCFG_BL_BASE = IO_PHYS + 0x01E90000,
IOCFG_LT_BASE = IO_PHYS + 0x01F20000,
IOCFG_TL_BASE = IO_PHYS + 0x01F30000,
SSUSB_SIF_BASE = IO_PHYS + 0x01F40300,
+ MMSYS_BASE = IO_PHYS + 0x04000000,
+ DISP_OVL0_BASE = IO_PHYS + 0x04008000,
+ DISP_OVL0_2L_BASE = IO_PHYS + 0x04009000,
+ DISP_OVL1_2L_BASE = IO_PHYS + 0x0400A000,
+ DISP_RDMA0_BASE = IO_PHYS + 0x0400B000,
+ DISP_RDMA1_BASE = IO_PHYS + 0x0400C000,
+ DISP_COLOR0_BASE = IO_PHYS + 0x0400E000,
+ DISP_CCORR0_BASE = IO_PHYS + 0x0400F000,
+ DISP_AAL0_BASE = IO_PHYS + 0x04010000,
+ DISP_GAMMA0_BASE = IO_PHYS + 0x04011000,
+ DISP_DITHER0_BASE = IO_PHYS + 0x04012000,
+ DSI_BASE = IO_PHYS + 0x04014000,
+ DISP_MUTEX_BASE = IO_PHYS + 0x04016000,
+ SMI_LARB0 = IO_PHYS + 0x04017000,
SMI_BASE = IO_PHYS + 0x04019000,
};
diff --git a/src/soc/mediatek/mt8183/include/soc/ddp.h b/src/soc/mediatek/mt8183/include/soc/ddp.h
new file mode 100644
index 0000000..1914868
--- /dev/null
+++ b/src/soc/mediatek/mt8183/include/soc/ddp.h
@@ -0,0 +1,315 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DDP_REG_H_
+#define _DDP_REG_H_
+
+#include <soc/addressmap.h>
+#include <types.h>
+
+#define MAIN_PATH_OVL_NR 2
+
+struct mmsys_cfg_regs {
+ u32 reserved_0x000[64]; /* 0x000 */
+ u32 mmsys_cg_con0; /* 0x100 */
+ u32 mmsys_cg_set0; /* 0x104 */
+ u32 mmsys_cg_clr0; /* 0x108 */
+ u32 reserved_0x10C; /* 0x10C */
+ u32 mmsys_cg_con1; /* 0x110 */
+ u32 mmsys_cg_set1; /* 0x114 */
+ u32 mmsys_cg_clr1; /* 0x118 */
+ u32 reserved_0x11C[889]; /* 0x11C */
+ u32 disp_ovl0_mout_en; /* 0xF00 */
+ u32 disp_ovl0_2l_mout_en; /* 0xF04 */
+ u32 disp_ovl1_2l_mout_en; /* 0xF08 */
+ u32 disp_dither0_mout_en; /* 0xF0C */
+ u32 reserved_0xF10[5]; /* 0xF10 - 0xF20 */
+ u32 disp_path0_sel_in; /* 0xF24 */
+ u32 reserved_0xF28; /* 0xF28 */
+ u32 dsi0_sel_in; /* 0xF2C */
+ u32 dpi0_sel_in; /* 0xF30 */
+ u32 reserved_0xF34; /* 0xF34 */
+ u32 disp_ovl0_2l_sel_in; /* 0xF38 */
+ u32 reserved_0xF3C[5]; /* 0xF3C - 0xF4C */
+ u32 disp_rdma0_sout_sel_in; /* 0xF50 */
+ u32 disp_rdma1_sout_sel_in; /* 0xF54 */
+ u32 reserved_0xF58[3]; /* 0xF58 - 0xF60 */
+ u32 dpi0_sel_sout_sel_in; /* 0xF64 */
+};
+
+check_member(mmsys_cfg_regs, mmsys_cg_con0, 0x100);
+check_member(mmsys_cfg_regs, dpi0_sel_sout_sel_in, 0xF64);
+static struct mmsys_cfg_regs *const mmsys_cfg =
+ (void *)MMSYS_BASE;
+
+
+/* DISP_REG_CONFIG_MMSYS_CG_CON0
+ Configures free-run clock gating 0
+ 0: Enable clock
+ 1: Clock gating */
+enum {
+ CG_CON0_SMI_COMMON = BIT(0),
+ CG_CON0_SMI_LARB0 = BIT(1),
+ CG_CON0_GALS_COMMON0 = BIT(3),
+ CG_CON0_GALS_COMMON1 = BIT(4),
+ CG_CON0_DISP_OVL0 = BIT(20),
+ CG_CON0_DISP_OVL0_2L = BIT(21),
+ CG_CON0_DISP_OVL1_2L = BIT(22),
+ CG_CON0_DISP_RDMA0 = BIT(23),
+ CG_CON0_DISP_RDMA1 = BIT(24),
+ CG_CON0_DISP_WDMA0 = BIT(25),
+ CG_CON0_DISP_COLOR0 = BIT(26),
+ CG_CON0_DISP_CCORR0 = BIT(27),
+ CG_CON0_DISP_AAL0 = BIT(28),
+ CG_CON0_DISP_GAMMA0 = BIT(29),
+ CG_CON0_DISP_DITHER0 = BIT(30),
+ CG_CON0_DISP_ALL = CG_CON0_SMI_COMMON |
+ CG_CON0_SMI_LARB0 |
+ CG_CON0_GALS_COMMON0 |
+ CG_CON0_GALS_COMMON1 |
+ CG_CON0_DISP_OVL0 |
+ CG_CON0_DISP_OVL0_2L |
+ CG_CON0_DISP_RDMA0 |
+ CG_CON0_DISP_COLOR0 |
+ CG_CON0_DISP_CCORR0 |
+ CG_CON0_DISP_AAL0 |
+ CG_CON0_DISP_DITHER0 |
+ CG_CON0_DISP_GAMMA0,
+ CG_CON0_ALL = 0xffffffff
+};
+
+/* DISP_REG_CONFIG_MMSYS_CG_CON1
+ Configures free-run clock gating 1
+ 0: Enable clock
+ 1: Clock gating */
+enum {
+ CG_CON1_DISP_DSI0 = BIT(0),
+ CG_CON1_DISP_DSI0_INTERFACE = BIT(1),
+ CG_CON1_DISP_26M = BIT(7),
+
+ CG_CON1_ALL = 0xffffffff
+};
+
+enum {
+ OVL0_MOUT_EN_RDMA0 = BIT(0),
+ OVL0_MOUT_EN_OVL0_2L = BIT(4),
+ OVL0_2L_MOUT_EN_DISP_PATH0 = BIT(0),
+ OVL1_2L_MOUT_EN_DISP_RDMA1 = BIT(4),
+ DITHER0_MOUT_EN_DISP_DSI0 = BIT(0),
+};
+
+enum {
+ DISP_PATH0_SEL_IN_OVL0 = 0,
+ DISP_PATH0_SEL_IN_OVL0_2L = 1,
+ DSI0_SEL_IN_DITHER0_MOUT = 0,
+ DSI0_SEL_IN_RDMA0 = 1,
+ RDMA0_SOUT_SEL_IN_DSI0 = 0,
+ RDMA0_SOUT_SEL_IN_COLOR = 1,
+};
+
+struct disp_mutex_regs {
+ u32 inten;
+ u32 intsta;
+ u32 reserved0[6];
+ struct {
+ u32 en;
+ u32 dummy;
+ u32 rst;
+ u32 ctl;
+ u32 mod;
+ u32 reserved[3];
+ } mutex[12];
+};
+
+static struct disp_mutex_regs *const disp_mutex = (void *)DISP_MUTEX_BASE;
+
+enum {
+ MUTEX_MOD_DISP_RDMA0 = BIT(0),
+ MUTEX_MOD_DISP_RDMA1 = BIT(1),
+ MUTEX_MOD_DISP_OVL0 = BIT(9),
+ MUTEX_MOD_DISP_OVL0_2L = BIT(10),
+ MUTEX_MOD_DISP_OVL1_2L = BIT(11),
+ MUTEX_MOD_DISP_WDMA0 = BIT(12),
+ MUTEX_MOD_DISP_COLOR0 = BIT(13),
+ MUTEX_MOD_DISP_CCORR0 = BIT(14),
+ MUTEX_MOD_DISP_AAL0 = BIT(15),
+ MUTEX_MOD_DISP_GAMMA0 = BIT(16),
+ MUTEX_MOD_DISP_DITHER0 = BIT(17),
+ MUTEX_MOD_DISP_PWM0 = BIT(28),
+ MUTEX_MOD_MAIN_PATH = MUTEX_MOD_DISP_OVL0 | MUTEX_MOD_DISP_OVL0_2L |
+ MUTEX_MOD_DISP_RDMA0 | MUTEX_MOD_DISP_COLOR0 |
+ MUTEX_MOD_DISP_CCORR0 | MUTEX_MOD_DISP_AAL0 |
+ MUTEX_MOD_DISP_GAMMA0 |
+ MUTEX_MOD_DISP_DITHER0,
+};
+
+enum {
+ MUTEX_SOF_SINGLE_MODE = 0,
+ MUTEX_SOF_DSI0 = 1,
+ MUTEX_SOF_DPI0 = 2,
+};
+
+struct disp_ovl_regs {
+ u32 sta;
+ u32 inten;
+ u32 intsta;
+ u32 en;
+ u32 trig;
+ u32 rst;
+ u32 reserved_0x018[2];
+ u32 roi_size;
+ u32 datapath_con;
+ u32 roi_bgclr;
+ u32 src_con;
+ struct {
+ u32 con;
+ u32 srckey;
+ u32 src_size;
+ u32 offset;
+ u32 reserved0;
+ u32 pitch;
+ u32 reserved1[2];
+ } layer[4];
+ u32 reserved_0x0B0[4];
+ struct {
+ u32 ctrl;
+ u32 reserved0;
+ u32 mem_gmc_setting;
+ u32 mem_slow_con;
+ u32 fifo_ctrl;
+ u32 reserved1[3];
+ } rdma[4];
+ u32 reserved_0x140[880];
+ u32 reserved_0xF00[16];
+ u32 l0_addr;
+ u32 reserved_0xF44[7];
+ u32 l1_addr;
+ u32 reserved_0xF64[7];
+ u32 l2_addr;
+ u32 reserved_0xF84[7];
+ u32 l3_addr;
+};
+
+check_member(disp_ovl_regs, l3_addr, 0xFA0);
+static struct disp_ovl_regs *const disp_ovl[2] = {
+ (void *)DISP_OVL0_BASE, (void *)DISP_OVL0_2L_BASE
+};
+
+struct disp_rdma_regs {
+ u32 int_enable;
+ u32 int_status;
+ u32 reserved0[2];
+ u32 global_con;
+ u32 size_con_0;
+ u32 size_con_1;
+ u32 target_line;
+ u32 reserved1;
+ u32 mem_con;
+ u32 reserved2;
+ u32 mem_src_pitch;
+ u32 mem_gmc_setting_0;
+ u32 mem_gmc_setting_1;
+ u32 mem_slow_con;
+ u32 mem_gmc_setting_2;
+ u32 fifo_con;
+ u32 reserved3[4];
+ u32 cf[3][3];
+ u32 cf_pre_add[3];
+ u32 cf_post_add[3];
+ u32 dummy;
+ u32 debug_out_sel;
+};
+
+enum {
+ RDMA_ENGINE_EN = BIT(0),
+ RDMA_FIFO_UNDERFLOW_EN = BIT(31),
+ RDMA_FIFO_SIZE_0 = 5, /* 5K */
+ RDMA_VREFRESH = 60, /* vrefresh 60HZ */
+ RDMA_MEM_GMC = 0x40402020,
+};
+
+check_member(disp_rdma_regs, debug_out_sel, 0x94);
+static struct disp_rdma_regs *const disp_rdma[2] = {
+ (void *)DISP_RDMA0_BASE,
+ (void *)DISP_RDMA1_BASE,
+};
+
+struct disp_color_regs {
+ u8 reserved0[1024];
+ u32 cfg_main;
+ u8 reserved1[2044];
+ u32 start;
+ u8 reserved2[76];
+ u32 width;
+ u32 height;
+};
+
+check_member(disp_color_regs, height, 0xC54);
+static struct disp_color_regs *const disp_color = (void *)DISP_COLOR0_BASE;
+
+enum {
+ COLOR_BYPASS_ALL = BIT(7),
+ COLOR_SEQ_SEL = BIT(13),
+};
+
+struct disp_pq_regs {
+ u32 en;
+ u32 reset;
+ u32 inten;
+ u32 intsta;
+ u32 status;
+ u32 reserved0[3];
+ u32 cfg;
+ u32 reserved1[3];
+ u32 size;
+};
+
+enum {
+ PQ_EN = BIT(0),
+ PQ_RELAY_MODE = BIT(0),
+};
+
+static struct disp_pq_regs *const disp_ccorr = (void *)DISP_CCORR0_BASE;
+
+static struct disp_pq_regs *const disp_aal = (void *)DISP_AAL0_BASE;
+
+static struct disp_pq_regs *const disp_gamma = (void *)DISP_GAMMA0_BASE;
+
+static struct disp_pq_regs *const disp_dither = (void *)DISP_DITHER0_BASE;
+
+enum {
+ SMI_LARB_NON_SEC_CON = 0x380,
+};
+
+enum OVL_INPUT_FORMAT {
+ OVL_INFMT_RGB565 = 0,
+ OVL_INFMT_RGB888 = 1,
+ OVL_INFMT_RGBA8888 = 2,
+ OVL_INFMT_ARGB8888 = 3,
+ OVL_INFMT_UYVY = 4,
+ OVL_INFMT_YUYV = 5,
+ OVL_INFMT_UNKNOWN = 16,
+
+ OVL_COLOR_BASE = 30,
+ OVL_INFMT_BGR565 = OVL_INFMT_RGB565 + OVL_COLOR_BASE,
+ OVL_INFMT_BGR888 = OVL_INFMT_RGB888 + OVL_COLOR_BASE,
+ OVL_INFMT_BGRA8888 = OVL_INFMT_RGBA8888 + OVL_COLOR_BASE,
+ OVL_INFMT_ABGR8888 = OVL_INFMT_ARGB8888 + OVL_COLOR_BASE,
+};
+
+void mtk_ddp_init(void);
+void mtk_ddp_mode_set(const struct edid *edid);
+
+#endif
diff --git a/src/soc/mediatek/mt8183/include/soc/dsi.h b/src/soc/mediatek/mt8183/include/soc/dsi.h
new file mode 100644
index 0000000..dc89668
--- /dev/null
+++ b/src/soc/mediatek/mt8183/include/soc/dsi.h
@@ -0,0 +1,487 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DSI_REG_H_
+#define _DSI_REG_H_
+
+#include <edid.h>
+#include <soc/addressmap.h>
+#include <types.h>
+
+enum mipi_dsi_pixel_format {
+ MIPI_DSI_FMT_RGB888,
+ MIPI_DSI_FMT_RGB666,
+ MIPI_DSI_FMT_RGB666_PACKED,
+ MIPI_DSI_FMT_RGB565
+};
+
+/* video mode */
+enum {
+ MIPI_DSI_MODE_VIDEO = BIT(0),
+ /* video burst mode */
+ MIPI_DSI_MODE_VIDEO_BURST = BIT(1),
+ /* video pulse mode */
+ MIPI_DSI_MODE_VIDEO_SYNC_PULSE = BIT(2),
+ /* enable auto vertical count mode */
+ MIPI_DSI_MODE_VIDEO_AUTO_VERT = BIT(3),
+ /* enable hsync-end packets in vsync-pulse and v-porch area */
+ MIPI_DSI_MODE_VIDEO_HSE = BIT(4),
+ /* disable hfront-porch area */
+ MIPI_DSI_MODE_VIDEO_HFP = BIT(5),
+ /* disable hback-porch area */
+ MIPI_DSI_MODE_VIDEO_HBP = BIT(6),
+ /* disable hsync-active area */
+ MIPI_DSI_MODE_VIDEO_HSA = BIT(7),
+ /* flush display FIFO on vsync pulse */
+ MIPI_DSI_MODE_VSYNC_FLUSH = BIT(8),
+ /* disable EoT packets in HS mode */
+ MIPI_DSI_MODE_EOT_PACKET = BIT(9),
+ /* device supports non-continuous clock behavior (DSI spec 5.6.1) */
+ MIPI_DSI_CLOCK_NON_CONTINUOUS = BIT(10),
+ /* transmit data in low power */
+ MIPI_DSI_MODE_LPM = BIT(11)
+};
+
+struct dsi_regs {
+ u32 dsi_start;
+ u8 reserved0[4];
+ u32 dsi_inten;
+ u32 dsi_intsta;
+ u32 dsi_con_ctrl;
+ u32 dsi_mode_ctrl;
+ u32 dsi_txrx_ctrl;
+ u32 dsi_psctrl;
+ u32 dsi_vsa_nl;
+ u32 dsi_vbp_nl;
+ u32 dsi_vfp_nl;
+ u32 dsi_vact_nl;
+ u32 dsi_lfr_con;
+ u32 dsi_lfr_sta;
+ u32 dsi_size_con;
+ u32 dsi_vfp_early_stop;
+ u32 reserved1[4];
+ u32 dsi_hsa_wc;
+ u32 dsi_hbp_wc;
+ u32 dsi_hfp_wc;
+ u32 dsi_bllp_wc;
+ u32 dsi_cmdq_size;
+ u32 dsi_hstx_cklp_wc;
+ u8 reserved2[156];
+ u32 dsi_phy_lccon;
+ u32 dsi_phy_ld0con;
+ u8 reserved3[4];
+ u32 dsi_phy_timecon0;
+ u32 dsi_phy_timecon1;
+ u32 dsi_phy_timecon2;
+ u32 dsi_phy_timecon3;
+ u8 reserved4[16];
+ u32 dsi_vm_cmd_con;
+ u8 reserved5[92];
+ u32 dsi_force_commit;
+ u8 reserved6[108];
+ u32 dsi_cmdq0;
+};
+
+check_member(dsi_regs, dsi_phy_lccon, 0x104);
+check_member(dsi_regs, dsi_phy_timecon3, 0x11c);
+check_member(dsi_regs, dsi_vm_cmd_con, 0x130);
+check_member(dsi_regs, dsi_force_commit, 0x190);
+check_member(dsi_regs, dsi_cmdq0, 0x200);
+static struct dsi_regs *const dsi = (void *)DSI_BASE;
+
+#define DELAY_CMD 0
+#define END_OF_TABLE 1
+#define INIT_GENENIC_CMD 2
+#define INIT_DCS_CMD 3
+
+struct lcm_init_table {
+ u32 cmd;
+ u32 len;
+ u8 data[64];
+};
+
+struct mtk_phy_timing {
+ u8 lpx;
+ u8 da_hs_prepare;
+ u8 da_hs_zero;
+ u8 da_hs_trail;
+
+ u8 ta_go;
+ u8 ta_sure;
+ u8 ta_get;
+ u8 da_hs_exit;
+
+ u8 clk_hs_zero;
+ u8 clk_hs_trail;
+
+ u8 clk_hs_prepare;
+ u8 clk_hs_post;
+ u8 clk_hs_exit;
+};
+
+/* DSI_INTSTA */
+enum {
+ LPRX_RD_RDY_INT_FLAG = BIT(0),
+ CMD_DONE_INT_FLAG = BIT(1),
+ TE_RDY_INT_FLAG = BIT(2),
+ VM_DONE_INT_FLAG = BIT(3),
+ EXT_TE_RDY_INT_FLAG = BIT(4),
+ DSI_BUSY = BIT(31),
+};
+
+/* DSI_CON_CTRL */
+enum {
+ DSI_RESET = BIT(0),
+ DSI_EN = BIT(1),
+ DSI_DUAL = BIT(4),
+};
+
+/* DSI_MODE_CTRL */
+enum {
+ MODE = 3,
+ CMD_MODE = 0,
+ SYNC_PULSE_MODE = 1,
+ SYNC_EVENT_MODE = 2,
+ BURST_MODE = 3,
+ FRM_MODE = BIT(16),
+ MIX_MODE = BIT(17)
+};
+
+/* DSI_PSCTRL */
+enum {
+ DSI_PS_WC = 0x3fff,
+ DSI_PS_SEL = (3 << 16),
+ PACKED_PS_16BIT_RGB565 = (0 << 16),
+ LOOSELY_PS_18BIT_RGB666 = (1 << 16),
+ PACKED_PS_18BIT_RGB666 = (2 << 16),
+ PACKED_PS_24BIT_RGB888 = (3 << 16)
+};
+
+/* DSI_CMDQ_SIZE */
+enum {
+ CMDQ_SIZE = 0x3f,
+};
+
+/* DSI_PHY_LCCON */
+enum {
+ LC_HS_TX_EN = BIT(0),
+ LC_ULPM_EN = BIT(1),
+ LC_WAKEUP_EN = BIT(2)
+};
+
+/*DSI_PHY_LD0CON */
+enum {
+ LD0_RM_TRIG_EN = BIT(0),
+ LD0_ULPM_EN = BIT(1),
+ LD0_WAKEUP_EN = BIT(2)
+};
+
+enum {
+ LPX = (0xff << 0),
+ HS_PRPR = (0xff << 8),
+ HS_ZERO = (0xff << 16),
+ HS_TRAIL = (0xff << 24)
+};
+
+enum {
+ TA_GO = (0xff << 0),
+ TA_SURE = (0xff << 8),
+ TA_GET = (0xff << 16),
+ DA_HS_EXIT = (0xff << 24)
+};
+
+enum {
+ CONT_DET = (0xff << 0),
+ CLK_ZERO = (0xf << 16),
+ CLK_TRAIL = (0xff << 24)
+};
+
+enum {
+ CLK_HS_PRPR = (0xff << 0),
+ CLK_HS_POST = (0xff << 8),
+ CLK_HS_EXIT = (0xf << 16)
+};
+
+/* DSI_VM_CMD_CON */
+enum {
+ VM_CMD_EN = BIT(0),
+ TS_VFP_EN = BIT(5),
+};
+
+/* DSI_CMDQ0 */
+enum {
+ CONFIG = (0xff << 0),
+ SHORT_PACKET = 0,
+ LONG_PACKET = 2,
+ BTA = BIT(2),
+ DATA_ID = (0xff << 8),
+ DATA_0 = (0xff << 16),
+ DATA_1 = (0xff << 24),
+};
+
+#define MIPITX_LANE_CON 0x000c
+#define MIPITX_PLL_PWR 0x0028
+#define MIPITX_PLL_CON0 0x002c
+#define MIPITX_PLL_CON1 0x0030
+#define MIPITX_PLL_CON2 0x0034
+#define MIPITX_PLL_CON3 0x0038
+#define MIPITX_PLL_CON4 0x003c
+#define MIPITX_D2_SW_CTL_EN 0x0144
+#define MIPITX_D0_SW_CTL_EN 0x0244
+#define MIPITX_CK_CKMODE_EN 0x0328
+#define DSI_CK_CKMODE_EN BIT(0)
+#define MIPITX_CK_SW_CTL_EN 0x0344
+#define MIPITX_D1_SW_CTL_EN 0x0444
+#define MIPITX_D3_SW_CTL_EN 0x0544
+#define DSI_SW_CTL_EN BIT(0)
+#define AD_DSI_PLL_SDM_PWR_ON BIT(0)
+#define AD_DSI_PLL_SDM_ISO_EN BIT(1)
+
+#define RG_DSI_PLL_EN BIT(4)
+#define RG_DSI_PLL_POSDIV (0x7 << 8)
+
+/* MIPITX_REG */
+struct mipi_tx_regs {
+ u32 dsi_con;
+ u32 dsi_clock_lane;
+ u32 dsi_data_lane[4];
+ u8 reserved0[40];
+ u32 dsi_top_con;
+ u32 dsi_bg_con;
+ u8 reserved1[8];
+ u32 dsi_pll_con0;
+ u32 dsi_pll_con1;
+ u32 dsi_pll_con2;
+ u32 dsi_pll_con3;
+ u32 dsi_pll_chg;
+ u32 dsi_pll_top;
+ u32 dsi_pll_pwr;
+ u8 reserved2[4];
+ u32 dsi_rgs;
+ u32 dsi_gpi_en;
+ u32 dsi_gpi_pull;
+ u32 dsi_phy_sel;
+ u32 dsi_sw_ctrl_en;
+ u32 dsi_sw_ctrl_con0;
+ u32 dsi_sw_ctrl_con1;
+ u32 dsi_sw_ctrl_con2;
+ u32 dsi_dbg_con;
+ u32 dsi_dbg_out;
+ u32 dsi_apb_async_sta;
+};
+
+check_member(mipi_tx_regs, dsi_top_con, 0x40);
+check_member(mipi_tx_regs, dsi_pll_pwr, 0x68);
+
+static void *const mipi_tx = (void *)MIPITX_BASE;
+
+/* MIPITX_DSI_CON */
+enum {
+ RG_DSI_LDOCORE_EN = BIT(0),
+ RG_DSI_CKG_LDOOUT_EN = BIT(1),
+ RG_DSI_BCLK_SEL = (3 << 2),
+ RG_DSI_LD_IDX_SEL = (7 << 4),
+ RG_DSI_PHYCLK_SEL = (2 << 8),
+ RG_DSI_DSICLK_FREQ_SEL = BIT(10),
+ RG_DSI_LPTX_CLMP_EN = BIT(11)
+};
+
+/* MIPITX_DSI_CLOCK_LANE */
+enum {
+ LDOOUT_EN = BIT(0),
+ CKLANE_EN = BIT(1),
+ IPLUS1 = BIT(2),
+ LPTX_IPLUS2 = BIT(3),
+ LPTX_IMINUS = BIT(4),
+ LPCD_IPLUS = BIT(5),
+ LPCD_IMLUS = BIT(6),
+ RT_CODE = (0xf << 8)
+};
+
+/* MIPITX_DSI_TOP_CON */
+enum {
+ RG_DSI_LNT_INTR_EN = BIT(0),
+ RG_DSI_LNT_HS_BIAS_EN = BIT(1),
+ RG_DSI_LNT_IMP_CAL_EN = BIT(2),
+ RG_DSI_LNT_TESTMODE_EN = BIT(3),
+ RG_DSI_LNT_IMP_CAL_CODE = (0xf << 4),
+ RG_DSI_LNT_AIO_SEL = (7 << 8),
+ RG_DSI_PAD_TIE_LOW_EN = BIT(11),
+ RG_DSI_DEBUG_INPUT_EN = BIT(12),
+ RG_DSI_PRESERVE = (7 << 13)
+};
+
+/* MIPITX_DSI_BG_CON */
+enum {
+ RG_DSI_BG_CORE_EN = BIT(0),
+ RG_DSI_BG_CKEN = BIT(1),
+ RG_DSI_BG_DIV = (0x3 << 2),
+ RG_DSI_BG_FAST_CHARGE = BIT(4),
+ RG_DSI_V12_SEL = (7 << 5),
+ RG_DSI_V10_SEL = (7 << 8),
+ RG_DSI_V072_SEL = (7 << 11),
+ RG_DSI_V04_SEL = (7 << 14),
+ RG_DSI_V032_SEL = (7 << 17),
+ RG_DSI_V02_SEL = (7 << 20),
+ rsv_23 = BIT(23),
+ RG_DSI_BG_R1_TRIM = (0xf << 24),
+ RG_DSI_BG_R2_TRIM = (0xf << 28)
+};
+
+/* MIPITX_DSI_PLL_CON0 */
+enum {
+ RG_DSI_MPPLL_PLL_EN = BIT(0),
+ RG_DSI_MPPLL_PREDIV = (3 << 1),
+ RG_DSI_MPPLL_TXDIV0 = (3 << 3),
+ RG_DSI_MPPLL_TXDIV1 = (3 << 5),
+ RG_DSI_MPPLL_POSDIV = (7 << 7),
+ RG_DSI_MPPLL_MONVC_EN = BIT(10),
+ RG_DSI_MPPLL_MONREF_EN = BIT(11),
+ RG_DSI_MPPLL_VOD_EN = BIT(12)
+};
+
+/* MIPITX_DSI_PLL_CON1 */
+enum {
+ RG_DSI_MPPLL_SDM_FRA_EN = BIT(0),
+ RG_DSI_MPPLL_SDM_SSC_PH_INIT = BIT(1),
+ RG_DSI_MPPLL_SDM_SSC_EN = BIT(2),
+ RG_DSI_MPPLL_SDM_SSC_PRD = (0xffff << 16)
+};
+
+/* MIPITX_DSI_PLL_PWR */
+enum {
+ RG_DSI_MPPLL_SDM_PWR_ON = BIT(0),
+ RG_DSI_MPPLL_SDM_ISO_EN = BIT(1),
+ RG_DSI_MPPLL_SDM_PWR_ACK = BIT(8)
+};
+
+/* MIPI DSI Processor-to-Peripheral transaction types */
+enum {
+ MIPI_DSI_V_SYNC_START = 0x01,
+ MIPI_DSI_V_SYNC_END = 0x11,
+ MIPI_DSI_H_SYNC_START = 0x21,
+ MIPI_DSI_H_SYNC_END = 0x31,
+
+ MIPI_DSI_COLOR_MODE_OFF = 0x02,
+ MIPI_DSI_COLOR_MODE_ON = 0x12,
+ MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22,
+ MIPI_DSI_TURN_ON_PERIPHERAL = 0x32,
+
+ MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 0x03,
+ MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 0x13,
+ MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 0x23,
+
+ MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 0x04,
+ MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 0x14,
+ MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 0x24,
+
+ MIPI_DSI_DCS_SHORT_WRITE = 0x05,
+ MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15,
+
+ MIPI_DSI_DCS_READ = 0x06,
+
+ MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37,
+
+ MIPI_DSI_END_OF_TRANSMISSION = 0x08,
+
+ MIPI_DSI_NULL_PACKET = 0x09,
+ MIPI_DSI_BLANKING_PACKET = 0x19,
+ MIPI_DSI_GENERIC_LONG_WRITE = 0x29,
+ MIPI_DSI_DCS_LONG_WRITE = 0x39,
+
+ MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c,
+ MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c,
+ MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c,
+
+ MIPI_DSI_PACKED_PIXEL_STREAM_30 = 0x0d,
+ MIPI_DSI_PACKED_PIXEL_STREAM_36 = 0x1d,
+ MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 = 0x3d,
+
+ MIPI_DSI_PACKED_PIXEL_STREAM_16 = 0x0e,
+ MIPI_DSI_PACKED_PIXEL_STREAM_18 = 0x1e,
+ MIPI_DSI_PIXEL_STREAM_3BYTE_18 = 0x2e,
+ MIPI_DSI_PACKED_PIXEL_STREAM_24 = 0x3e,
+};
+
+/* MIPI DSI Peripheral-to-Processor transaction types */
+enum {
+ MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT = 0x02,
+ MIPI_DSI_RX_END_OF_TRANSMISSION = 0x08,
+ MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE = 0x11,
+ MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE = 0x12,
+ MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE = 0x1a,
+ MIPI_DSI_RX_DCS_LONG_READ_RESPONSE = 0x1c,
+ MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE = 0x21,
+ MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE = 0x22,
+};
+
+/* MIPI DCS commands */
+enum {
+ MIPI_DCS_NOP = 0x00,
+ MIPI_DCS_SOFT_RESET = 0x01,
+ MIPI_DCS_GET_DISPLAY_ID = 0x04,
+ MIPI_DCS_GET_RED_CHANNEL = 0x06,
+ MIPI_DCS_GET_GREEN_CHANNEL = 0x07,
+ MIPI_DCS_GET_BLUE_CHANNEL = 0x08,
+ MIPI_DCS_GET_DISPLAY_STATUS = 0x09,
+ MIPI_DCS_GET_POWER_MODE = 0x0A,
+ MIPI_DCS_GET_ADDRESS_MODE = 0x0B,
+ MIPI_DCS_GET_PIXEL_FORMAT = 0x0C,
+ MIPI_DCS_GET_DISPLAY_MODE = 0x0D,
+ MIPI_DCS_GET_SIGNAL_MODE = 0x0E,
+ MIPI_DCS_GET_DIAGNOSTIC_RESULT = 0x0F,
+ MIPI_DCS_ENTER_SLEEP_MODE = 0x10,
+ MIPI_DCS_EXIT_SLEEP_MODE = 0x11,
+ MIPI_DCS_ENTER_PARTIAL_MODE = 0x12,
+ MIPI_DCS_ENTER_NORMAL_MODE = 0x13,
+ MIPI_DCS_EXIT_INVERT_MODE = 0x20,
+ MIPI_DCS_ENTER_INVERT_MODE = 0x21,
+ MIPI_DCS_SET_GAMMA_CURVE = 0x26,
+ MIPI_DCS_SET_DISPLAY_OFF = 0x28,
+ MIPI_DCS_SET_DISPLAY_ON = 0x29,
+ MIPI_DCS_SET_COLUMN_ADDRESS = 0x2A,
+ MIPI_DCS_SET_PAGE_ADDRESS = 0x2B,
+ MIPI_DCS_WRITE_MEMORY_START = 0x2C,
+ MIPI_DCS_WRITE_LUT = 0x2D,
+ MIPI_DCS_READ_MEMORY_START = 0x2E,
+ MIPI_DCS_SET_PARTIAL_AREA = 0x30,
+ MIPI_DCS_SET_SCROLL_AREA = 0x33,
+ MIPI_DCS_SET_TEAR_OFF = 0x34,
+ MIPI_DCS_SET_TEAR_ON = 0x35,
+ MIPI_DCS_SET_ADDRESS_MODE = 0x36,
+ MIPI_DCS_SET_SCROLL_START = 0x37,
+ MIPI_DCS_EXIT_IDLE_MODE = 0x38,
+ MIPI_DCS_ENTER_IDLE_MODE = 0x39,
+ MIPI_DCS_SET_PIXEL_FORMAT = 0x3A,
+ MIPI_DCS_WRITE_MEMORY_CONTINUE = 0x3C,
+ MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E,
+ MIPI_DCS_SET_TEAR_SCANLINE = 0x44,
+ MIPI_DCS_GET_SCANLINE = 0x45,
+ MIPI_DCS_READ_DDB_START = 0xA1,
+ MIPI_DCS_READ_DDB_CONTINUE = 0xA8,
+};
+
+#define MTK_DSI_HOST_IS_READ(type) \
+ ((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \
+ (type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \
+ (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
+ (type == MIPI_DSI_DCS_READ))
+
+extern int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, bool dual,
+ const struct edid *edid,
+ struct lcm_init_table *init_cmd,
+ u32 count);
+
+#endif
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I09d127ab491bca98f3a9c9b7d4ad4b09674c963d
Gerrit-Change-Number: 33106
Gerrit-PatchSet: 1
Gerrit-Owner: jitao shi <jitao.shi(a)mediatek.com>
Gerrit-MessageType: newchange
3
6
Change in coreboot[master]: drivers/analogix: improve the clock tolance from 0.1% to 2%
by jitao shi (Code Review) 27 Mar '21
by jitao shi (Code Review) 27 Mar '21
27 Mar '21
jitao shi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39025 )
Change subject: drivers/analogix: improve the clock tolance from 0.1% to 2%
......................................................................
drivers/analogix: improve the clock tolance from 0.1% to 2%
Improve the input tolance to avoid panel scroll.
BUG=b:149051882
BRANCH=kukui
TEST=None
Change-Id: I4af96f58876932175b28fc0a8543720ebd7b5deb
Signed-off-by: Jitao Shi <jitao.shi(a)mediatek.com>
---
M src/drivers/analogix/anx7625/anx7625.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/39025/1
diff --git a/src/drivers/analogix/anx7625/anx7625.c b/src/drivers/analogix/anx7625/anx7625.c
index 9387a83b..d2d09d8 100644
--- a/src/drivers/analogix/anx7625/anx7625.c
+++ b/src/drivers/analogix/anx7625/anx7625.c
@@ -395,7 +395,7 @@
ret |= anx7625_reg_write(bus, RX_P1_ADDR, MIPI_PLL_N_NUM_7_0,
(n & 0xff));
/* diff */
- ret |= anx7625_reg_write(bus, RX_P1_ADDR, MIPI_DIGITAL_ADJ_1, 0x37);
+ ret |= anx7625_reg_write(bus, RX_P1_ADDR, MIPI_DIGITAL_ADJ_1, 0x3d);
ret |= anx7625_odfc_config(bus, post_divider - 1);
--
To view, visit https://review.coreboot.org/c/coreboot/+/39025
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I4af96f58876932175b28fc0a8543720ebd7b5deb
Gerrit-Change-Number: 39025
Gerrit-PatchSet: 1
Gerrit-Owner: jitao shi <jitao.shi(a)mediatek.com>
Gerrit-MessageType: newchange
6
15
Change in ...coreboot[master]: getac/p470: Let clang-format handle the coding style
by Patrick Georgi (Code Review) 26 Mar '21
by Patrick Georgi (Code Review) 26 Mar '21
26 Mar '21
Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31652
Change subject: getac/p470: Let clang-format handle the coding style
......................................................................
getac/p470: Let clang-format handle the coding style
Also make the format mandatory for the board.
Change-Id: Ib34af7c4db359e132b968fe8409580af05fba9e3
Signed-off-by: Patrick Georgi <pgeorgi(a)google.com>
---
A .clang-format-scope
M src/mainboard/getac/p470/acpi_tables.c
M src/mainboard/getac/p470/cstates.c
M src/mainboard/getac/p470/ec_oem.c
M src/mainboard/getac/p470/ec_oem.h
M src/mainboard/getac/p470/gpio.c
M src/mainboard/getac/p470/hda_verb.c
M src/mainboard/getac/p470/irq_tables.c
M src/mainboard/getac/p470/mainboard.c
M src/mainboard/getac/p470/mainboard.h
M src/mainboard/getac/p470/mptable.c
M src/mainboard/getac/p470/romstage.c
M src/mainboard/getac/p470/smihandler.c
13 files changed, 179 insertions(+), 136 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/31652/1
diff --git a/.clang-format-scope b/.clang-format-scope
new file mode 100644
index 0000000..96c588c
--- /dev/null
+++ b/.clang-format-scope
@@ -0,0 +1 @@
+src/mainboard/getac
diff --git a/src/mainboard/getac/p470/acpi_tables.c b/src/mainboard/getac/p470/acpi_tables.c
index 162c20a..460f345 100644
--- a/src/mainboard/getac/p470/acpi_tables.c
+++ b/src/mainboard/getac/p470/acpi_tables.c
@@ -33,7 +33,7 @@
gnvs->cmbp = 0x00;
}
-static long acpi_create_ecdt(acpi_ecdt_t * ecdt)
+static long acpi_create_ecdt(acpi_ecdt_t *ecdt)
{
/* Attention: Make sure these match the values from
* the DSDT's ec.asl
@@ -43,7 +43,7 @@
acpi_header_t *header = &(ecdt->header);
- memset((void *) ecdt, 0, ecdt_len);
+ memset((void *)ecdt, 0, ecdt_len);
/* fill out header fields */
memcpy(header->signature, "ECDT", 4);
@@ -61,7 +61,7 @@
ecdt->ec_control.addrl = 0x66;
ecdt->ec_control.addrh = 0;
- ecdt->ec_data.space_id = ACPI_ADDRESS_SPACE_IO; /* Memory */
+ ecdt->ec_data.space_id = ACPI_ADDRESS_SPACE_IO; /* Memory */
ecdt->ec_data.bit_width = 8;
ecdt->ec_data.bit_offset = 0;
ecdt->ec_data.addrl = 0x62;
@@ -73,14 +73,12 @@
strncpy((char *)ecdt->ec_id, ec_id, strlen(ec_id));
- header->checksum =
- acpi_checksum((void *) ecdt, ecdt_len);
+ header->checksum = acpi_checksum((void *)ecdt, ecdt_len);
return header->length;
}
-unsigned long mainboard_write_acpi_tables(struct device *device,
- unsigned long start,
+unsigned long mainboard_write_acpi_tables(struct device *device, unsigned long start,
acpi_rsdp_t *rsdp)
{
unsigned long current;
diff --git a/src/mainboard/getac/p470/cstates.c b/src/mainboard/getac/p470/cstates.c
index 38b0d30..2f1f815 100644
--- a/src/mainboard/getac/p470/cstates.c
+++ b/src/mainboard/getac/p470/cstates.c
@@ -16,21 +16,21 @@
#include <southbridge/intel/i82801gx/i82801gx.h>
static acpi_cstate_t cst_entries[] = {
- {
- /* ACPI C1 / CPU C1 */
- 1, 0x01, 1000,
- { ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0, 0 }
- },
- {
- /* ACPI C2 / CPU C2 */
- 2, 0x01, 500,
- { ACPI_ADDRESS_SPACE_IO, 8, 0, { 0 }, DEFAULT_PMBASE + LV2, 0 }
- },
- {
- /* ACPI C3 / CPU C2 */
- 2, 0x11, 250,
- { ACPI_ADDRESS_SPACE_IO, 8, 0, { 0 }, DEFAULT_PMBASE + LV3, 0 }
- },
+ {/* ACPI C1 / CPU C1 */
+ 1,
+ 0x01,
+ 1000,
+ {ACPI_ADDRESS_SPACE_FIXED, 1, 2, {1}, 0, 0}},
+ {/* ACPI C2 / CPU C2 */
+ 2,
+ 0x01,
+ 500,
+ {ACPI_ADDRESS_SPACE_IO, 8, 0, {0}, DEFAULT_PMBASE + LV2, 0}},
+ {/* ACPI C3 / CPU C2 */
+ 2,
+ 0x11,
+ 250,
+ {ACPI_ADDRESS_SPACE_IO, 8, 0, {0}, DEFAULT_PMBASE + LV3, 0}},
};
int get_cst_entries(acpi_cstate_t **entries)
diff --git a/src/mainboard/getac/p470/ec_oem.c b/src/mainboard/getac/p470/ec_oem.c
index 8740167..49b7274 100644
--- a/src/mainboard/getac/p470/ec_oem.c
+++ b/src/mainboard/getac/p470/ec_oem.c
@@ -32,7 +32,7 @@
}
if (!timeout) {
printk(BIOS_DEBUG, "Timeout while sending OEM command 0x%02x to EC!\n",
- command);
+ command);
// return -1;
}
@@ -51,8 +51,7 @@
printk(BIOS_SPEW, ".");
}
if (!timeout) {
- printk(BIOS_DEBUG, "Timeout while sending OEM data 0x%02x to EC!\n",
- data);
+ printk(BIOS_DEBUG, "Timeout while sending OEM data 0x%02x to EC!\n", data);
// return -1;
}
@@ -112,12 +111,18 @@
{
u8 ec_sc = inb(EC_OEM_SC);
printk(BIOS_DEBUG, "Embedded Controller Status: ");
- if (ec_sc & (1 << 6)) printk(BIOS_DEBUG, "SMI_EVT ");
- if (ec_sc & (1 << 5)) printk(BIOS_DEBUG, "SCI_EVT ");
- if (ec_sc & (1 << 4)) printk(BIOS_DEBUG, "BURST ");
- if (ec_sc & (1 << 3)) printk(BIOS_DEBUG, "CMD ");
- if (ec_sc & (1 << 1)) printk(BIOS_DEBUG, "IBF ");
- if (ec_sc & (1 << 0)) printk(BIOS_DEBUG, "OBF ");
+ if (ec_sc & (1 << 6))
+ printk(BIOS_DEBUG, "SMI_EVT ");
+ if (ec_sc & (1 << 5))
+ printk(BIOS_DEBUG, "SCI_EVT ");
+ if (ec_sc & (1 << 4))
+ printk(BIOS_DEBUG, "BURST ");
+ if (ec_sc & (1 << 3))
+ printk(BIOS_DEBUG, "CMD ");
+ if (ec_sc & (1 << 1))
+ printk(BIOS_DEBUG, "IBF ");
+ if (ec_sc & (1 << 0))
+ printk(BIOS_DEBUG, "OBF ");
printk(BIOS_DEBUG, "\n");
return ec_sc;
diff --git a/src/mainboard/getac/p470/ec_oem.h b/src/mainboard/getac/p470/ec_oem.h
index 5d56107..ba42d7e 100644
--- a/src/mainboard/getac/p470/ec_oem.h
+++ b/src/mainboard/getac/p470/ec_oem.h
@@ -17,23 +17,35 @@
#ifndef _MAINBOARD_EC_OEM_H
#define _MAINBOARD_EC_OEM_H
-#define EC_OEM_DATA 0x68
-#define EC_OEM_SC 0x6c
+#define EC_OEM_DATA 0x68
+#define EC_OEM_SC 0x6c
/* EC_SC input */
-#define EC_SMI_EVT (1 << 6) // 1: SMI event pending
-#define EC_SCI_EVT (1 << 5) // 1: SCI event pending
-#define EC_BURST (1 << 4) // controller is in burst mode
-#define EC_CMD (1 << 3) // 1: byte in data register is command
- // 0: byte in data register is data
-#define EC_IBF (1 << 1) // 1: input buffer full (data ready for ec)
-#define EC_OBF (1 << 0) // 1: output buffer full (data ready for host)
+// 1: SMI event pending
+#define EC_SMI_EVT (1 << 6)
+
+// 1: SCI event pending
+#define EC_SCI_EVT (1 << 5)
+
+// controller is in burst mode
+#define EC_BURST (1 << 4)
+
+// 1: byte in data register is command
+// 0: byte in data register is data
+#define EC_CMD (1 << 3)
+
+// 1: input buffer full (data ready for ec)
+#define EC_IBF (1 << 1)
+
+// 1: output buffer full (data ready for host)
+#define EC_OBF (1 << 0)
+
/* EC_SC output */
-#define RD_EC 0x80 // Read Embedded Controller
-#define WR_EC 0x81 // Write Embedded Controller
-#define BE_EC 0x82 // Burst Enable Embedded Controller
-#define BD_EC 0x83 // Burst Disable Embedded Controller
-#define QR_EC 0x84 // Query Embedded Controller
+#define RD_EC 0x80 // Read Embedded Controller
+#define WR_EC 0x81 // Write Embedded Controller
+#define BE_EC 0x82 // Burst Enable Embedded Controller
+#define BD_EC 0x83 // Burst Disable Embedded Controller
+#define QR_EC 0x84 // Query Embedded Controller
int send_ec_oem_command(u8 command);
int send_ec_oem_data(u8 data);
diff --git a/src/mainboard/getac/p470/gpio.c b/src/mainboard/getac/p470/gpio.c
index be52a86..2785bca 100644
--- a/src/mainboard/getac/p470/gpio.c
+++ b/src/mainboard/getac/p470/gpio.c
@@ -74,8 +74,7 @@
.gpio8 = GPIO_INVERT,
};
-static const struct pch_gpio_set1 pch_gpio_set1_blink = {
-};
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {};
static const struct pch_gpio_set2 pch_gpio_set2_mode = {
.gpio33 = GPIO_MODE_GPIO,
@@ -100,16 +99,18 @@
};
const struct pch_gpio_map mainboard_gpio_map = {
- .set1 = {
- .mode = &pch_gpio_set1_mode,
- .direction = &pch_gpio_set1_direction,
- .level = &pch_gpio_set1_level,
- .blink = &pch_gpio_set1_blink,
- .invert = &pch_gpio_set1_invert,
- },
- .set2 = {
- .mode = &pch_gpio_set2_mode,
- .direction = &pch_gpio_set2_direction,
- .level = &pch_gpio_set2_level,
- },
+ .set1 =
+ {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ },
+ .set2 =
+ {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ },
};
diff --git a/src/mainboard/getac/p470/hda_verb.c b/src/mainboard/getac/p470/hda_verb.c
index e858a35..1ec2205 100644
--- a/src/mainboard/getac/p470/hda_verb.c
+++ b/src/mainboard/getac/p470/hda_verb.c
@@ -17,9 +17,9 @@
const u32 cim_verb_data[] = {
/* coreboot specific header */
- 0x10ec0262, // Codec Vendor / Device ID: Realtek ALC262
- 0x10714700, // Subsystem ID
- 0x0000000d, // Number of jacks
+ 0x10ec0262, // Codec Vendor / Device ID: Realtek ALC262
+ 0x10714700, // Subsystem ID
+ 0x0000000d, // Number of jacks
/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10ec0000 */
AZALIA_SUBVENDOR(0x0, 0x10EC0000),
diff --git a/src/mainboard/getac/p470/irq_tables.c b/src/mainboard/getac/p470/irq_tables.c
index 06d1492..fa491bf 100644
--- a/src/mainboard/getac/p470/irq_tables.c
+++ b/src/mainboard/getac/p470/irq_tables.c
@@ -17,18 +17,19 @@
#include <arch/pirq_routing.h>
static const struct irq_routing_table intel_irq_routing_table = {
- PIRQ_SIGNATURE, /* u32 signature */
- PIRQ_VERSION, /* u16 version */
- 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total 18 devices on the bus */
- 0x00, /* Where the interrupt router lies (bus) */
- (0x1f << 3)|0x0, /* Where the interrupt router lies (dev) */
- 0, /* IRQs devoted exclusively to PCI usage */
- 0x8086, /* Vendor */
- 0x27b0, /* Device */
- 0, /* miniport */
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
- 0xf, /* u8 checksum. */
+ PIRQ_SIGNATURE, /* u32 signature */
+ PIRQ_VERSION, /* u16 version */
+ 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* There can be total 18 devices on the bus */
+ 0x00, /* Where the interrupt router lies (bus) */
+ (0x1f << 3) | 0x0, /* Where the interrupt router lies (dev) */
+ 0, /* IRQs devoted exclusively to PCI usage */
+ 0x8086, /* Vendor */
+ 0x27b0, /* Device */
+ 0, /* miniport */
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
+ 0xf, /* u8 checksum. */
{
+ // clang-format off
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe?
{0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA
@@ -48,8 +49,8 @@
{0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168
{0x02,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0},
{0x03,(0x00 << 3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0},
- }
-};
+ // clang-format on
+ }};
unsigned long write_pirq_routing_table(unsigned long addr)
{
diff --git a/src/mainboard/getac/p470/mainboard.c b/src/mainboard/getac/p470/mainboard.c
index 5d271fd..0645424 100644
--- a/src/mainboard/getac/p470/mainboard.c
+++ b/src/mainboard/getac/p470/mainboard.c
@@ -25,7 +25,7 @@
#include "mainboard.h"
-#define MAX_LCD_BRIGHTNESS 0xd8
+#define MAX_LCD_BRIGHTNESS 0xd8
static void ec_enable(void)
{
@@ -77,7 +77,8 @@
static void mainboard_init(struct device *dev)
{
ec_enable();
- install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_TXT_STRETCH, 0, 3);
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+ GMA_INT15_PANEL_FIT_TXT_STRETCH, 0, 3);
}
// mainboard_enable is executed as first thing after
diff --git a/src/mainboard/getac/p470/mainboard.h b/src/mainboard/getac/p470/mainboard.h
index 0e6b24c..d074960 100644
--- a/src/mainboard/getac/p470/mainboard.h
+++ b/src/mainboard/getac/p470/mainboard.h
@@ -13,6 +13,5 @@
struct acpi_rsdp;
-unsigned long mainboard_write_acpi_tables(struct device *device,
- unsigned long start,
+unsigned long mainboard_write_acpi_tables(struct device *device, unsigned long start,
struct acpi_rsdp *rsdp);
diff --git a/src/mainboard/getac/p470/mptable.c b/src/mainboard/getac/p470/mptable.c
index c00102d..80c33df 100644
--- a/src/mainboard/getac/p470/mptable.c
+++ b/src/mainboard/getac/p470/mptable.c
@@ -41,28 +41,42 @@
mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
/* Builtin devices on Bus 0 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, 0x2, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x2, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2, 0x17);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x2, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x2, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x2, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, 0x2, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, 0x2, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, 0x2, 0x11);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x8, 0x2,
+ 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x2,
+ 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2,
+ 0x17);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x2,
+ 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x2,
+ 0x12);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x2,
+ 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x6c, 0x2,
+ 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x70, 0x2,
+ 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x71, 0x2,
+ 0x11);
/* Firewire 4:0.0 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x0, 0x2, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x4, 0x0, 0x2,
+ 0x10);
// riser slot top 5:8.0
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x20, 0x2, 0x14);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x5, 0x20, 0x2,
+ 0x14);
// riser slot middle 5:9.0
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x24, 0x2, 0x15);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x5, 0x24, 0x2,
+ 0x15);
// riser slot bottom 5:a.0
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x28, 0x2, 0x16);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x5, 0x28, 0x2,
+ 0x16);
/* Onboard Ethernet */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2,
+ 0x10);
/* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
mptable_lintsrc(mc, isa_bus);
diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index 3f80664..a591307 100644
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -36,18 +36,18 @@
printk(BIOS_SPEW, "\n Initializing drive bay...\n");
gpios = inl(DEFAULT_GPIOBASE + 0x38); // GPIO Level 2
- gpios |= (1 << 0); // GPIO33 = ODD
- gpios |= (1 << 1); // GPIO34 = IDE_RST#
- outl(gpios, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */
+ gpios |= (1 << 0); // GPIO33 = ODD
+ gpios |= (1 << 1); // GPIO34 = IDE_RST#
+ outl(gpios, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */
gpios = inl(DEFAULT_GPIOBASE + 0x0c); // GPIO Level
- gpios &= ~(1 << 13); // ??
- outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
+ gpios &= ~(1 << 13); // ??
+ outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
printk(BIOS_SPEW, "\n Initializing Ethernet NIC...\n");
gpios = inl(DEFAULT_GPIOBASE + 0x0c); // GPIO Level
- gpios &= ~(1 << 24); // Enable LAN Power
- outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
+ gpios &= ~(1 << 24); // Enable LAN Power
+ outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
}
static void ich7_enable_lpc(void)
@@ -61,9 +61,10 @@
// decode range
pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0007);
// decode range
- pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN
- | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN
- | FDD_LPC_EN| lpt_en | COMB_LPC_EN | COMA_LPC_EN);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN,
+ CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN
+ | GAMEL_LPC_EN | FDD_LPC_EN | lpt_en | COMB_LPC_EN
+ | COMA_LPC_EN);
// Enable 0x02e0 - 0x2ff
pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x001c02e1);
// Enable 0x600 - 0x6ff
@@ -93,7 +94,7 @@
{
unsigned int port = dev >> 8;
outb(reg, port);
- outb(val, port+1);
+ outb(val, port + 1);
}
static void early_superio_config(void)
@@ -103,15 +104,15 @@
dev = PNP_DEV(0x4e, 0x00);
pnp_enter_ext_func_mode(dev);
- pnp_write_register(dev, 0x02, 0x0e); // UART power
- pnp_write_register(dev, 0x1b, (0x3e8 >> 2)); // UART3 base
- pnp_write_register(dev, 0x1c, (0x2e8 >> 2)); // UART4 base
+ pnp_write_register(dev, 0x02, 0x0e); // UART power
+ pnp_write_register(dev, 0x1b, (0x3e8 >> 2)); // UART3 base
+ pnp_write_register(dev, 0x1c, (0x2e8 >> 2)); // UART4 base
pnp_write_register(dev, 0x1d, (5 << 4) | 11); // UART3,4 IRQ
- pnp_write_register(dev, 0x1e, 1); // no 32khz clock
- pnp_write_register(dev, 0x24, (0x3f8 >> 2)); // UART1 base
- pnp_write_register(dev, 0x28, (4 << 4) | 0); // UART1,2 IRQ
- pnp_write_register(dev, 0x2c, 0); // DMA0 FIR
- pnp_write_register(dev, 0x30, (0x600 >> 4)); // Runtime Register Block Base
+ pnp_write_register(dev, 0x1e, 1); // no 32khz clock
+ pnp_write_register(dev, 0x24, (0x3f8 >> 2)); // UART1 base
+ pnp_write_register(dev, 0x28, (4 << 4) | 0); // UART1,2 IRQ
+ pnp_write_register(dev, 0x2c, 0); // DMA0 FIR
+ pnp_write_register(dev, 0x30, (0x600 >> 4)); // Runtime Register Block Base
pnp_write_register(dev, 0x31, 0xce); // GPIO1 DIR
pnp_write_register(dev, 0x32, 0x00); // GPIO1 POL
@@ -144,8 +145,8 @@
static void rcba_config(void)
{
/* Set up virtual channel 0 */
- //RCBA32(0x0014) = 0x80000001;
- //RCBA32(0x001c) = 0x03128010;
+ // RCBA32(0x0014) = 0x80000001;
+ // RCBA32(0x001c) = 0x03128010;
/* Device 1f interrupt pin register */
RCBA32(D31IP) = 0x00042220;
diff --git a/src/mainboard/getac/p470/smihandler.c b/src/mainboard/getac/p470/smihandler.c
index 5a82044..ca95447 100644
--- a/src/mainboard/getac/p470/smihandler.c
+++ b/src/mainboard/getac/p470/smihandler.c
@@ -115,7 +115,7 @@
case 0xde:
printk(BIOS_DEBUG, "LAN power off\n");
reg32 = inl(DEFAULT_GPIOBASE + GP_LVL);
- reg32 |= (1 << 24); // Disable LAN Power
+ reg32 |= (1 << 24); // Disable LAN Power
outl(reg32, DEFAULT_GPIOBASE + GP_LVL);
break;
case 0xdf:
@@ -151,27 +151,37 @@
u8 reg8;
switch (hotkey) {
- case 0x3b: break; // Fn+F1
- case 0x3c: break; // Fn+F2
- case 0x3d: break; // Fn+F3
- case 0x3e: break; // Fn+F4
- case 0x3f: break; // Fn+F5
- case 0x40: // Fn+F6 (Decrease Display Brightness)
- reg8 = ec_read(0x17);
- reg8 = (reg8 > 8) ? (reg8 - 8) : 0;
- ec_write(0x17, reg8);
- return;
- case 0x41: // Fn+F7 (Increase Display Brightness)
- reg8 = ec_read(0x17);
- reg8 += 8;
- reg8 = (reg8 >= MAX_LCD_BRIGHTNESS) ? MAX_LCD_BRIGHTNESS : reg8;
- ec_write(0x17, reg8);
- return;
- case 0x42: break; // Fn+F8
- case 0x43: break; // Fn+F9
- case 0x44: break; // Fn+F10
- case 0x57: break; // Fn+F11
- case 0x58: break; // Fn+F12
+ case 0x3b: // Fn+F1
+ break;
+ case 0x3c: // Fn+F2
+ break;
+ case 0x3d: // Fn+F3
+ break;
+ case 0x3e: // Fn+F4
+ break;
+ case 0x3f: // Fn+F5
+ break;
+ case 0x40: // Fn+F6 (Decrease Display Brightness)
+ reg8 = ec_read(0x17);
+ reg8 = (reg8 > 8) ? (reg8 - 8) : 0;
+ ec_write(0x17, reg8);
+ return;
+ case 0x41: // Fn+F7 (Increase Display Brightness)
+ reg8 = ec_read(0x17);
+ reg8 += 8;
+ reg8 = (reg8 >= MAX_LCD_BRIGHTNESS) ? MAX_LCD_BRIGHTNESS : reg8;
+ ec_write(0x17, reg8);
+ return;
+ case 0x42: // Fn+F8
+ break;
+ case 0x43: // Fn+F9
+ break;
+ case 0x44: // Fn+F10
+ break;
+ case 0x57: // Fn+F11
+ break;
+ case 0x58: // Fn+F12
+ break;
}
printk(BIOS_DEBUG, "EC hotkey: %02x\n", hotkey);
}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ib34af7c4db359e132b968fe8409580af05fba9e3
Gerrit-Change-Number: 31652
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-MessageType: newchange
4
10
Change in coreboot[master]: mb/asus/p2b: Migrate southbridge ACPI stuff
by Keith Hui (Code Review) 22 Mar '21
by Keith Hui (Code Review) 22 Mar '21
22 Mar '21
Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41050 )
Change subject: mb/asus/p2b: Migrate southbridge ACPI stuff
......................................................................
mb/asus/p2b: Migrate southbridge ACPI stuff
Move (remaining) ACPI stuff for both southbridge main and PM functions
into one file under sb/intel/i82371eb, that is simply included from the
board's \_SB scope.
Also, southbridge no longer claims I/O ports 0x2e-0x2f, following the
p3b-f OEM scheme, and its PM device now reports its own I/O resources.
Change-Id: Ibed49a800dec19534761e5ab22a6cbb1e6bd4a5d
Signed-off-by: Keith Hui <buurin(a)gmail.com>
---
M src/mainboard/asus/p2b/dsdt.asl
M src/southbridge/intel/i82371eb/acpi/i82371eb.asl
2 files changed, 85 insertions(+), 76 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/41050/1
diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl
index c3a279d..b998ceb 100644
--- a/src/mainboard/asus/p2b/dsdt.asl
+++ b/src/mainboard/asus/p2b/dsdt.asl
@@ -159,79 +159,7 @@
#include <northbridge/intel/i440bx/acpi/sb_pci0_crs.asl>
#include <southbridge/intel/i82371eb/acpi/isabridge.asl>
- /* Begin southbridge block */
- Device (PX40)
- {
- Name(_ADR, 0x00040000)
- OperationRegion (PIRQ, PCI_Config, 0x60, 0x04)
- Field (PIRQ, ByteAcc, NoLock, Preserve)
- {
- PIRA, 8,
- PIRB, 8,
- PIRC, 8,
- PIRD, 8
- }
-
- /* PNP Motherboard Resources */
- Device (SYSR)
- {
- Name (_HID, EisaId ("PNP0C02"))
- Name (_UID, 0x02)
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF1, ResourceTemplate ()
- {
- /* PM register ports */
- IO (Decode16, 0x0000, 0x0000, 0x01, 0x40, _Y06)
- /* SMBus register ports */
- IO (Decode16, 0x0000, 0x0000, 0x01, 0x10, _Y07)
- /* PIIX4E ports */
- /* Aliased DMA ports */
- IO (Decode16, 0x0010, 0x0010, 0x01, 0x10, )
- /* Aliased PIC ports */
- IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E, )
- /* Aliased timer ports */
- IO (Decode16, 0x0050, 0x0050, 0x01, 0x04, )
- IO (Decode16, 0x0062, 0x0062, 0x01, 0x02, )
- IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B, )
- IO (Decode16, 0x0074, 0x0074, 0x01, 0x0C, )
- IO (Decode16, 0x0091, 0x0091, 0x01, 0x03, )
- IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E, )
- IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10, )
- IO (Decode16, 0x0294, 0x0294, 0x01, 0x04, )
- IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x02, )
- IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02, )
- })
- CreateWordField (BUF1, _Y06._MIN, PMLO)
- CreateWordField (BUF1, _Y06._MAX, PMRL)
- CreateWordField (BUF1, _Y07._MIN, SBLO)
- CreateWordField (BUF1, _Y07._MAX, SBRL)
-
- And (\_SB.PCI0.PX43.PM00, 0xFFFE, PMLO)
- And (\_SB.PCI0.PX43.SB00, 0xFFFE, SBLO)
- Store (PMLO, PMRL)
- Store (SBLO, SBRL)
- Return (BUF1)
- }
- }
- #include <southbridge/intel/i82371eb/acpi/i82371eb.asl>
- }
- Device (PX43)
- {
- Name (_ADR, 0x00040003) // _ADR: Address
- OperationRegion (IPMU, PCI_Config, PMBA, 0x02)
- Field (IPMU, ByteAcc, NoLock, Preserve)
- {
- PM00, 16
- }
-
- OperationRegion (ISMB, PCI_Config, SMBBA, 0x02)
- Field (ISMB, ByteAcc, NoLock, Preserve)
- {
- SB00, 16
- }
- }
-
+ #include <southbridge/intel/i82371eb/acpi/i82371eb.asl>
#include <superio/winbond/w83977tf/acpi/superio.asl>
}
}
diff --git a/src/southbridge/intel/i82371eb/acpi/i82371eb.asl b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl
index 57f347e..1e2818c 100644
--- a/src/southbridge/intel/i82371eb/acpi/i82371eb.asl
+++ b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl
@@ -1,17 +1,60 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */
-/*
- * Declares assorted devices that falls under this southbridge.
- */
#include "southbridge/intel/i82371eb/i82371eb.h"
+/* Declares assorted devices that falls under this southbridge. */
+Device (PX40)
+{
+ Name(_ADR, 0x00040000)
+ OperationRegion (PIRQ, PCI_Config, 0x60, 0x04)
+ Field (PIRQ, ByteAcc, NoLock, Preserve)
+ {
+ PIRA, 8,
+ PIRB, 8,
+ PIRC, 8,
+ PIRD, 8
+ }
+
OperationRegion (S1XX, PCI_Config, 0xB2, 0x01)
Field (S1XX, ByteAcc, NoLock, Preserve)
{
FXS1, 8
}
+ /* PNP Motherboard Resources */
+ Device (SYSR)
+ {
+ Name (_HID, EisaId ("PNP0C02"))
+ Name (_UID, 0x02)
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF1, ResourceTemplate ()
+ {
+ /* PIIX4E ports */
+ /* Aliased DMA ports */
+ IO (Decode16, 0x0010, 0x0010, 0x01, 0x10, )
+ /* Aliased PIC ports */
+ /* Do not claim 0x2e-0x2f, per P3B-F vendor DSDT */
+ IO (Decode16, 0x0022, 0x0022, 0x01, 0x0C, )
+ IO (Decode16, 0x0030, 0x0030, 0x01, 0x10, )
+ /* Aliased timer ports */
+ /* Existing DSDT only reserves to 0x54 */
+ IO (Decode16, 0x0044, 0x0044, 0x01, 0x10, )
+ IO (Decode16, 0x0062, 0x0062, 0x01, 0x02, )
+ IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B, )
+ IO (Decode16, 0x0074, 0x0074, 0x01, 0x0C, )
+ IO (Decode16, 0x0091, 0x0091, 0x01, 0x03, )
+ IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E, )
+ IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10, )
+ IO (Decode16, 0x0294, 0x0294, 0x01, 0x04, )
+ /* W83977TF/EF Super I/O config ports */
+ IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x02, )
+ IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02, )
+ })
+ Return (BUF1)
+ }
+ }
/* 8259-compatible Programmable Interrupt Controller */
Device (PIC)
{
@@ -79,3 +122,41 @@
IRQNoFlags () {13}
})
}
+}
+
+/* Power management functions allows ACPI reporting of PM and SMBus base ports. */
+Device (PX43)
+{
+ Name (_ADR, 0x00040003) // _ADR: Address
+ OperationRegion (IPMU, PCI_Config, PMBA, 0x02)
+ Field (IPMU, ByteAcc, NoLock, Preserve)
+ {
+ PM00, 16,
+ }
+
+ OperationRegion (ISMB, PCI_Config, SMBBA, 0x02)
+ Field (ISMB, ByteAcc, NoLock, Preserve)
+ {
+ SB00, 16,
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF1, ResourceTemplate ()
+ {
+ /* PM register ports */
+ IO (Decode16, 0x0000, 0x0000, 0x01, 0x40, _Y06)
+ /* SMBus register ports */
+ IO (Decode16, 0x0000, 0x0000, 0x01, 0x10, _Y07)
+ })
+ CreateWordField (BUF1, _Y06._MIN, PMLO)
+ CreateWordField (BUF1, _Y06._MAX, PMRL)
+ CreateWordField (BUF1, _Y07._MIN, SBLO)
+ CreateWordField (BUF1, _Y07._MAX, SBRL)
+
+ And (PM00, 0xFFFE, PMLO)
+ And (SB00, 0xFFFE, SBLO)
+ Store (PMLO, PMRL)
+ Store (SBLO, SBRL)
+ Return (BUF1)
+ }
+}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ibed49a800dec19534761e5ab22a6cbb1e6bd4a5d
Gerrit-Change-Number: 41050
Gerrit-PatchSet: 1
Gerrit-Owner: Keith Hui <buurin(a)gmail.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newchange
4
15
Change in coreboot[master]: [WIP] AGESA,binaryPI boards: Drop invalid MP table files
by Kyösti Mälkki (Code Review) 16 Mar '21
by Kyösti Mälkki (Code Review) 16 Mar '21
16 Mar '21
Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38313 )
Change subject: [WIP] AGESA,binaryPI boards: Drop invalid MP table files
......................................................................
[WIP] AGESA,binaryPI boards: Drop invalid MP table files
If we spot any error in the file, treat it as untested and
broken copy-paste.
Change-Id: Idd13b8b006fce7383f3f73c3c0a5d51a71c0155b
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/mainboard/amd/bettong/Kconfig
D src/mainboard/amd/bettong/mptable.c
M src/mainboard/amd/db-ft3b-lc/Kconfig
D src/mainboard/amd/db-ft3b-lc/mptable.c
M src/mainboard/amd/gardenia/Kconfig
D src/mainboard/amd/gardenia/mptable.c
M src/mainboard/amd/inagua/Kconfig
D src/mainboard/amd/inagua/mptable.c
M src/mainboard/amd/lamar/Kconfig
D src/mainboard/amd/lamar/mptable.c
M src/mainboard/amd/olivehill/Kconfig
D src/mainboard/amd/olivehill/mptable.c
M src/mainboard/amd/olivehillplus/Kconfig
D src/mainboard/amd/olivehillplus/mptable.c
M src/mainboard/amd/parmer/Kconfig
D src/mainboard/amd/parmer/mptable.c
M src/mainboard/amd/persimmon/Kconfig
D src/mainboard/amd/persimmon/mptable.c
M src/mainboard/amd/south_station/Kconfig
D src/mainboard/amd/south_station/mptable.c
M src/mainboard/amd/thatcher/Kconfig
D src/mainboard/amd/thatcher/mptable.c
M src/mainboard/amd/union_station/Kconfig
D src/mainboard/amd/union_station/mptable.c
M src/mainboard/asrock/e350m1/Kconfig
D src/mainboard/asrock/e350m1/mptable.c
M src/mainboard/asrock/imb-a180/Kconfig
D src/mainboard/asrock/imb-a180/mptable.c
M src/mainboard/asus/am1i-a/Kconfig
D src/mainboard/asus/am1i-a/mptable.c
M src/mainboard/asus/f2a85-m/Kconfig
D src/mainboard/asus/f2a85-m/mptable.c
M src/mainboard/bap/ode_e20XX/Kconfig
D src/mainboard/bap/ode_e20XX/mptable.c
M src/mainboard/bap/ode_e21XX/Kconfig
D src/mainboard/bap/ode_e21XX/mptable.c
M src/mainboard/biostar/a68n_5200/Kconfig
D src/mainboard/biostar/a68n_5200/mptable.c
M src/mainboard/biostar/am1ml/Kconfig
D src/mainboard/biostar/am1ml/mptable.c
M src/mainboard/elmex/pcm205400/Kconfig
D src/mainboard/elmex/pcm205400/mptable.c
M src/mainboard/gizmosphere/gizmo/Kconfig
D src/mainboard/gizmosphere/gizmo/mptable.c
M src/mainboard/gizmosphere/gizmo2/Kconfig
D src/mainboard/gizmosphere/gizmo2/mptable.c
D src/mainboard/google/kahlee/mptable.c
M src/mainboard/hp/abm/Kconfig
D src/mainboard/hp/abm/mptable.c
M src/mainboard/hp/pavilion_m6_1035dx/Kconfig
D src/mainboard/hp/pavilion_m6_1035dx/mptable.c
M src/mainboard/jetway/nf81-t56n-lf/Kconfig
D src/mainboard/jetway/nf81-t56n-lf/mptable.c
M src/mainboard/lenovo/g505s/Kconfig
D src/mainboard/lenovo/g505s/mptable.c
M src/mainboard/lippert/frontrunner-af/Kconfig
D src/mainboard/lippert/frontrunner-af/mptable.c
M src/mainboard/lippert/toucan-af/Kconfig
D src/mainboard/lippert/toucan-af/mptable.c
M src/mainboard/msi/ms7721/Kconfig
D src/mainboard/msi/ms7721/mptable.c
M src/mainboard/pcengines/apu1/Kconfig
D src/mainboard/pcengines/apu1/mptable.c
M src/mainboard/pcengines/apu2/Kconfig
D src/mainboard/pcengines/apu2/mptable.c
65 files changed, 0 insertions(+), 4,840 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/38313/1
diff --git a/src/mainboard/amd/bettong/Kconfig b/src/mainboard/amd/bettong/Kconfig
index 4617360..50140f7 100644
--- a/src/mainboard/amd/bettong/Kconfig
+++ b/src/mainboard/amd/bettong/Kconfig
@@ -28,7 +28,6 @@
select DEFAULT_POST_ON_LPC
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_8192
select GFXUMA
diff --git a/src/mainboard/amd/bettong/mptable.c b/src/mainboard/amd/bettong/mptable.c
deleted file mode 100644
index d9632d5..0000000
--- a/src/mainboard/amd/bettong/mptable.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/pi/hudson/hudson.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/amd/db-ft3b-lc/Kconfig b/src/mainboard/amd/db-ft3b-lc/Kconfig
index f17d2d3..7f24015 100644
--- a/src/mainboard/amd/db-ft3b-lc/Kconfig
+++ b/src/mainboard/amd/db-ft3b-lc/Kconfig
@@ -29,7 +29,6 @@
select DEFAULT_POST_ON_LPC
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_8192
select GFXUMA
diff --git a/src/mainboard/amd/db-ft3b-lc/mptable.c b/src/mainboard/amd/db-ft3b-lc/mptable.c
deleted file mode 100644
index 40a75ad..0000000
--- a/src/mainboard/amd/db-ft3b-lc/mptable.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /* Initialize the MP_Table */
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- /*
- * Type 0: Processor Entries:
- * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
- * CPU Signature (Stepping, Model, Family),
- * Feature Flags
- */
- smp_write_processors(mc);
-
- /*
- * Type 1: Bus Entries:
- * Bus ID, Bus Type
- */
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /*
- * Type 2: I/O APICs:
- * APIC ID, Version, APIC Flags:EN, Address
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- /*
- * Type 3: I/O Interrupt Table Entries:
- * Int Type, Int Polarity, Int Level, Source Bus ID,
- * Source Bus IRQ, Dest APIC ID, Dest PIN#
- */
-
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
-
- /* SMBUS / ACPI */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
-
- /* Southbridge HD Audio */
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[PIRQ_EHCI1]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[PIRQ_EHCI2]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[PIRQ_EHCI3]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]);
-
- /* SATA */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
-
- /* on board NIC & Slot PCIE */
- PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]);
- PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]);
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_D]);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_A]);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_B]);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_C]);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_D]);
-
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
-
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/amd/gardenia/Kconfig b/src/mainboard/amd/gardenia/Kconfig
index e97a3ba..424a47d 100644
--- a/src/mainboard/amd/gardenia/Kconfig
+++ b/src/mainboard/amd/gardenia/Kconfig
@@ -21,7 +21,6 @@
select AMD_APU_STONEYRIDGE
select AMD_APU_PKG_FP4
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_8192
select GFXUMA
diff --git a/src/mainboard/amd/gardenia/mptable.c b/src/mainboard/amd/gardenia/mptable.c
deleted file mode 100644
index 5bb70e9..0000000
--- a/src/mainboard/amd/gardenia/mptable.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <soc/southbridge.h>
-#include <amdblocks/amd_pci_util.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- //mptable_write_buses(mc, NULL, &bus_isa);
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), \
- MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, \
- (intr), (apicid), (pin))
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, \
- MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), \
- (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig
index a5ba07e..77f6b8a 100644
--- a/src/mainboard/amd/inagua/Kconfig
+++ b/src/mainboard/amd/inagua/Kconfig
@@ -27,7 +27,6 @@
select SUPERIO_SMSC_KBC1100
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_2048
select GFXUMA
diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c
deleted file mode 100644
index b8bd0b3..0000000
--- a/src/mainboard/amd/inagua/mptable.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device*/
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
- /* Southbridge HD Audio: */
- PCI_INT(0x0, 0x14, 0x2, 0x12);
-
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/amd/lamar/Kconfig b/src/mainboard/amd/lamar/Kconfig
index c856534..2e19c3d 100644
--- a/src/mainboard/amd/lamar/Kconfig
+++ b/src/mainboard/amd/lamar/Kconfig
@@ -29,7 +29,6 @@
select SUPERIO_FINTEK_F81216H
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_8192
select GFXUMA
diff --git a/src/mainboard/amd/lamar/mptable.c b/src/mainboard/amd/lamar/mptable.c
deleted file mode 100644
index 1f2093d..0000000
--- a/src/mainboard/amd/lamar/mptable.c
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <drivers/generic/ioapic/chip.h>
-#include <southbridge/amd/pi/hudson/amd_pci_int_defs.h>
-#include <northbridge/amd/pi/00630F01/pci_devs.h>
-
-#define NB_APIC_ADDR ((u8 *)0xFEC20000)
-
-#define PCI_INT(bus, dev, fn, apic, pin) \
- if (((pin) != 0x00) && ((pin) != 0x1F)) \
- { \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apic, (pin)); \
- }
-
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /* Initialize the MP_Table */
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- /*
- * Type 0: Processor Entries:
- * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
- * CPU Signature (Stepping, Model, Family),
- * Feature Flags
- */
- smp_write_processors(mc);
-
- /*
- * Type 1: Bus Entries:
- * Bus ID, Bus Type
- */
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /*
- * Type 2: I/O APICs:
- * APIC ID, Version, APIC Flags:EN, Address
- */
-
- u8 apicid_nb = (io_apic_read(NB_APIC_ADDR, 0x00) >> 24); /* Get the GNB IOAPIC ID */
- u8 apicver_nb = (io_apic_read(NB_APIC_ADDR, 0x01) & 0xFF); /* Get the GNB IOAPIC version */
-
- smp_write_ioapic(mc, apicid_nb, apicver_nb, NB_APIC_ADDR);
-
- u8 apicid_sb = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); /* Get the southbridge IOAPIC ID */
- u8 apicver_sb = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); /* Get the southbridge IOAPIC version */
-
- smp_write_ioapic(mc, apicid_sb, apicver_sb, VIO_APIC_VADDR);
-
- /*
- * Type 3: I/O Interrupt Table Entries:
- * Int Type, Int Polarity, Int Level, Source Bus ID,
- * Source Bus IRQ, Dest APIC ID, Dest PIN#
- */
- mptable_add_isa_interrupts(mc, bus_isa, apicid_nb, 0);
- mptable_add_isa_interrupts(mc, bus_isa, apicid_sb, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-
- /* APU Internal Graphic Device */
- PCI_INT(0x0, 0x01, 0x0, apicid_nb, intr_data_ptr[PIRQ_GFX]);
- PCI_INT(0x0, 0x01, 0x1, apicid_nb, intr_data_ptr[PIRQ_ACTL]);
-
- /* SMBUS / ACPI */
- PCI_INT(0x0, 0x14, 0x0, apicid_sb, intr_data_ptr[PIRQ_SMBUS]);
-
- /* Southbridge HD Audio */
- PCI_INT(0x0, 0x14, 0x2, apicid_sb, intr_data_ptr[PIRQ_HDA]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, apicid_sb, intr_data_ptr[PIRQ_OHCI1]);
- PCI_INT(0x0, 0x12, 0x2, apicid_sb, intr_data_ptr[PIRQ_EHCI1]);
- PCI_INT(0x0, 0x13, 0x0, apicid_sb, intr_data_ptr[PIRQ_OHCI2]);
- PCI_INT(0x0, 0x13, 0x2, apicid_sb, intr_data_ptr[PIRQ_EHCI2]);
- PCI_INT(0x0, 0x16, 0x0, apicid_sb, intr_data_ptr[PIRQ_OHCI3]);
- PCI_INT(0x0, 0x16, 0x2, apicid_sb, intr_data_ptr[PIRQ_EHCI3]);
- PCI_INT(0x0, 0x14, 0x5, apicid_sb, intr_data_ptr[PIRQ_OHCI4]);
-
- /* SATA */
- PCI_INT(0x0, 0x11, 0x0, apicid_sb, intr_data_ptr[PIRQ_SATA]);
-
- /* IDE */
- PCI_INT(0x0, 0x14, 0x1, apicid_sb, intr_data_ptr[PIRQ_IDE]);
-
- /* PCI slots */
- /* NB Gfx PCIe Bridges */
- PCI_INT(0, 0x2, 0x1, apicid_nb, intr_data_ptr[PIRQ_A]);
- PCI_INT(0, 0x2, 0x2, apicid_nb, intr_data_ptr[PIRQ_A]);
-
- /* NB GPP PCIe Bridges */
- PCI_INT(0, 0x3, 0x1, apicid_nb, intr_data_ptr[PIRQ_A]);
- PCI_INT(0, 0x3, 0x2, apicid_nb, intr_data_ptr[PIRQ_A]);
- PCI_INT(0, 0x3, 0x3, apicid_nb, intr_data_ptr[PIRQ_A]);
- PCI_INT(0, 0x3, 0x4, apicid_nb, intr_data_ptr[PIRQ_A]);
- PCI_INT(0, 0x3, 0x5, apicid_nb, intr_data_ptr[PIRQ_A]);
-
- /* PCI slots */
- PCI_INT(0, 0x14, 0x4, apicid_sb, intr_data_ptr[PIRQ_A]);
-
- /* FCH GPP PCIe Bridges */
- PCI_INT(0x0, 0x15, 0x0, apicid_sb, intr_data_ptr[PIRQ_A]);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, apicid_sb, intr_data_ptr[PIRQ_A]);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, apicid_sb, intr_data_ptr[PIRQ_A]);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, apicid_sb, intr_data_ptr[PIRQ_A]);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
-
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/amd/olivehill/Kconfig b/src/mainboard/amd/olivehill/Kconfig
index 78f768f..8810c1d 100644
--- a/src/mainboard/amd/olivehill/Kconfig
+++ b/src/mainboard/amd/olivehill/Kconfig
@@ -27,7 +27,6 @@
select DEFAULT_POST_ON_LPC
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096
diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c
deleted file mode 100644
index 7082013..0000000
--- a/src/mainboard/amd/olivehill/mptable.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <southbridge/amd/agesa/hudson/hudson.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- //mptable_write_buses(mc, NULL, &bus_isa);
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/amd/olivehillplus/Kconfig b/src/mainboard/amd/olivehillplus/Kconfig
index 907de3b..1745969 100644
--- a/src/mainboard/amd/olivehillplus/Kconfig
+++ b/src/mainboard/amd/olivehillplus/Kconfig
@@ -28,7 +28,6 @@
select DEFAULT_POST_ON_LPC
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_8192
select GFXUMA
diff --git a/src/mainboard/amd/olivehillplus/mptable.c b/src/mainboard/amd/olivehillplus/mptable.c
deleted file mode 100644
index 0f6ca81..0000000
--- a/src/mainboard/amd/olivehillplus/mptable.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/pi/hudson/hudson.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- //mptable_write_buses(mc, NULL, &bus_isa);
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/amd/parmer/Kconfig b/src/mainboard/amd/parmer/Kconfig
index ae024dd..94f55ce 100644
--- a/src/mainboard/amd/parmer/Kconfig
+++ b/src/mainboard/amd/parmer/Kconfig
@@ -27,7 +27,6 @@
select DEFAULT_POST_ON_LPC
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096
diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c
deleted file mode 100644
index 3a5540c..0000000
--- a/src/mainboard/amd/parmer/mptable.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <southbridge/amd/agesa/hudson/hudson.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- //mptable_write_buses(mc, NULL, &bus_isa);
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig
index f243f0f..248e4d4 100644
--- a/src/mainboard/amd/persimmon/Kconfig
+++ b/src/mainboard/amd/persimmon/Kconfig
@@ -27,7 +27,6 @@
select SUPERIO_FINTEK_F81865F
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096
diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c
deleted file mode 100644
index bc7a3ac..0000000
--- a/src/mainboard/amd/persimmon/mptable.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <stdint.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <drivers/generic/ioapic/chip.h>
-#include <arch/ioapic.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- /* Initialize the MP_Table */
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- /*
- * Type 0: Processor Entries:
- * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
- * CPU Signature (Stepping, Model, Family),
- * Feature Flags
- */
- smp_write_processors(mc);
-
- /*
- * Type 1: Bus Entries:
- * Bus ID, Bus Type
- */
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /*
- * Type 2: I/O APICs:
- * APIC ID, Version, APIC Flags:EN, Address
- */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /*
- * Type 3: I/O Interrupt Table Entries:
- * Int Type, Int Polarity, Int Level, Source Bus ID,
- * Source Bus IRQ, Dest APIC ID, Dest PIN#
- */
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
-
- /* SMBUS / ACPI */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
-
- /* Southbridge HD Audio */
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
-
- /* LPC */
- PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
- PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
- PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
- PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]);
-
- /* IDE */
- PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]);
-
- /* SATA */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
-
- /* on board NIC & Slot PCIE */
- PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
- PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0 */
- PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
- PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
- PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
- PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
- }
-
- /* PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
- /* PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
- /* PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
- /* PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/amd/south_station/Kconfig b/src/mainboard/amd/south_station/Kconfig
index 42841cb..0d76d50 100644
--- a/src/mainboard/amd/south_station/Kconfig
+++ b/src/mainboard/amd/south_station/Kconfig
@@ -27,7 +27,6 @@
select SUPERIO_FINTEK_F81865F
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096
select GFXUMA
diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c
deleted file mode 100644
index b8bd0b3..0000000
--- a/src/mainboard/amd/south_station/mptable.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device*/
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
- /* Southbridge HD Audio: */
- PCI_INT(0x0, 0x14, 0x2, 0x12);
-
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/amd/thatcher/Kconfig b/src/mainboard/amd/thatcher/Kconfig
index e556592..b79511f 100644
--- a/src/mainboard/amd/thatcher/Kconfig
+++ b/src/mainboard/amd/thatcher/Kconfig
@@ -27,7 +27,6 @@
select DEFAULT_POST_ON_LPC
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select SUPERIO_SMSC_LPC47N217
diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c
deleted file mode 100644
index 05d222a..0000000
--- a/src/mainboard/amd/thatcher/mptable.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <southbridge/amd/agesa/hudson/hudson.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
- u8 byte;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- //mptable_write_buses(mc, NULL, &bus_isa);
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/amd/union_station/Kconfig b/src/mainboard/amd/union_station/Kconfig
index 1532d34..2dc82c9 100644
--- a/src/mainboard/amd/union_station/Kconfig
+++ b/src/mainboard/amd/union_station/Kconfig
@@ -26,7 +26,6 @@
select SOUTHBRIDGE_AMD_CIMX_SB800
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_2048
select GFXUMA
diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c
deleted file mode 100644
index b8bd0b3..0000000
--- a/src/mainboard/amd/union_station/mptable.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device*/
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
- /* Southbridge HD Audio: */
- PCI_INT(0x0, 0x14, 0x2, 0x12);
-
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig
index 3bbc2a5..18058c9 100644
--- a/src/mainboard/asrock/e350m1/Kconfig
+++ b/src/mainboard/asrock/e350m1/Kconfig
@@ -24,7 +24,6 @@
select SB_SUPERIO_HWM
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096
diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c
deleted file mode 100644
index ce8cfa0..0000000
--- a/src/mainboard/asrock/e350m1/mptable.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-
-#include <arch/ioapic.h>
-#include <arch/smp/mpspec.h>
-#include <stdint.h>
-#include <string.h>
-
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "ASROCK ", 8);
-
- smp_write_processors(mc);
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device*/
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
- /* Southbridge HD Audio: */
- PCI_INT(0x0, 0x14, 0x2, 0x12);
-
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/asrock/imb-a180/Kconfig b/src/mainboard/asrock/imb-a180/Kconfig
index 8fca61c..7110c89 100644
--- a/src/mainboard/asrock/imb-a180/Kconfig
+++ b/src/mainboard/asrock/imb-a180/Kconfig
@@ -24,7 +24,6 @@
select SUPERIO_WINBOND_W83627UHG
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096
diff --git a/src/mainboard/asrock/imb-a180/mptable.c b/src/mainboard/asrock/imb-a180/mptable.c
deleted file mode 100644
index 7082013..0000000
--- a/src/mainboard/asrock/imb-a180/mptable.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <southbridge/amd/agesa/hudson/hudson.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- //mptable_write_buses(mc, NULL, &bus_isa);
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/asus/am1i-a/Kconfig b/src/mainboard/asus/am1i-a/Kconfig
index a0dae9f..8a7e7e9 100644
--- a/src/mainboard/asus/am1i-a/Kconfig
+++ b/src/mainboard/asus/am1i-a/Kconfig
@@ -10,7 +10,6 @@
select USE_OPTION_TABLE
select HAVE_CMOS_DEFAULT
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
diff --git a/src/mainboard/asus/am1i-a/mptable.c b/src/mainboard/asus/am1i-a/mptable.c
deleted file mode 100644
index 9efcab3..0000000
--- a/src/mainboard/asus/am1i-a/mptable.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * Copyright (C) 2018 Gergely Kiss <mail.gery(a)gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <drivers/generic/ioapic/chip.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- /* Initialize the MP_Table */
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- /*
- * Type 0: Processor Entries:
- * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
- * CPU Signature (Stepping, Model, Family),
- * Feature Flags
- */
- smp_write_processors(mc);
-
- /*
- * Type 1: Bus Entries:
- * Bus ID, Bus Type
- */
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /*
- * Type 2: I/O APICs:
- * APIC ID, Version, APIC Flags:EN, Address
- */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /*
- * Type 3: I/O Interrupt Table Entries:
- * Int Type, Int Polarity, Int Level, Source Bus ID,
- * Source Bus IRQ, Dest APIC ID, Dest PIN#
- */
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_A]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_B]);
-
- /* GPP Ports */
- PCI_INT(0x0, 0x02, 0x0, intr_data_ptr[PIRQ_A]);
- PCI_INT(0x0, 0x02, 0x1, intr_data_ptr[PIRQ_B]);
- PCI_INT(0x0, 0x02, 0x2, intr_data_ptr[PIRQ_C]);
- PCI_INT(0x0, 0x02, 0x3, intr_data_ptr[PIRQ_D]);
-
- /* SATA */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
-
- /* USB */
- PCI_INT(0x0, 0x10, 0x0, intr_data_ptr[PIRQ_C]); /* XHCI */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[PIRQ_EHCI1]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[PIRQ_EHCI2]);
-
- /* Southbridge HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_HDA]);
-
- /* PCIe slot & Onboard NIC */
- PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_A]);
- PCI_INT(0x1, 0x0, 0x1, intr_data_ptr[PIRQ_B]);
- PCI_INT(0x1, 0x0, 0x2, intr_data_ptr[PIRQ_C]);
- PCI_INT(0x1, 0x0, 0x3, intr_data_ptr[PIRQ_D]);
- PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_B]);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/asus/f2a85-m/Kconfig b/src/mainboard/asus/f2a85-m/Kconfig
index c1dd063..5d5adb4 100644
--- a/src/mainboard/asus/f2a85-m/Kconfig
+++ b/src/mainboard/asus/f2a85-m/Kconfig
@@ -23,7 +23,6 @@
select SOUTHBRIDGE_AMD_AGESA_HUDSON
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select SUPERIO_ITE_IT8728F if BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_LE
diff --git a/src/mainboard/asus/f2a85-m/mptable.c b/src/mainboard/asus/f2a85-m/mptable.c
deleted file mode 100644
index b5b0433..0000000
--- a/src/mainboard/asus/f2a85-m/mptable.c
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/ioapic.h>
-#include <arch/smp/mpspec.h>
-#include <cpu/x86/lapic.h>
-#include <stdint.h>
-#include <string.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <southbridge/amd/agesa/hudson/hudson.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
- u8 byte;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- //mptable_write_buses(mc, NULL, &bus_isa);
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* IOMMU */
- PCI_INT(0x0, 0x0, 0x0, 0x10);
- PCI_INT(0x0, 0x0, 0x1, 0x11);
- PCI_INT(0x0, 0x0, 0x2, 0x12);
- PCI_INT(0x0, 0x0, 0x3, 0x13);
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/bap/ode_e20XX/Kconfig b/src/mainboard/bap/ode_e20XX/Kconfig
index 2a72deb..6d417ed 100644
--- a/src/mainboard/bap/ode_e20XX/Kconfig
+++ b/src/mainboard/bap/ode_e20XX/Kconfig
@@ -28,7 +28,6 @@
select DEFAULT_POST_ON_LPC
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096
select GFXUMA
diff --git a/src/mainboard/bap/ode_e20XX/mptable.c b/src/mainboard/bap/ode_e20XX/mptable.c
deleted file mode 100644
index e4edc5f..0000000
--- a/src/mainboard/bap/ode_e20XX/mptable.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <drivers/generic/ioapic/chip.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- /* Initialize the MP_Table */
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- /*
- * Type 0: Processor Entries:
- * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
- * CPU Signature (Stepping, Model, Family),
- * Feature Flags
- */
- smp_write_processors(mc);
-
- /*
- * Type 1: Bus Entries:
- * Bus ID, Bus Type
- */
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /*
- * Type 2: I/O APICs:
- * APIC ID, Version, APIC Flags:EN, Address
- */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /*
- * Type 3: I/O Interrupt Table Entries:
- * Int Type, Int Polarity, Int Level, Source Bus ID,
- * Source Bus IRQ, Dest APIC ID, Dest PIN#
- */
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
-
- /* SMBUS / ACPI */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
-
- /* Southbridge HD Audio */
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
-
- /* LPC */
- PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
- PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
- PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]);
- PCI_INT(0x0, 0x16, 0x2, intr_data_ptr[PIRQ_EHCI3]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]);
-
- /* SATA */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
-
- /* on board NIC & Slot PCIE */
- PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]);
- PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]);
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0 */
- PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]);
- PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]);
- PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]);
- PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]);
-
- /* PCI_SLOT 1 */
- PCI_INT(bus_pci, 0x6, 0x0, intr_data_ptr[PIRQ_F]);
- PCI_INT(bus_pci, 0x6, 0x1, intr_data_ptr[PIRQ_G]);
- PCI_INT(bus_pci, 0x6, 0x2, intr_data_ptr[PIRQ_H]);
- PCI_INT(bus_pci, 0x6, 0x3, intr_data_ptr[PIRQ_E]);
-
- /* PCI_SLOT 2 */
- PCI_INT(bus_pci, 0x7, 0x0, intr_data_ptr[PIRQ_G]);
- PCI_INT(bus_pci, 0x7, 0x1, intr_data_ptr[PIRQ_H]);
- PCI_INT(bus_pci, 0x7, 0x2, intr_data_ptr[PIRQ_E]);
- PCI_INT(bus_pci, 0x7, 0x3, intr_data_ptr[PIRQ_F]);
-
- PCI_INT(bus_pci, 0x0, 0x0, intr_data_ptr[PIRQ_C]);
- PCI_INT(bus_pci, 0x0, 0x1, intr_data_ptr[PIRQ_D]);
- PCI_INT(bus_pci, 0x0, 0x2, intr_data_ptr[PIRQ_E]);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_D]);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_A]);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_B]);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_C]);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_D]);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/bap/ode_e21XX/Kconfig b/src/mainboard/bap/ode_e21XX/Kconfig
index ff71d5b..c1b78c8 100644
--- a/src/mainboard/bap/ode_e21XX/Kconfig
+++ b/src/mainboard/bap/ode_e21XX/Kconfig
@@ -28,7 +28,6 @@
select DEFAULT_POST_ON_LPC
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_8192
select GFXUMA
diff --git a/src/mainboard/bap/ode_e21XX/mptable.c b/src/mainboard/bap/ode_e21XX/mptable.c
deleted file mode 100644
index 0f6ca81..0000000
--- a/src/mainboard/bap/ode_e21XX/mptable.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/pi/hudson/hudson.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- //mptable_write_buses(mc, NULL, &bus_isa);
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/biostar/a68n_5200/Kconfig b/src/mainboard/biostar/a68n_5200/Kconfig
index f608513..c8d8884 100644
--- a/src/mainboard/biostar/a68n_5200/Kconfig
+++ b/src/mainboard/biostar/a68n_5200/Kconfig
@@ -29,7 +29,6 @@
select SUPERIO_ITE_IT8728F
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096
select GFXUMA
diff --git a/src/mainboard/biostar/a68n_5200/mptable.c b/src/mainboard/biostar/a68n_5200/mptable.c
deleted file mode 100644
index 7082013..0000000
--- a/src/mainboard/biostar/a68n_5200/mptable.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <southbridge/amd/agesa/hudson/hudson.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- //mptable_write_buses(mc, NULL, &bus_isa);
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/biostar/am1ml/Kconfig b/src/mainboard/biostar/am1ml/Kconfig
index 9eaa6fb..c9960e3 100644
--- a/src/mainboard/biostar/am1ml/Kconfig
+++ b/src/mainboard/biostar/am1ml/Kconfig
@@ -24,7 +24,6 @@
select GFXUMA
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
diff --git a/src/mainboard/biostar/am1ml/mptable.c b/src/mainboard/biostar/am1ml/mptable.c
deleted file mode 100644
index 659a141..0000000
--- a/src/mainboard/biostar/am1ml/mptable.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <drivers/generic/ioapic/chip.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- /* Initialize the MP_Table */
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- /*
- * Type 0: Processor Entries:
- * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
- * CPU Signature (Stepping, Model, Family),
- * Feature Flags
- */
- smp_write_processors(mc);
-
- /*
- * Type 1: Bus Entries:
- * Bus ID, Bus Type
- */
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /*
- * Type 2: I/O APICs:
- * APIC ID, Version, APIC Flags:EN, Address
- */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /*
- * Type 3: I/O Interrupt Table Entries:
- * Int Type, Int Polarity, Int Level, Source Bus ID,
- * Source Bus IRQ, Dest APIC ID, Dest PIN#
- */
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
-
- /* SMBUS / ACPI */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
-
- /* Southbridge HD Audio */
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
-
- /* LPC */
- PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
- PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
- PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]);
- PCI_INT(0x0, 0x16, 0x2, intr_data_ptr[PIRQ_EHCI3]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]);
-
- /* SATA */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
-
- /* on board NIC & Slot PCIE */
- PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]);
- PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]);
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0 */
- PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]);
- PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]);
- PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]);
- PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]);
-
- /* PCI_SLOT 1 */
- PCI_INT(bus_pci, 0x6, 0x0, intr_data_ptr[PIRQ_F]);
- PCI_INT(bus_pci, 0x6, 0x1, intr_data_ptr[PIRQ_G]);
- PCI_INT(bus_pci, 0x6, 0x2, intr_data_ptr[PIRQ_H]);
- PCI_INT(bus_pci, 0x6, 0x3, intr_data_ptr[PIRQ_E]);
-
- /* PCI_SLOT 2 */
- PCI_INT(bus_pci, 0x7, 0x0, intr_data_ptr[PIRQ_G]);
- PCI_INT(bus_pci, 0x7, 0x1, intr_data_ptr[PIRQ_H]);
- PCI_INT(bus_pci, 0x7, 0x2, intr_data_ptr[PIRQ_E]);
- PCI_INT(bus_pci, 0x7, 0x3, intr_data_ptr[PIRQ_F]);
-
- PCI_INT(bus_pci, 0x0, 0x0, intr_data_ptr[PIRQ_C]);
- PCI_INT(bus_pci, 0x0, 0x1, intr_data_ptr[PIRQ_D]);
- PCI_INT(bus_pci, 0x0, 0x2, intr_data_ptr[PIRQ_E]);
- }
-
- /* PCIe Lan*/
- //PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_D]);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_A]);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_B]);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_C]);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_D]);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/elmex/pcm205400/Kconfig b/src/mainboard/elmex/pcm205400/Kconfig
index e94a6d8..5892992 100644
--- a/src/mainboard/elmex/pcm205400/Kconfig
+++ b/src/mainboard/elmex/pcm205400/Kconfig
@@ -39,7 +39,6 @@
select SUPERIO_FINTEK_F81865F
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096
diff --git a/src/mainboard/elmex/pcm205400/mptable.c b/src/mainboard/elmex/pcm205400/mptable.c
deleted file mode 100644
index bc7a3ac..0000000
--- a/src/mainboard/elmex/pcm205400/mptable.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <stdint.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <drivers/generic/ioapic/chip.h>
-#include <arch/ioapic.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- /* Initialize the MP_Table */
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- /*
- * Type 0: Processor Entries:
- * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
- * CPU Signature (Stepping, Model, Family),
- * Feature Flags
- */
- smp_write_processors(mc);
-
- /*
- * Type 1: Bus Entries:
- * Bus ID, Bus Type
- */
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /*
- * Type 2: I/O APICs:
- * APIC ID, Version, APIC Flags:EN, Address
- */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /*
- * Type 3: I/O Interrupt Table Entries:
- * Int Type, Int Polarity, Int Level, Source Bus ID,
- * Source Bus IRQ, Dest APIC ID, Dest PIN#
- */
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
-
- /* SMBUS / ACPI */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
-
- /* Southbridge HD Audio */
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
-
- /* LPC */
- PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
- PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
- PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
- PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]);
-
- /* IDE */
- PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]);
-
- /* SATA */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
-
- /* on board NIC & Slot PCIE */
- PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
- PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0 */
- PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
- PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
- PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
- PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
- }
-
- /* PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
- /* PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
- /* PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
- /* PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/gizmosphere/gizmo/Kconfig b/src/mainboard/gizmosphere/gizmo/Kconfig
index e195e8f..30c88c1 100644
--- a/src/mainboard/gizmosphere/gizmo/Kconfig
+++ b/src/mainboard/gizmosphere/gizmo/Kconfig
@@ -23,7 +23,6 @@
select SOUTHBRIDGE_AMD_CIMX_SB800
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_2048
diff --git a/src/mainboard/gizmosphere/gizmo/mptable.c b/src/mainboard/gizmosphere/gizmo/mptable.c
deleted file mode 100644
index a47336c..0000000
--- a/src/mainboard/gizmosphere/gizmo/mptable.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- * Copyright (C) 2013 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device*/
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
- /* Southbridge HD Audio: */
- PCI_INT(0x0, 0x14, 0x2, 0x12);
-
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/gizmosphere/gizmo2/Kconfig b/src/mainboard/gizmosphere/gizmo2/Kconfig
index 685e271..6a8095d 100644
--- a/src/mainboard/gizmosphere/gizmo2/Kconfig
+++ b/src/mainboard/gizmosphere/gizmo2/Kconfig
@@ -28,7 +28,6 @@
select DEFAULT_POST_ON_LPC
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096
diff --git a/src/mainboard/gizmosphere/gizmo2/mptable.c b/src/mainboard/gizmosphere/gizmo2/mptable.c
deleted file mode 100644
index e4edc5f..0000000
--- a/src/mainboard/gizmosphere/gizmo2/mptable.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <drivers/generic/ioapic/chip.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- /* Initialize the MP_Table */
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- /*
- * Type 0: Processor Entries:
- * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
- * CPU Signature (Stepping, Model, Family),
- * Feature Flags
- */
- smp_write_processors(mc);
-
- /*
- * Type 1: Bus Entries:
- * Bus ID, Bus Type
- */
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /*
- * Type 2: I/O APICs:
- * APIC ID, Version, APIC Flags:EN, Address
- */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /*
- * Type 3: I/O Interrupt Table Entries:
- * Int Type, Int Polarity, Int Level, Source Bus ID,
- * Source Bus IRQ, Dest APIC ID, Dest PIN#
- */
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
-
- /* SMBUS / ACPI */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
-
- /* Southbridge HD Audio */
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
-
- /* LPC */
- PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
- PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
- PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]);
- PCI_INT(0x0, 0x16, 0x2, intr_data_ptr[PIRQ_EHCI3]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]);
-
- /* SATA */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
-
- /* on board NIC & Slot PCIE */
- PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]);
- PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]);
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0 */
- PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]);
- PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]);
- PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]);
- PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]);
-
- /* PCI_SLOT 1 */
- PCI_INT(bus_pci, 0x6, 0x0, intr_data_ptr[PIRQ_F]);
- PCI_INT(bus_pci, 0x6, 0x1, intr_data_ptr[PIRQ_G]);
- PCI_INT(bus_pci, 0x6, 0x2, intr_data_ptr[PIRQ_H]);
- PCI_INT(bus_pci, 0x6, 0x3, intr_data_ptr[PIRQ_E]);
-
- /* PCI_SLOT 2 */
- PCI_INT(bus_pci, 0x7, 0x0, intr_data_ptr[PIRQ_G]);
- PCI_INT(bus_pci, 0x7, 0x1, intr_data_ptr[PIRQ_H]);
- PCI_INT(bus_pci, 0x7, 0x2, intr_data_ptr[PIRQ_E]);
- PCI_INT(bus_pci, 0x7, 0x3, intr_data_ptr[PIRQ_F]);
-
- PCI_INT(bus_pci, 0x0, 0x0, intr_data_ptr[PIRQ_C]);
- PCI_INT(bus_pci, 0x0, 0x1, intr_data_ptr[PIRQ_D]);
- PCI_INT(bus_pci, 0x0, 0x2, intr_data_ptr[PIRQ_E]);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_D]);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_A]);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_B]);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_C]);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_D]);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/google/kahlee/mptable.c b/src/mainboard/google/kahlee/mptable.c
deleted file mode 100644
index 5bb70e9..0000000
--- a/src/mainboard/google/kahlee/mptable.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <soc/southbridge.h>
-#include <amdblocks/amd_pci_util.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- //mptable_write_buses(mc, NULL, &bus_isa);
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), \
- MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, \
- (intr), (apicid), (pin))
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, \
- MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), \
- (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/hp/abm/Kconfig b/src/mainboard/hp/abm/Kconfig
index 907c025..6239086 100644
--- a/src/mainboard/hp/abm/Kconfig
+++ b/src/mainboard/hp/abm/Kconfig
@@ -29,7 +29,6 @@
select SUPERIO_NUVOTON_NCT5104D
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_8192
diff --git a/src/mainboard/hp/abm/mptable.c b/src/mainboard/hp/abm/mptable.c
deleted file mode 100644
index 7082013..0000000
--- a/src/mainboard/hp/abm/mptable.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <southbridge/amd/agesa/hudson/hudson.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- //mptable_write_buses(mc, NULL, &bus_isa);
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig
index c6c35df..1f17a15 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig
+++ b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig
@@ -25,7 +25,6 @@
select EC_COMPAL_ENE932
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_SMI_HANDLER
select HAVE_ACPI_TABLES
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c
deleted file mode 100644
index ecc57b0..0000000
--- a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/ioapic.h>
-#include <arch/smp/mpspec.h>
-#include <cpu/x86/lapic.h>
-#include <stdint.h>
-#include <string.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <southbridge/amd/agesa/hudson/hudson.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- //mptable_write_buses(mc, NULL, &bus_isa);
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* IOMMU */
- PCI_INT(0x0, 0x00, 0x0, 0x10);
- PCI_INT(0x0, 0x00, 0x1, 0x11);
- PCI_INT(0x0, 0x00, 0x2, 0x12);
- PCI_INT(0x0, 0x00, 0x3, 0x13);
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig b/src/mainboard/jetway/nf81-t56n-lf/Kconfig
index dfa01b9..dddca36 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig
+++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig
@@ -28,7 +28,6 @@
select SUPERIO_FINTEK_F71869AD
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_2048
diff --git a/src/mainboard/jetway/nf81-t56n-lf/mptable.c b/src/mainboard/jetway/nf81-t56n-lf/mptable.c
deleted file mode 100644
index 9a983b4..0000000
--- a/src/mainboard/jetway/nf81-t56n-lf/mptable.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/ioapic.h>
-#include <arch/smp/mpspec.h>
-#include <drivers/generic/ioapic/chip.h>
-#include <stdint.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- /* Initialize the MP_Table */
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- /*
- * Type 0: Processor Entries:
- * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
- * CPU Signature (Stepping, Model, Family),
- * Feature Flags
- */
- smp_write_processors(mc);
-
- /*
- * Type 1: Bus Entries:
- * Bus ID, Bus Type
- */
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /*
- * Type 2: I/O APICs:
- * APIC ID, Version, APIC Flags:EN, Address
- */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /*
- * Type 3: I/O Interrupt Table Entries:
- * Int Type, Int Polarity, Int Level, Source Bus ID,
- * Source Bus IRQ, Dest APIC ID, Dest PIN#
- */
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
-
- /* SMBUS / ACPI */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
-
- /* Southbridge HD Audio */
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
-
- /* LPC */
- PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
- PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
- PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
- PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]);
-
- /* IDE */
- PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]);
-
- /* SATA */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
-
- /* On-board NIC & Slot PCIE. */
- PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
- PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0 */
- PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
- PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
- PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
- PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
- }
-
- /* On-board Realtek NIC 2. (PCIe PortA) */
- PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
- /* PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
- /* PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
- /* PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig
index 6ffe508..7f0d7bf 100644
--- a/src/mainboard/lenovo/g505s/Kconfig
+++ b/src/mainboard/lenovo/g505s/Kconfig
@@ -24,7 +24,6 @@
select DEFAULT_POST_ON_LPC
select EC_COMPAL_ENE932
select HAVE_OPTION_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_SMI_HANDLER
select HAVE_ACPI_TABLES
diff --git a/src/mainboard/lenovo/g505s/mptable.c b/src/mainboard/lenovo/g505s/mptable.c
deleted file mode 100644
index ecc57b0..0000000
--- a/src/mainboard/lenovo/g505s/mptable.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/ioapic.h>
-#include <arch/smp/mpspec.h>
-#include <cpu/x86/lapic.h>
-#include <stdint.h>
-#include <string.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <southbridge/amd/agesa/hudson/hudson.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- //mptable_write_buses(mc, NULL, &bus_isa);
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* IOMMU */
- PCI_INT(0x0, 0x00, 0x0, 0x10);
- PCI_INT(0x0, 0x00, 0x1, 0x11);
- PCI_INT(0x0, 0x00, 0x2, 0x12);
- PCI_INT(0x0, 0x00, 0x3, 0x13);
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/lippert/frontrunner-af/Kconfig b/src/mainboard/lippert/frontrunner-af/Kconfig
index 4a007bf..64a8f14 100644
--- a/src/mainboard/lippert/frontrunner-af/Kconfig
+++ b/src/mainboard/lippert/frontrunner-af/Kconfig
@@ -27,7 +27,6 @@
select SUPERIO_SMSC_SMSCSUPERIO
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
# This erases 28 KB and writes 10 KB register dumps to SPI flash on every
# boot, wasting 3 s and causing wear! Therefore disable S3 for now.
#select HAVE_ACPI_RESUME
diff --git a/src/mainboard/lippert/frontrunner-af/mptable.c b/src/mainboard/lippert/frontrunner-af/mptable.c
deleted file mode 100644
index 78b8ec2..0000000
--- a/src/mainboard/lippert/frontrunner-af/mptable.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device*/
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
- /* Southbridge HD Audio: */
- PCI_INT(0x0, 0x14, 0x2, 0x12);
-
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/lippert/toucan-af/Kconfig b/src/mainboard/lippert/toucan-af/Kconfig
index b62da2e..e97099b 100644
--- a/src/mainboard/lippert/toucan-af/Kconfig
+++ b/src/mainboard/lippert/toucan-af/Kconfig
@@ -29,7 +29,6 @@
select SUPERIO_WINBOND_W83627DHG
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
# This erases 28 KB and writes 10 KB register dumps to SPI flash on every
# boot, wasting 3 s and causing wear! Therefore disable S3 for now.
#select HAVE_ACPI_RESUME
diff --git a/src/mainboard/lippert/toucan-af/mptable.c b/src/mainboard/lippert/toucan-af/mptable.c
deleted file mode 100644
index 78b8ec2..0000000
--- a/src/mainboard/lippert/toucan-af/mptable.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device*/
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
- /* Southbridge HD Audio: */
- PCI_INT(0x0, 0x14, 0x2, 0x12);
-
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/msi/ms7721/Kconfig b/src/mainboard/msi/ms7721/Kconfig
index 1fee747..b57bc48 100644
--- a/src/mainboard/msi/ms7721/Kconfig
+++ b/src/mainboard/msi/ms7721/Kconfig
@@ -25,7 +25,6 @@
select SOUTHBRIDGE_AMD_AGESA_HUDSON
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select SUPERIO_FINTEK_F71869AD
select BOARD_ROMSIZE_KB_8192
diff --git a/src/mainboard/msi/ms7721/mptable.c b/src/mainboard/msi/ms7721/mptable.c
deleted file mode 100644
index fd55eda..0000000
--- a/src/mainboard/msi/ms7721/mptable.c
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/ioapic.h>
-#include <arch/smp/mpspec.h>
-#include <cpu/x86/lapic.h>
-#include <stdint.h>
-#include <string.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <southbridge/amd/agesa/hudson/hudson.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- //mptable_write_buses(mc, NULL, &bus_isa);
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* IOMMU */
- PCI_INT(0x0, 0x0, 0x0, 0x10);
- PCI_INT(0x0, 0x0, 0x1, 0x11);
- PCI_INT(0x0, 0x0, 0x2, 0x12);
- PCI_INT(0x0, 0x0, 0x3, 0x13);
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig
index 3396845..9871051 100644
--- a/src/mainboard/pcengines/apu1/Kconfig
+++ b/src/mainboard/pcengines/apu1/Kconfig
@@ -23,7 +23,6 @@
select SOUTHBRIDGE_AMD_CIMX_SB800
select SUPERIO_NUVOTON_NCT5104D
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select HAVE_OPTION_TABLE
diff --git a/src/mainboard/pcengines/apu1/mptable.c b/src/mainboard/pcengines/apu1/mptable.c
deleted file mode 100644
index 89e5dfc..0000000
--- a/src/mainboard/pcengines/apu1/mptable.c
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <stdint.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <drivers/generic/ioapic/chip.h>
-#include <arch/ioapic.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- /* Initialize the MP_Table */
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- /*
- * Type 0: Processor Entries:
- * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
- * CPU Signature (Stepping, Model, Family),
- * Feature Flags
- */
- smp_write_processors(mc);
-
- /*
- * Type 1: Bus Entries:
- * Bus ID, Bus Type
- */
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /*
- * Type 2: I/O APICs:
- * APIC ID, Version, APIC Flags:EN, Address
- */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /*
- * Type 3: I/O Interrupt Table Entries:
- * Int Type, Int Polarity, Int Level, Source Bus ID,
- * Source Bus IRQ, Dest APIC ID, Dest PIN#
- */
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
-
- /* SMBUS / ACPI */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
-
- /* Southbridge HD Audio */
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
-
- /* LPC */
- PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
- PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
- PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
- PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]);
-
- /* IDE */
- PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]);
-
- /* SATA */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
-
- /* on board NIC & Slot PCIE */
- PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
- PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
- PCI_INT(0x3, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
- PCI_INT(0x4, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
-
- /* PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
- /* PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
- /* PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
- /* PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig
index 8c713e5..604d490 100644
--- a/src/mainboard/pcengines/apu2/Kconfig
+++ b/src/mainboard/pcengines/apu2/Kconfig
@@ -26,7 +26,6 @@
select DEFAULT_POST_ON_LPC
select SUPERIO_NUVOTON_NCT5104D
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_8192
select USE_BLOBS
diff --git a/src/mainboard/pcengines/apu2/mptable.c b/src/mainboard/pcengines/apu2/mptable.c
deleted file mode 100644
index 772ee31..0000000
--- a/src/mainboard/pcengines/apu2/mptable.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <stdint.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /* Initialize the MP_Table */
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- /*
- * Type 0: Processor Entries:
- * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
- * CPU Signature (Stepping, Model, Family),
- * Feature Flags
- */
- smp_write_processors(mc);
-
- /*
- * Type 1: Bus Entries:
- * Bus ID, Bus Type
- */
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /*
- * Type 2: I/O APICs:
- * APIC ID, Version, APIC Flags:EN, Address
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- /*
- * Type 3: I/O Interrupt Table Entries:
- * Int Type, Int Polarity, Int Level, Source Bus ID,
- * Source Bus IRQ, Dest APIC ID, Dest PIN#
- */
-
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
-
- /* SMBUS / ACPI */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
-
- /* SD card */
- PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_SD]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[PIRQ_EHCI1]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[PIRQ_EHCI2]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[PIRQ_EHCI3]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]);
-
- /* SATA */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
-
- /* on board NIC & Slot PCIE */
- PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]);
- PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]);
-
-
- /* GPP0 */
- PCI_INT(0x0, 0x2, 0x0, 0x10); // Network 3
- /* GPP1 */
- PCI_INT(0x0, 0x2, 0x1, 0x11); // Network 2
- /* GPP2 */
- PCI_INT(0x0, 0x2, 0x2, 0x12); // Network 1
- /* GPP3 */
- PCI_INT(0x0, 0x2, 0x3, 0x13); // mPCI
- /* GPP4 */
- PCI_INT(0x0, 0x2, 0x4, 0x14); // mPCI
-
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
-
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */
- return (unsigned long)smp_write_config_table(v);
-}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Idd13b8b006fce7383f3f73c3c0a5d51a71c0155b
Gerrit-Change-Number: 38313
Gerrit-PatchSet: 1
Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-MessageType: newchange
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