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Change in coreboot[master]: mb/ocp/deltalake: Configure IIO PCIe ports via FSP
by Johnny Lin (Code Review) 12 May '21

12 May '21

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42096 ) Change subject: mb/ocp/deltalake: Configure IIO PCIe ports via FSP ...................................................................... mb/ocp/deltalake: Configure IIO PCIe ports via FSP Change-Id: I7cff6d71588f91c3210cbaa17484644d5b89cc62 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/mainboard/ocp/deltalake/cpxsp_dl_iio.h M src/mainboard/ocp/deltalake/romstage.c M src/soc/intel/xeon_sp/cpx/acpi.c M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h 5 files changed, 271 insertions(+), 80 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/42096/1 diff --git a/src/mainboard/ocp/deltalake/cpxsp_dl_iio.h b/src/mainboard/ocp/deltalake/cpxsp_dl_iio.h index b7f8c85..b9535ff 100644 --- a/src/mainboard/ocp/deltalake/cpxsp_dl_iio.h +++ b/src/mainboard/ocp/deltalake/cpxsp_dl_iio.h @@ -5,69 +5,82 @@ #include <FspmUpd.h> #include <soc/pci_devs.h> +#include <hob_iiouds.h> -#if 0 /* * DeltaLake Iio PCIe Port Table */ -static const UPD_PCI_PORT_CONFIG dl_iio_pci_port = { - // PortIndex | HidePort | DeEmphasis | PortLinkSpeed | MaxPayload | - // DfxDnTxPreset | DfxRxPreset | DfxUpTxPreset | Sris | PcieCommonClock | NtbPpd | - // NtbSplitBar | NtbBarSizePBar23 | NtbBarSizePBar4 | NtbBarSizePBar5 | - // NtbBarSizePBar45 | NtbBarSizeSBar23 | NtbBarSizeSBar4 | NtbBarSizeSbar5 | - // NtbBarSizeSBar45 | NtbSBar01Prefetch | NtbXlinkCtlOverride -/* - { PORT_1A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_1B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_1C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_1D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_2A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_2B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_2C, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_2D, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_3A, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_3B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_3C, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_3D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_4A, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_4B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_4C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_4D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, -*/ +static const UPD_IIO_PCIE_PORT_CONFIG dl_iio_pci_port[] = { + /* Socket | PortIndex | HidePort | DeEmphasis | PortLinkSpeed | MaxPayload | + DfxDnTxPreset | DfxRxPreset | DfxUpTxPreset | Sris | PcieCommonClock | NtbIndex | + NtbPpd | NtbBarSizeOverride | NtbSplitBar | NtbBarSizeImBar1 | NtbBarSizeImBar2 + NtbBarSizeImBar2_0 | NtbBarSizeImBar2_1| NtbBarSizeEmBarSZ1 | NtbBarSizeEmBarSZ2 + NtbBarSizeEmBarSZ2_0 | NtbBarSizeEmBarSZ2_1 | NtbXlinkCtlOverride */ + /* PORT_1A ~ PORT_1D */ + { 0, PORT_1A, NOT_HIDE, 0x00, PcieAuto, 0x0, + 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF, + NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16, + 0x0C, 0x0C, 0x16, 0x16, + 0x0C, 0x0C, 0x03}, + { 0, PORT_1B, NOT_HIDE, 0x00, PcieAuto, 0x0, + 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF, + NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16, + 0x0C, 0x0C, 0x16, 0x16, + 0x0C, 0x0C, 0x03}, + { 0, PORT_1C, NOT_HIDE, 0x00, PcieAuto, 0x0, + 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF, + NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16, + 0x0C, 0x0C, 0x16, 0x16, + 0x0C, 0x0C, 0x03}, + { 0, PORT_1D, NOT_HIDE, 0x00, PcieAuto, 0x0, + 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF, + NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16, + 0x0C, 0x0C, 0x16, 0x16, + 0x0C, 0x0C, 0x03}, + /* PORT_2A ~ PORT_2D */ + { 0, PORT_2A, NOT_HIDE, 0x00, PcieAuto, 0x0, + 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF, + NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16, + 0x0C, 0x0C, 0x16, 0x16, + 0x0C, 0x0C, 0x03}, + { 0, PORT_2B, NOT_HIDE, 0x00, PcieAuto, 0x0, + 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF, + NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16, + 0x0C, 0x0C, 0x16, 0x16, + 0x0C, 0x0C, 0x03}, + { 0, PORT_2C, NOT_HIDE, 0x00, PcieAuto, 0x0, + 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF, + NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16, + 0x0C, 0x0C, 0x16, 0x16, + 0x0C, 0x0C, 0x03}, + { 0, PORT_2D, NOT_HIDE, 0x00, PcieAuto, 0x0, + 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF, + NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16, + 0x0C, 0x0C, 0x16, 0x16, + 0x0C, 0x0C, 0x03}, + /* PORT_3A ~ PORT_3D does not exist */ + /* PORT_4A ~ PORT_4D */ + { 0, PORT_4A, NOT_HIDE, 0x00, PcieAuto, 0x0, + 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF, + NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16, + 0x0C, 0x0C, 0x16, 0x16, + 0x0C, 0x0C, 0x03}, + { 0, PORT_4B, NOT_HIDE, 0x00, PcieAuto, 0x0, + 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF, + NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16, + 0x0C, 0x0C, 0x16, 0x16, + 0x0C, 0x0C, 0x03}, + { 0, PORT_4C, NOT_HIDE, 0x00, PcieAuto, 0x0, + 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF, + NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16, + 0x0C, 0x0C, 0x16, 0x16, + 0x0C, 0x0C, 0x03}, + { 0, PORT_4D, NOT_HIDE, 0x00, PcieAuto, 0x0, + 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF, + NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16, + 0x0C, 0x0C, 0x16, 0x16, + 0x0C, 0x0C, 0x03}, }; -#endif /* * DeltaLake PCH PCIe Port Table diff --git a/src/mainboard/ocp/deltalake/romstage.c b/src/mainboard/ocp/deltalake/romstage.c index eabbd6b..ecfb910 100644 --- a/src/mainboard/ocp/deltalake/romstage.c +++ b/src/mainboard/ocp/deltalake/romstage.c @@ -61,13 +61,30 @@ uint8_t index; oem_update_iio(mupd); - -#if 0 - mupd->FspmConfig.IioPciConfig.ConfigurationTable = - (UPD_PCI_PORT_CONFIG *) dl_iio_pci_port; - mupd->FspmConfig.IioPciConfig.NumberOfEntries = - ARRAY_SIZE(dl_iio_pci_port); -#endif + /* Config IIO PCIe ports from table */ + mupd->FspmConfig.IioPcieConfigTablePtr = (uint32_t) dl_iio_pci_port; + mupd->FspmConfig.IioPcieConfigTableNumber = ARRAY_SIZE(dl_iio_pci_port); + /* Config all IIO PCIe ports? */ + mupd->FspmConfig.IIOPcieRootPortEnable = 1; + mupd->FspmConfig.DeEmphasis = 0x00; + mupd->FspmConfig.IIOPciePortLinkSpeed = PcieAuto; //0 + mupd->FspmConfig.IIOPcieMaxPayload = 0x0; + mupd->FspmConfig.DfxDnTxPreset = 0xFF; + mupd->FspmConfig.DfxRxPreset = 0xFF; + mupd->FspmConfig.DfxUpTxPreset = 0xFF; + mupd->FspmConfig.PcieCommonClock = 0x1; + mupd->FspmConfig.NtbPpd = NTB_PORT_TRANSPARENT; //0 + mupd->FspmConfig.NtbBarSizeOverride = 0x00; + mupd->FspmConfig.NtbSplitBar = 0x00; + mupd->FspmConfig.NtbBarSizeImBar1 = 0x16; + mupd->FspmConfig.NtbBarSizeImBar2 = 0x16; + mupd->FspmConfig.NtbBarSizeImBar2_0 = 0x0C; + mupd->FspmConfig.NtbBarSizeImBar2_1 = 0x0C; + mupd->FspmConfig.NtbBarSizeEmBarSZ1 = 0x16; + mupd->FspmConfig.NtbBarSizeEmBarSZ2 = 0x16; + mupd->FspmConfig.NtbBarSizeEmBarSZ2_0 = 0x0C; + mupd->FspmConfig.NtbBarSizeEmBarSZ2_1 = 0x0C; + mupd->FspmConfig.NtbXlinkCtlOverride = 0x03; for (index = 0; index < ARRAY_SIZE(dl_pch_pci_port); index++) { mupd->FspmConfig.PchPcieForceEnable[dl_pch_pci_port[index].PortIndex] = diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index 8cdd01e..6789e92 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -424,11 +424,11 @@ else if (p >= PORT_2A && p <= PORT_2D) return PSTACK1; else if (p >= PORT_4A && p <= PORT_4D) - return PSTACK2; + return PSTACK3; else if (p >= PORT_5A && p <= PORT_5D) - return PSTACK3; // MCP0 + return PSTACK4; // MCP0 else - return PSTACK4; // MCP1 + return MAX_STACKS; // MCP1 } static unsigned long acpi_create_drhd(unsigned long current, int socket, int stack, diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h index 4374058..72a3b13 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h @@ -77,6 +77,9 @@ KTI_LINK5 } KTI_LOGIC_LINK; +#define HIDE 1 +#define NOT_HIDE 0 + #define IIO_BIFURCATE_xxxxxxxx 0xFE #define IIO_BIFURCATE_x4x4x4x4 0x0 #define IIO_BIFURCATE_x4x4xxx8 0x1 @@ -133,6 +136,44 @@ Iio_IouMax } IIO_IOUS; +typedef struct { + //For IioPcieConfig + UINT8 Socket; + UINT16 PortIndex; + UINT8 HidePort; + UINT8 DeEmphasis; + UINT8 PortLinkSpeed; + UINT8 MaxPayload; + UINT8 DfxDnTxPreset; + UINT8 DfxRxPreset; + UINT8 DfxUpTxPreset; + UINT8 Sris; + UINT8 PcieCommonClock; + //For IIO Ntb^M + UINT8 NtbIndex; + UINT8 NtbPpd; + UINT8 NtbBarSizeOverride; + UINT8 NtbSplitBar; + UINT8 NtbBarSizeImBar1; + UINT8 NtbBarSizeImBar2; + UINT8 NtbBarSizeImBar2_0; + UINT8 NtbBarSizeImBar2_1; + UINT8 NtbBarSizeEmBarSZ1; + UINT8 NtbBarSizeEmBarSZ2; + UINT8 NtbBarSizeEmBarSZ2_0; + UINT8 NtbBarSizeEmBarSZ2_1; + UINT8 NtbXlinkCtlOverride; +} UPD_IIO_PCIE_PORT_CONFIG; + +/** + NTB Per Port Definition + **/ +typedef enum { + NTB_PORT_TRANSPARENT = 0, + NTB_PORT_NTB_NTB +} NTB_PPD; + + /** UPD_PCH_PCIE_PORT: PortIndex - PCH PCIe Port Index. @@ -535,45 +576,160 @@ **/ UINT8 IioConfigIOU4[8]; -/** Offset 0x00F7 - PchAdrEn +/** Offset 0x00F7 +**/ + UINT8 UnusedUpdSpace4; + +/** Offset 0x00F8 - Usage type for IIO PCIE Config Table Ptr + IIO PCIE Config Table Ptr +**/ + UINT32 IioPcieConfigTablePtr; + +/** Offset 0x00FC - Usage type for IIO PCIE Config Table Number + IIO PCIE Config Table Number +**/ + UINT32 IioPcieConfigTableNumber; + +/** Offset 0x0100 - Usage type for IIO PCIE Root Port Enable or Disable + IIO PCH rootport, if port is enabled, the value is 0x01, if the port is disabled, + the value is 0x00 +**/ + UINT8 IIOPcieRootPortEnable; + +/** Offset 0x0101 - Usage type for IIO DeEmphasis + IIO DeEmphasis +**/ + UINT8 DeEmphasis; + +/** Offset 0x0102 - Usage type for IIO PCIE Root Port link speed + IIO root port link speed +**/ + UINT8 IIOPciePortLinkSpeed; + +/** Offset 0x0103 - Usage type for IIO PCIE Root Port Max Payload + IIO Root Port Max Payload +**/ + UINT8 IIOPcieMaxPayload; + +/** Offset 0x0104 - Usage type for IIO DfxDnTxPreset + IIO DfxDnTxPreset +**/ + UINT8 DfxDnTxPreset; + +/** Offset 0x0105 - Usage type for IIO DfxRxPreset + IIO DfxRxPreset +**/ + UINT8 DfxRxPreset; + +/** Offset 0x0106 - Usage type for IIO DfxUpTxPreset + IIO DfxUpTxPreset +**/ + UINT8 DfxUpTxPreset; + +/** Offset 0x0107 - Usage type for IIO PcieCommonClock + IIO PcieCommonClock +**/ + UINT8 PcieCommonClock; + +/** Offset 0x0108 - Usage type for IIO NtbPpd + IIO NtbPpd +**/ + UINT8 NtbPpd; + +/** Offset 0x0109 - Usage type for IIO NtbBarSizeOverride + IIO NtbBarSizeOverride +**/ + UINT8 NtbBarSizeOverride; + +/** Offset 0x010A - Usage type for IIO NtbSplitBar + IIO NtbSplitBar +**/ + UINT8 NtbSplitBar; + +/** Offset 0x010B - Usage type for IIO NtbBarSizeImBar1 + IIO NtbBarSizeImBar1 +**/ + UINT8 NtbBarSizeImBar1; + +/** Offset 0x010C - Usage type for IIO NtbBarSizeImBar2 + IIO PNtbBarSizeImBar2 +**/ + UINT8 NtbBarSizeImBar2; + +/** Offset 0x010D - Usage type for IIO NtbBarSizeImBar2_0 + IIO PNtbBarSizeImBar2_0 +**/ + UINT8 NtbBarSizeImBar2_0; + +/** Offset 0x010E - Usage type for IIO NtbBarSizeImBar2_1 + IIO NtbBarSizeImBar2_1 +**/ + UINT8 NtbBarSizeImBar2_1; + +/** Offset 0x010F - Usage type for IIO NtbBarSizeEmBarSZ1 + IIO NtbBarSizeEmBarSZ1 +**/ + UINT8 NtbBarSizeEmBarSZ1; + +/** Offset 0x0110 - Usage type for IIO NtbBarSizeEmBarSZ2 + IIO NtbBarSizeEmBarSZ2 +**/ + UINT8 NtbBarSizeEmBarSZ2; + +/** Offset 0x0111 - Usage type for IIO NtbBarSizeEmBarSZ2_0 + IIO NtbBarSizeEmBarSZ2_0 +**/ + UINT8 NtbBarSizeEmBarSZ2_0; + +/** Offset 0x0112 - Usage type for IIO NtbBarSizeEmBarSZ2_1 + IIO NtbBarSizeEmBarSZ2_1 +**/ + UINT8 NtbBarSizeEmBarSZ2_1; + +/** Offset 0x0113 - Usage type for IIO NtbXlinkCtlOverride + IIO NtbXlinkCtlOverride +**/ + UINT8 NtbXlinkCtlOverride; + +/** Offset 0x0114 - PchAdrEn Enable or Disable PchAdr **/ UINT8 PchAdrEn; -/** Offset 0x00F8 - } TYPE:{Combo +/** Offset 0x0115 - } TYPE:{Combo Root port swapping based on device connection status : TRUE or FALSE TRUE : 0x01, FALSE : 0x00 **/ UINT8 PchPcieRootPortFunctionSwap; -/** Offset 0x00F9 - PCH PCIE PLL Ssc +/** Offset 0x0116 - PCH PCIE PLL Ssc Valid spread range : 0x00-0x14 (A value of 0 is SSC of 0.0%. A value of 20 is SSC of 2.0%), Auto : 0xFE(Set to hardware default), Disable : 0xFF **/ UINT8 PchPciePllSsc; -/** Offset 0x00FA - Usage type for PCH PCIE Root Port Index +/** Offset 0x0117 - Usage type for PCH PCIE Root Port Index Index assigned to every PCH PCIE Root Port **/ UINT8 PchPciePortIndex[20]; -/** Offset 0x010E - Usage type for PCH PCIE Root Port Enable or Disable +/** Offset 0x012B - Usage type for PCH PCIE Root Port Enable or Disable 0-19: PCH rootport, if port is enabled, the value is 0x01, if the port is disabled, the value is 0x00 **/ UINT8 PchPcieForceEnable[20]; -/** Offset 0x0122 - Usage type for PCH PCIE Root Port Link Speed +/** Offset 0x013F - Usage type for PCH PCIE Root Port Link Speed 0-19: PCH rootport, 0x00 : Pcie Auto Speed, 0x01 : Pcie Gen1 Speed, 0x02 : Pcie Gen2 Speed, 0x03 : Pcie Gen3 Speed **/ UINT8 PchPciePortLinkSpeed[20]; -/** Offset 0x0136 +/** Offset 0x0153 **/ - UINT8 UnusedUpdSpace4[2]; + UINT8 UnusedUpdSpace5[1]; -/** Offset 0x0138 +/** Offset 0x0154 **/ UINT8 ReservedMemoryInitUpd[16]; } FSP_M_CONFIG; @@ -594,11 +750,11 @@ **/ FSP_M_CONFIG FspmConfig; -/** Offset 0x0148 +/** Offset 0x0164 **/ - UINT8 UnusedUpdSpace5[6]; + UINT8 UnusedUpdSpace6[2]; -/** Offset 0x014E +/** Offset 0x0166 **/ UINT16 UpdTerminator; } FSPM_UPD; diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h index 7ac630f..79b7d7a 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h @@ -102,6 +102,11 @@ PORT_2C, PORT_2D, // IOU2 + PORT_3A, + PORT_3B, + PORT_3C, + PORT_3D, + // IOU3 PORT_4A, PORT_4B, PORT_4C, -- To view, visit https://review.coreboot.org/c/coreboot/+/42096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cff6d71588f91c3210cbaa17484644d5b89cc62 Gerrit-Change-Number: 42096 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/riscv: Fixed exception handling when CONFIG_RISCV_WORKING_HARTID...
by Xiang Wang (Code Review) 08 May '21

08 May '21

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37461 ) Change subject: arch/riscv: Fixed exception handling when CONFIG_RISCV_WORKING_HARTID not equal 0 ...................................................................... arch/riscv: Fixed exception handling when CONFIG_RISCV_WORKING_HARTID not equal 0 Change-Id: Ic45560b4bfbf9366425ef4006ac2765113457349 Signed-off-by: Xiang Wang <merle(a)hardenedlinux.org> --- M src/arch/riscv/trap_util.S 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/37461/1 diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index 8aba48b..8c1f6cc 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -118,6 +118,7 @@ # someday this gets fixed. //csrr sp, mhartid csrr sp, 0xf14 + addi sp, sp, -CONFIG_RISCV_WORKING_HARTID .Lsmp_hang: bnez sp, .Lsmp_hang -- To view, visit https://review.coreboot.org/c/coreboot/+/37461 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic45560b4bfbf9366425ef4006ac2765113457349 Gerrit-Change-Number: 37461 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <merle(a)hardenedlinux.org> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: [WIP]mb/lenovo/w541: Add Lenovo ThinkPad W541
by Peter Lemenkov (Code Review) 26 Apr '21

26 Apr '21

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38733 ) Change subject: [WIP]mb/lenovo/w541: Add Lenovo ThinkPad W541 ...................................................................... [WIP]mb/lenovo/w541: Add Lenovo ThinkPad W541 UNTESTED. Change-Id: I315627cba495bfc376321c632248e50734daac71 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- A src/mainboard/lenovo/w541/Kconfig A src/mainboard/lenovo/w541/Kconfig.name A src/mainboard/lenovo/w541/Makefile.inc A src/mainboard/lenovo/w541/acpi/ec.asl A src/mainboard/lenovo/w541/acpi/platform.asl A src/mainboard/lenovo/w541/acpi/superio.asl A src/mainboard/lenovo/w541/acpi_tables.c A src/mainboard/lenovo/w541/board_info.txt A src/mainboard/lenovo/w541/data.vbt A src/mainboard/lenovo/w541/devicetree.cb A src/mainboard/lenovo/w541/dsdt.asl A src/mainboard/lenovo/w541/gma-mainboard.ads A src/mainboard/lenovo/w541/gpio.c A src/mainboard/lenovo/w541/hda_verb.c A src/mainboard/lenovo/w541/mainboard.c A src/mainboard/lenovo/w541/romstage.c A src/mainboard/lenovo/w541/smihandler.c 17 files changed, 807 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/38733/1 diff --git a/src/mainboard/lenovo/w541/Kconfig b/src/mainboard/lenovo/w541/Kconfig new file mode 100644 index 0000000..4c016fa --- /dev/null +++ b/src/mainboard/lenovo/w541/Kconfig @@ -0,0 +1,42 @@ +if BOARD_LENOVO_THINKPAD_W541 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_2048 # FIXME: correct this + select CPU_INTEL_HASWELL + select EC_LENOVO_H8 + select EC_LENOVO_PMH7 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT # FIXME: check this + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SYSTEM_TYPE_LAPTOP + +config MAINBOARD_DIR + string + default "lenovo/w541" + +config MAINBOARD_PART_NUMBER + string + default "ThinkPad W541" + +config VGA_BIOS_FILE + string + default "pci8086,0416.rom" + +config VGA_BIOS_ID + string + default "8086,0416" + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/lenovo/w541/Kconfig.name b/src/mainboard/lenovo/w541/Kconfig.name new file mode 100644 index 0000000..f2ee59c --- /dev/null +++ b/src/mainboard/lenovo/w541/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_LENOVO_THINKPAD_W541 + bool "ThinkPad W541" diff --git a/src/mainboard/lenovo/w541/Makefile.inc b/src/mainboard/lenovo/w541/Makefile.inc new file mode 100644 index 0000000..fa6e7af --- /dev/null +++ b/src/mainboard/lenovo/w541/Makefile.inc @@ -0,0 +1,3 @@ +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +smm-y += smihandler.c diff --git a/src/mainboard/lenovo/w541/acpi/ec.asl b/src/mainboard/lenovo/w541/acpi/ec.asl new file mode 100644 index 0000000..3ff0ff7 --- /dev/null +++ b/src/mainboard/lenovo/w541/acpi/ec.asl @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Iru Cai <mytbk920423(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <ec/lenovo/h8/acpi/ec.asl> diff --git a/src/mainboard/lenovo/w541/acpi/platform.asl b/src/mainboard/lenovo/w541/acpi/platform.asl new file mode 100644 index 0000000..add8c2d --- /dev/null +++ b/src/mainboard/lenovo/w541/acpi/platform.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Iru Cai <mytbk920423(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK,1) +{ + /* ME may not be up yet. */ + Store (0, \_TZ.MEB1) + Store (0, \_TZ.MEB2) + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + \_SB.PCI0.LPCB.EC.RADI(0) +} diff --git a/src/mainboard/lenovo/w541/acpi/superio.asl b/src/mainboard/lenovo/w541/acpi/superio.asl new file mode 100644 index 0000000..3139e35 --- /dev/null +++ b/src/mainboard/lenovo/w541/acpi/superio.asl @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Iru Cai <mytbk920423(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/lenovo/w541/acpi_tables.c b/src/mainboard/lenovo/w541/acpi_tables.c new file mode 100644 index 0000000..ff6c05a --- /dev/null +++ b/src/mainboard/lenovo/w541/acpi_tables.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/lynxpoint/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* the lid is open by default */ + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/lenovo/w541/board_info.txt b/src/mainboard/lenovo/w541/board_info.txt new file mode 100644 index 0000000..cd1d140 --- /dev/null +++ b/src/mainboard/lenovo/w541/board_info.txt @@ -0,0 +1,4 @@ +Category: laptop +FIXME: put ROM package, ROM socketed, ROM protocol, Flashrom support +Board URL: https://www.lenovo.com/us/en/laptops/thinkpad/w-series/w541/ +Release year: 2015 diff --git a/src/mainboard/lenovo/w541/data.vbt b/src/mainboard/lenovo/w541/data.vbt new file mode 100644 index 0000000..4471ca1 --- /dev/null +++ b/src/mainboard/lenovo/w541/data.vbt Binary files differ diff --git a/src/mainboard/lenovo/w541/devicetree.cb b/src/mainboard/lenovo/w541/devicetree.cb new file mode 100644 index 0000000..d7057e4 --- /dev/null +++ b/src/mainboard/lenovo/w541/devicetree.cb @@ -0,0 +1,123 @@ +chip northbridge/intel/haswell # FIXME: check gfx.ndid and gfx.did + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx.ndid" = "3" + register "gpu_cpu_backlight" = "0x00000000" + register "gpu_ddi_e_connected" = "1" + register "gpu_dp_b_hotplug" = "0" + register "gpu_dp_c_hotplug" = "0" + register "gpu_dp_d_hotplug" = "0" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "0" + register "gpu_panel_power_backlight_on_delay" = "0" + register "gpu_panel_power_cycle_delay" = "0" + register "gpu_panel_power_down_delay" = "0" + register "gpu_panel_power_up_delay" = "0" + register "gpu_pch_backlight" = "0x00000000" + device cpu_cluster 0x0 on + chip cpu/intel/haswell + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on end + device lapic 0xacac off end + end + end + device domain 0x0 on + subsystemid 0x17aa 0x2211 inherit + + device pci 00.0 on end # Host bridge Host bridge + device pci 01.0 on end # PCIe Bridge for discrete graphics Unsupported PCI device 8086:0c01 + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x17aa 0x221e + end + device pci 03.0 on end # Mini-HD audio Audio controller + + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "gen1_dec" = "0x007c1601" + register "gen2_dec" = "0x000c15e1" + register "gen3_dec" = "0x00040291" + register "gen4_dec" = "0x000c06a1" + register "gpi13_routing" = "2" + register "gpi1_routing" = "2" + register "pirqa_routing" = "0x8b" + register "pirqb_routing" = "0x8a" + register "pirqc_routing" = "0x87" + register "pirqd_routing" = "0x86" + register "pirqe_routing" = "0x8b" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x8a" + register "pirqh_routing" = "0x89" + register "sata_ahci" = "1" + register "sata_port_map" = "0x21" + device pci 14.0 on end # xHCI Controller + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 on end # Management Engine KT + device pci 19.0 on # Intel Gigabit Ethernet Unsupported PCI device 8086:153a + subsystemid 0x17aa 0x2210 + end + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1f.0 on # LPC bridge PCI-LPC bridge + chip ec/lenovo/pmh7 + register "backlight_enable" = "0x01" + register "dock_event_enable" = "0x01" + device pnp ff.1 on end # dummy + end + chip ec/lenovo/h8 # FIXME: has_keyboard_backlight, has_power_management_beeps, has_uwb + register "beepmask0" = "0x00" + register "beepmask1" = "0x86" + register "config0" = "0xa6" + register "config1" = "0x05" + register "config2" = "0xa8" + register "config3" = "0xc4" + register "event2_enable" = "0xff" + register "event3_enable" = "0xff" + register "event4_enable" = "0xd0" + register "event5_enable" = "0x3c" + register "event7_enable" = "0x81" + register "event8_enable" = "0x7b" + register "event9_enable" = "0xff" + register "eventb_enable" = "0x08" + register "eventc_enable" = "0xff" + register "eventd_enable" = "0xff" + register "evente_enable" = "0x9d" + device pnp ff.2 on # dummy + io 0x60 = 0x62 + io 0x62 = 0x66 + io 0x64 = 0x1600 + io 0x66 = 0x1604 + end + end + end + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on # SMBus + chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip + device i2c 54 on end + device i2c 55 on end + device i2c 56 on end + device i2c 57 on end + device i2c 5c on end + device i2c 5d on end + device i2c 5e on end + device i2c 5f on end + end + end + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/lenovo/w541/dsdt.asl b/src/mainboard/lenovo/w541/dsdt.asl new file mode 100644 index 0000000..69cd416 --- /dev/null +++ b/src/mainboard/lenovo/w541/dsdt.asl @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Iru Cai <mytbk920423(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +#define EC_LENOVO_H8_ME_WORKAROUND 1 +#define THINKPAD_EC_GPE 17 + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI 2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/haswell.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } +} diff --git a/src/mainboard/lenovo/w541/gma-mainboard.ads b/src/mainboard/lenovo/w541/gma-mainboard.ads new file mode 100644 index 0000000..d7afe73 --- /dev/null +++ b/src/mainboard/lenovo/w541/gma-mainboard.ads @@ -0,0 +1,34 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + Internal); + +end GMA.Mainboard; diff --git a/src/mainboard/lenovo/w541/gpio.c b/src/mainboard/lenovo/w541/gpio.c new file mode 100644 index 0000000..23d4cdb --- /dev/null +++ b/src/mainboard/lenovo/w541/gpio.c @@ -0,0 +1,205 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_OUTPUT, + .gpio4 = GPIO_DIR_OUTPUT, + .gpio5 = GPIO_DIR_OUTPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio3 = GPIO_LEVEL_LOW, + .gpio4 = GPIO_LEVEL_LOW, + .gpio5 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_LOW, + .gpio19 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_LOW, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/lenovo/w541/hda_verb.c b/src/mainboard/lenovo/w541/hda_verb.c new file mode 100644 index 0000000..6c9c43c --- /dev/null +++ b/src/mainboard/lenovo/w541/hda_verb.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0292, /* Codec Vendor / Device ID: Realtek */ + 0x17aa2211, /* Subsystem ID */ + 12, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x17aa2211), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x0321101f), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x03a11020), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40738105), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/w541/mainboard.c b/src/mainboard/lenovo/w541/mainboard.c new file mode 100644 index 0000000..c53471b --- /dev/null +++ b/src/mainboard/lenovo/w541/mainboard.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Iru Cai <mytbk920423(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <ec/lenovo/h8/h8.h> + +static void mainboard_enable(struct device *dev) +{ + /* FIXME: fix those values*/ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/lenovo/w541/romstage.c b/src/mainboard/lenovo/w541/romstage.c new file mode 100644 index 0000000..eb95283 --- /dev/null +++ b/src/mainboard/lenovo/w541/romstage.c @@ -0,0 +1,104 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <arch/romstage.h> +#include <cpu/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/pei_data.h> +#include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/lynxpoint/pch.h> + +static const struct rcba_config_instruction rcba_config[] = { + RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D29IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D28IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D27IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D26IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D25IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D20IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + + RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), + + RCBA_END_CONFIG, +}; + +void mainboard_config_superio(void) +{ +} + +void mainboard_romstage_entry(void) +{ + struct pei_data pei_data = { + .pei_version = PEI_VERSION, + .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = HPET_ADDR, + .rcba = (uintptr_t)DEFAULT_RCBA, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .temp_mmio_base = 0xfed08000, + .system_type = 0, /* mobile */ + .tseg_size = CONFIG_SMM_TSEG_SIZE, + /* note that SPD addresses are left-shifted by 1. */ + .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, /* FIXME: check this */ + .ec_present = 0, + .gbe_enable = 0, /* FIXME: check this */ + .dimm_channel0_disabled = 0, /* FIXME: leave channel 0 enabled */ + .dimm_channel1_disabled = 0, /* FIXME: leave channel 1 enabled */ + .max_ddr3_freq = 1600, + .usb2_ports = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + }, + .usb3_ports = { + { 1, 0 }, + { 1, 0 }, + { 1, USB_OC_PIN_SKIP }, + { 1, USB_OC_PIN_SKIP }, + { 1, 1 }, + { 1, 1 }, + }, + }; + + struct romstage_params romstage_params = { + .pei_data = &pei_data, + .gpio_map = &mainboard_gpio_map, + .rcba_config = rcba_config, + }; + + romstage_common(&romstage_params); +} diff --git a/src/mainboard/lenovo/w541/smihandler.c b/src/mainboard/lenovo/w541/smihandler.c new file mode 100644 index 0000000..29bf797 --- /dev/null +++ b/src/mainboard/lenovo/w541/smihandler.c @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <ec/acpi/ec.h> +#include <ec/lenovo/h8/h8.h> +#include <delay.h> +#include <southbridge/intel/lynxpoint/pch.h> + +#define GPE_EC_SCI 1 +/* FIXME: check this */ +#define GPE_EC_WAKE 13 + +static void mainboard_smi_handle_ec_sci(void) +{ + u8 status = inb(EC_SC); + u8 event; + + if (!(status & EC_SCI_EVT)) + return; + + event = ec_query(); + printk(BIOS_DEBUG, "EC event %02x\n", event); +} + +void mainboard_smi_gpi(u32 gpi_sts) +{ + if (gpi_sts & (1 << GPE_EC_SCI)) + mainboard_smi_handle_ec_sci(); +} + +int mainboard_smi_apmc(u8 data) +{ + switch (data) { + case APM_CNT_ACPI_ENABLE: + /* use 0x1600/0x1604 to prevent races with userspace */ + ec_set_ports(0x1604, 0x1600); + /* route EC_SCI to SCI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + case APM_CNT_ACPI_DISABLE: + /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't + provide a EC query function */ + ec_set_ports(0x66, 0x62); + /* route EC_SCI to SMI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + default: + break; + } + return 0; +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (slp_typ == 3) { + u8 ec_wake = ec_read(0x32); + /* If EC wake events are enabled, + * enable wake on EC WAKE GPE. */ + if (ec_wake & 0x14) { + /* Redirect EC WAKE GPE to SCI. */ + gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/38733 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I315627cba495bfc376321c632248e50734daac71 Gerrit-Change-Number: 38733 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] mainboard/acer: Add TravelMate X314
by Felix Singer (Code Review) 23 Apr '21

23 Apr '21

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35461 ) Change subject: [WIP] mainboard/acer: Add TravelMate X314 ...................................................................... [WIP] mainboard/acer: Add TravelMate X314 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Change-Id: Ia9a1c3492aa41ef20a4408cc91370b8f94adbe47 --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/travelmate-x314/Kconfig A src/mainboard/acer/travelmate-x314/Kconfig.name A src/mainboard/acer/travelmate-x314/acpi_tables.c A src/mainboard/acer/travelmate-x314/board_info.txt A src/mainboard/acer/travelmate-x314/devicetree.cb A src/mainboard/acer/travelmate-x314/dsdt.asl 8 files changed, 211 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/35461/1 diff --git a/src/mainboard/acer/Kconfig b/src/mainboard/acer/Kconfig new file mode 100644 index 0000000..28a2945 --- /dev/null +++ b/src/mainboard/acer/Kconfig @@ -0,0 +1,28 @@ +## +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +if VENDOR_ACER + +choice + prompt "Mainboard model" + +source "src/mainboard/acer/*/Kconfig.name" + +endchoice + +source "src/mainboard/acer/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "Acer" + +endif # VENDOR_ACER diff --git a/src/mainboard/acer/Kconfig.name b/src/mainboard/acer/Kconfig.name new file mode 100644 index 0000000..bb177f9 --- /dev/null +++ b/src/mainboard/acer/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_ACER + bool "Acer" diff --git a/src/mainboard/acer/travelmate-x314/Kconfig b/src/mainboard/acer/travelmate-x314/Kconfig new file mode 100644 index 0000000..8b71cbd --- /dev/null +++ b/src/mainboard/acer/travelmate-x314/Kconfig @@ -0,0 +1,70 @@ +if BOARD_ACER_TRAVELMATE_X314 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_SMI_HANDLER + select ONBOARD_VGA_IS_PRIMARY + select SOC_INTEL_WHISKEYLAKE +# select SPD_READ_BY_WORD + select SYSTEM_TYPE_LAPTOP + +config MAINBOARD_VENDOR + string + default "Acer" + +config MAINBOARD_FAMILY + string + default "TravelMate" + +config MAINBOARD_PART_NUMBER + string + default "X314" + +config MAINBOARD_VERSION + string + default "1.0" + +config MAINBOARD_DIR + string + default "acer/travelmate-x314" + +config SUBSYSTEM_VENDOR_ID + hex + default 0xdead + +config SUBSYSTEM_DEVICE_ID + hex + default 0xbeef + +config MAX_CPUS + int + default 8 + +config VGA_BIOS_ID + string + default "8086,3ea0" + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +config PXE_ROM_ID + string + default "dead,beef" + +config POST_DEVICE + bool + default n + +config CONSOLE_POST + bool + default y + +endif # BOARD_ACER_TRAVELMATE_X314 diff --git a/src/mainboard/acer/travelmate-x314/Kconfig.name b/src/mainboard/acer/travelmate-x314/Kconfig.name new file mode 100644 index 0000000..61b4b2c --- /dev/null +++ b/src/mainboard/acer/travelmate-x314/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ACER_TRAVELMATE_X314 + bool "TravelMate X314" diff --git a/src/mainboard/acer/travelmate-x314/acpi_tables.c b/src/mainboard/acer/travelmate-x314/acpi_tables.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/acer/travelmate-x314/acpi_tables.c diff --git a/src/mainboard/acer/travelmate-x314/board_info.txt b/src/mainboard/acer/travelmate-x314/board_info.txt new file mode 100644 index 0000000..92ee253 --- /dev/null +++ b/src/mainboard/acer/travelmate-x314/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: Acer +Board name: TravelMate X314 +Category: laptop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Release year: 2019 diff --git a/src/mainboard/acer/travelmate-x314/devicetree.cb b/src/mainboard/acer/travelmate-x314/devicetree.cb new file mode 100644 index 0000000..7c519b0 --- /dev/null +++ b/src/mainboard/acer/travelmate-x314/devicetree.cb @@ -0,0 +1,57 @@ +chip soc/intel/cannonlake + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA Thermal device + device pci 12.0 on end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.5 on end # SDCard + device pci 15.0 on end # I2C #0 + device pci 15.1 on end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on end # SATA + device pci 19.0 on end # I2C #4 + device pci 19.1 off end # I2C #5 + device pci 19.2 on end # UART #2 + device pci 1a.0 on end # eMMC + device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 + device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 off end # PCI Express Port 13 + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1e.0 on end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 on end # GbE + end +end diff --git a/src/mainboard/acer/travelmate-x314/dsdt.asl b/src/mainboard/acer/travelmate-x314/dsdt.asl new file mode 100644 index 0000000..daddd97 --- /dev/null +++ b/src/mainboard/acer/travelmate-x314/dsdt.asl @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2018 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/cannonlake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/cannonlake/acpi/globalnvs.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/cannonlake/acpi/northbridge.asl> + #include <soc/intel/cannonlake/acpi/southbridge.asl> + } + } + + // Chipset specific sleep states + #include <soc/intel/cannonlake/acpi/sleepstates.asl> +} -- To view, visit https://review.coreboot.org/c/coreboot/+/35461 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9a1c3492aa41ef20a4408cc91370b8f94adbe47 Gerrit-Change-Number: 35461 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/systemagent: Add new PCIEXBAR register LENGTH offset...
by Usha P (Code Review) 22 Apr '21

22 Apr '21

Usha P has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40363 ) Change subject: soc/intel/common/systemagent: Add new PCIEXBAR register LENGTH offset values ...................................................................... soc/intel/common/systemagent: Add new PCIEXBAR register LENGTH offset values Add PCIEXBAR register LENGTH offset values to accommodate new SoC implementation. Changes: 1. The major delta is 0x60:PCIEXBAR register LENGTH offset definition has been changed for latest SoC. 2. Common code takes care of setting the right value for pciex length. TEST=Able to build CNL, SKL, APL platforms. Change-Id: I75619be7614f58c96670ef86485d49d4da06ad91 Signed-off-by: Usha P <usha.p(a)intel.com> --- M src/soc/intel/common/block/systemagent/Kconfig M src/soc/intel/common/block/systemagent/systemagent_def.h M src/soc/intel/common/block/systemagent/systemagent_early.c 3 files changed, 44 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/40363/1 diff --git a/src/soc/intel/common/block/systemagent/Kconfig b/src/soc/intel/common/block/systemagent/Kconfig index 6d88cbc..db0cdbd 100644 --- a/src/soc/intel/common/block/systemagent/Kconfig +++ b/src/soc/intel/common/block/systemagent/Kconfig @@ -11,12 +11,28 @@ config SA_PCIEX_LENGTH_MIB hex - default 0x10000000 if (PCIEX_LENGTH_256MB) - default 0x8000000 if (PCIEX_LENGTH_128MB) - default 0x4000000 if (PCIEX_LENGTH_64MB) - default 0x10000000 + default 0x1000 if (PCIEX_LENGTH_4096MB) + default 0x800 if (PCIEX_LENGTH_2048MB) + default 0x400 if (PCIEX_LENGTH_1024MB) + default 0x200 if (PCIEX_LENGTH_512MB) + default 0x100 if (PCIEX_LENGTH_256MB) + default 0x80 if (PCIEX_LENGTH_128MB) + default 0x40 if (PCIEX_LENGTH_64MB) + default 0x100 help - This option allows you to select length of PCIEX region. + This option allows you to select length of PCIEX region in MiB. + +config PCIEX_LENGTH_4096MB + bool + +config PCIEX_LENGTH_2048MB + bool + +config PCIEX_LENGTH_1024MB + bool + +config PCIEX_LENGTH_512MB + bool config PCIEX_LENGTH_256MB bool diff --git a/src/soc/intel/common/block/systemagent/systemagent_def.h b/src/soc/intel/common/block/systemagent/systemagent_def.h index 03f4de4..91595c2 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_def.h +++ b/src/soc/intel/common/block/systemagent/systemagent_def.h @@ -19,6 +19,10 @@ #define DPR_PRS (1 << 1) #define DPR_SIZE_MASK 0xff0 +#define PCIEXBAR_LENGTH_4096MB 6 +#define PCIEXBAR_LENGTH_2048MB 5 +#define PCIEXBAR_LENGTH_1024MB 4 +#define PCIEXBAR_LENGTH_512MB 3 #define PCIEXBAR_LENGTH_64MB 2 #define PCIEXBAR_LENGTH_128MB 1 #define PCIEXBAR_LENGTH_256MB 0 diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index 79a6628..ff806ac 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -28,13 +28,29 @@ /* Get PCI Express Region Length */ switch (CONFIG_SA_PCIEX_LENGTH_MIB) { - case 256 * MiB: + /* + * Length of PCIEXBAR region would be more than 256MB if + * PCIEXBAR.LENGTH width is 3. + */ + case 4096: + pciexbar_length = PCIEXBAR_LENGTH_4096MB; + break; + case 2048: + pciexbar_length = PCIEXBAR_LENGTH_2048MB; + break; + case 1024: + pciexbar_length = PCIEXBAR_LENGTH_1024MB; + break; + case 512: + pciexbar_length = PCIEXBAR_LENGTH_512MB; + break; + case 256: pciexbar_length = PCIEXBAR_LENGTH_256MB; break; - case 128 * MiB: + case 128: pciexbar_length = PCIEXBAR_LENGTH_128MB; break; - case 64 * MiB: + case 64: pciexbar_length = PCIEXBAR_LENGTH_64MB; break; default: -- To view, visit https://review.coreboot.org/c/coreboot/+/40363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75619be7614f58c96670ef86485d49d4da06ad91 Gerrit-Change-Number: 40363 Gerrit-PatchSet: 1 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-MessageType: newchange

5 12

Change in coreboot[master]: soc/intel/skylake: lock TCO base address on pch finalize
by Michael Niewöhner (Code Review) 21 Apr '21

21 Apr '21

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35525 ) Change subject: soc/intel/skylake: lock TCO base address on pch finalize ...................................................................... soc/intel/skylake: lock TCO base address on pch finalize This is a follow-up on I5bd95b3580adc0f4cffa667f8979b7cf08925720 which already locks TCO itself but does not lock the base address. Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: Idab9419487e6e4cbdecd2efaa4772ff4960c9055 --- M src/soc/intel/common/block/smbus/tco.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/35525/1 diff --git a/src/soc/intel/common/block/smbus/tco.c b/src/soc/intel/common/block/smbus/tco.c index 1a215eb..a3ebe24 100644 --- a/src/soc/intel/common/block/smbus/tco.c +++ b/src/soc/intel/common/block/smbus/tco.c @@ -34,6 +34,7 @@ #define TCOBASE 0x50 #define TCOCTL 0x54 #define TCO_BASE_EN (1 << 8) +#define TCO_BASE_LOCK (1 << 0) /* Get base address of TCO I/O registers. */ static uint16_t tco_get_bar(void) @@ -61,8 +62,13 @@ void tco_lockdown(void) { + uint32_t reg32; uint16_t tcocnt; + /* TCO base address lockdown */ + reg32 = pci_read_config32(dev, TCOCTL); + pci_write_config32(dev, TCOCTL, reg32 | TCO_BASE_LOCK); + /* TCO Lock down */ tcocnt = tco_read_reg(TCO1_CNT); tcocnt |= TCO_LOCK; -- To view, visit https://review.coreboot.org/c/coreboot/+/35525 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idab9419487e6e4cbdecd2efaa4772ff4960c9055 Gerrit-Change-Number: 35525 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-MessageType: newchange

5 12

Change in coreboot[master]: [WIP]acpi: Get rid of boilerplate FADT
by Patrick Rudolph (Code Review) 19 Apr '21

19 Apr '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40036 ) Change subject: [WIP]acpi: Get rid of boilerplate FADT ...................................................................... [WIP]acpi: Get rid of boilerplate FADT Still not done.... Needs test on windows and Linux on all affected platforms, that is every x86 platform. Change-Id: If58fcf9a1c39c159dfa08339cb931e552d499747 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/acpi.c M src/arch/x86/include/arch/acpi.h M src/soc/intel/apollolake/acpi.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/skylake/acpi.c M src/soc/intel/xeon_sp/cpx/acpi.c M src/soc/intel/xeon_sp/skx/acpi.c M src/southbridge/amd/cimx/sb800/fadt.c M src/southbridge/amd/pi/hudson/fadt.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/i82371eb/fadt.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 17 files changed, 407 insertions(+), 1,080 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/40036/1 diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index e4932be..d540721 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -1249,6 +1249,17 @@ fadt->sleep_control_reg.bit_width = 8; fadt->sleep_status_reg.bit_width = 8; + if (CONFIG(ARCH_X86)) { + /* Set x86 defaults. A SoC can still overwrite those. */ + fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->reset_reg.addrl = SYS_RESET; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = RST_CPU | SYS_RST; + } acpi_fill_fadt(fadt); header->checksum = @@ -1256,6 +1267,130 @@ } #endif +static void acpi_update_access_size(acpi_addr_t *reg) +{ + switch (DIV_ROUND_UP(reg->bit_width, 8)) { + case 0: + reg->access_size = ACPI_ACCESS_SIZE_UNDEFINED; + default: + case 1: + reg->access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + break; + case 2: + reg->access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + break; + case 4: + reg->access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + break; + case 8: + reg->access_size = ACPI_ACCESS_SIZE_QDWORD_ACCESS; + break; + } +} + +void acpi_fill_fadt_x86_pm(acpi_fadt_t *fadt, + u32 pm1a_evt_blk, + u32 pm1b_evt_blk, + u32 pm1a_cnt_blk, + u32 pm1b_cnt_blk, + u32 pm2_cnt_blk, + u32 pm_tmr_blk, + u32 gpe0_blk, + u32 gpe1_blk, + u8 pm1_evt_len, + u8 pm1_cnt_len, + u8 pm2_cnt_len, + u8 pm_tmr_len, + u8 gpe0_blk_len, + u8 gpe1_blk_len, + u8 gpe1_base) +{ + fadt->pm1a_evt_blk = pm1a_evt_blk; + fadt->pm1b_evt_blk = pm1b_evt_blk; + fadt->pm1a_cnt_blk = pm1a_cnt_blk; + fadt->pm1b_cnt_blk = pm1b_cnt_blk; + fadt->pm2_cnt_blk = pm2_cnt_blk; + fadt->pm_tmr_blk = pm_tmr_blk; + fadt->gpe0_blk = gpe0_blk; + fadt->gpe1_blk = gpe1_blk; + fadt->gpe1_base = gpe1_base; + + fadt->pm1_evt_len = pm1_evt_len; + fadt->pm1_cnt_len = pm1_cnt_len; + fadt->pm2_cnt_len = pm2_cnt_len; + fadt->pm_tmr_len = pm_tmr_len; + fadt->gpe0_blk_len = gpe0_blk_len; + fadt->gpe1_blk_len = gpe1_blk_len; + + fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_evt_blk.addrl = pm1a_evt_blk; + fadt->x_pm1a_evt_blk.addrh = 0x0; + acpi_update_access_size(&fadt->x_pm1a_evt_blk); + + fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1b_evt_blk.bit_width = pm1_evt_len * 8; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1b_evt_blk.addrl = pm1b_evt_blk; + fadt->x_pm1b_evt_blk.addrh = 0x0; + acpi_update_access_size(&fadt->x_pm1b_evt_blk); + + fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1a_cnt_blk.bit_width = pm1_cnt_len * 8; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_cnt_blk.addrl = pm1a_cnt_blk; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + acpi_update_access_size(&fadt->x_pm1a_cnt_blk); + + fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1b_cnt_blk.bit_width = pm1_cnt_len * 8; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1b_cnt_blk.addrl = pm1b_cnt_blk; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + acpi_update_access_size(&fadt->x_pm1b_cnt_blk); + + fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm2_cnt_blk.bit_width = pm2_cnt_len * 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_pm2_cnt_blk.addrl = pm2_cnt_blk; + fadt->x_pm2_cnt_blk.addrh = 0x0; + acpi_update_access_size(&fadt->x_pm2_cnt_blk); + + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm_tmr_blk.bit_width = pm_tmr_len * 8; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm_tmr_blk.addrl = pm_tmr_blk; + fadt->x_pm_tmr_blk.addrh = 0x0; + acpi_update_access_size(&fadt->x_pm_tmr_blk); + + /* + * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5. + * The bit_width field intentionally overflows here. + * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which + * seems to work fine on Linux 5.0 and Windows 10. + */ + fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe0_blk.bit_width = gpe0_blk_len * 8; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_gpe0_blk.addrl = gpe0_blk; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe1_blk.bit_width = gpe1_blk_len * 8; + fadt->x_gpe1_blk.bit_offset = gpe1_base * 8; + fadt->x_gpe1_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_gpe1_blk.addrl = gpe1_blk; + fadt->x_gpe1_blk.addrh = 0x0; +} + unsigned long __weak fw_cfg_acpi_tables(unsigned long start) { return 0; diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 4351678..107ad86 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -844,6 +844,25 @@ #if CONFIG(COMMON_FADT) void acpi_fill_fadt(acpi_fadt_t *fadt); #endif +/** + * Fill in ACPI FADT fields used by a generic x86 platform. + * That is all PM* and GPE* are located in IO space. + */ +void acpi_fill_fadt_x86_pm(acpi_fadt_t *fadt, + u32 pm1a_evt_blk, + u32 pm1b_evt_blk, + u32 pm1a_cnt_blk, + u32 pm1b_cnt_blk, + u32 pm2_cnt_blk, + u32 pm_tmr_blk, + u32 gpe0_blk, + u32 gpe1_blk, + u8 pm1_evt_len, + u8 pm1_cnt_len, + u8 pm2_cnt_len, + u8 pm_tmr_len, + u8 gpe0_blk_len, + u8 gpe1_blk_len); void update_ssdt(void *ssdt); void update_ssdtx(void *ssdtx, int i); diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index fbfe33f..ef1c01d 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -152,10 +152,9 @@ void soc_fill_fadt(acpi_fadt_t *fadt) { const struct soc_intel_apollolake_config *cfg; + const uint16_t pmbase = ACPI_BASE_ADDRESS; cfg = config_of_soc(); - fadt->pm_tmr_blk = ACPI_BASE_ADDRESS + PM1_TMR; - fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; @@ -164,13 +163,25 @@ fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; - fadt->x_pm_tmr_blk.addrl = ACPI_BASE_ADDRESS + PM1_TMR; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - if (cfg->lpss_s0ix_enable) fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; + + acpi_fill_fadt_x86_pm(fadt, + pmbase + PM1_STS, + 0, + pmbase + PM1_CNT, + 0, + 0, + pmbase + PM1_TMR, + pmbase + GPE0_STS(0), + 0, + 4, + 2, + 0, + 4, + 2 * GPE0_REG_MAX, + 0, + 0); } static unsigned long soc_fill_dmar(unsigned long current) diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 84659c9..490cabc 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -176,17 +176,25 @@ const struct soc_intel_cannonlake_config *config; config = config_of_soc(); - fadt->pm_tmr_blk = pmbase + PM1_TMR; - fadt->pm_tmr_len = 4; - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; - fadt->x_pm_tmr_blk.addrh = 0x0; - if (config->s0ix_enable) fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; + + acpi_fill_fadt_x86_pm(fadt, + pmbase + PM1_STS, + 0, + pmbase + PM1_CNT, + 0, + 0, + pmbase + PM1_TMR, + pmbase + GPE0_STS(0), + 0, + 4, + 2, + 0, + 4, + 2 * GPE0_REG_MAX, + 0, + 0); } uint32_t soc_read_sci_irq_select(void) { diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index fe127a2..c729cc8 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -178,6 +178,17 @@ fadt->x_gpe1_blk.space_id = 1; + + fadt->pm1a_evt_blk = pmbase + PM1_STS; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + PM1_CNT; + fadt->pm1b_cnt_blk = 0x0; + + fadt->gpe0_blk = pmbase + GPE0_STS(0); + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + soc_fill_fadt(fadt); } diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index d3e2853..fd8b934 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -132,7 +132,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) { - u16 pmbase = get_pmbase(); + const u16 pmbase = get_pmbase(); /* System Management */ if (!CONFIG(HAVE_SMI_HANDLER)) { @@ -141,17 +141,6 @@ fadt->acpi_disable = 0x00; } - /* Power Control */ - fadt->pm2_cnt_blk = pmbase + PM2_CNT; - fadt->pm_tmr_blk = pmbase + PM1_TMR; - fadt->gpe1_blk = 0; - - /* Control Registers - Length */ - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 8; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; fadt->cst_cnt = 0; fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; @@ -171,75 +160,22 @@ ACPI_FADT_RESET_REGISTER | ACPI_FADT_SLEEP_TYPE | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - /* Reset Register */ - fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xCF9; - fadt->reset_reg.addrh = 0x00; - fadt->reset_value = 6; - - /* PM1 Status & PM1 Enable */ - fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk; - fadt->x_pm1a_evt_blk.addrh = 0x00; - - fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk; - fadt->x_pm1b_evt_blk.addrh = 0x00; - - /* PM1 Control Registers */ - fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; - fadt->x_pm1a_cnt_blk.addrh = 0x00; - - fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk; - fadt->x_pm1b_cnt_blk.addrh = 0x00; - - /* PM2 Control Registers */ - fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk; - fadt->x_pm2_cnt_blk.addrh = 0x00; - - /* PM1 Timer Register */ - fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; - fadt->x_pm_tmr_blk.addrh = 0x00; - - /* General-Purpose Event Registers */ - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + EventEnable */ - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0x00; - - fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; - fadt->x_gpe1_blk.addrh = 0x00; + acpi_fill_fadt_x86_pm(fadt, + pmbase + PM1_STS, + 0, + pmbase + PM1_CNT, + 0, + pmbase + PM2_CNT, + pmbase + PM1_TMR, + pmbase + GPE0_STS(0), + 0, + 4, + 2, + 1, + 4, + 2 * GPE0_REG_MAX * sizeof(uint32_t), + 0, + 0); motherboard_fill_fadt(fadt); } diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 550dd56..9e24017 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -234,8 +234,6 @@ const uint16_t pmbase = ACPI_BASE_ADDRESS; config_t *config = config_of_soc(); - fadt->header.revision = get_acpi_table_revision(FADT); - fadt->sci_int = acpi_sci_irq(); fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; @@ -243,23 +241,6 @@ fadt->s4bios_req = 0x0; fadt->pstate_cnt = 0; - fadt->pm1a_evt_blk = pmbase + PM1_STS; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + PM1_CNT; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + PM2_CNT; - fadt->pm_tmr_blk = pmbase + PM1_TMR; - fadt->gpe0_blk = pmbase + GPE0_STS(0); - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - /* There are 4 GPE0 STS/EN pairs each 32 bits wide. */ - fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; fadt->cst_cnt = 0; fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = 87; @@ -282,75 +263,22 @@ if (config->s0ix_enable) fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - fadt->reset_value = 6; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; - fadt->x_pm_tmr_blk.addrh = 0x0; - - /* - * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5. - * The bit_width field intentionally overflows here. - * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which - * seems to work fine on Linux 5.0 and Windows 10. - */ - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; + acpi_fill_fadt_x86_pm(fadt, + pmbase + PM1_STS, + 0, + pmbase + PM1_CNT, + 0, + pmbase + PM2_CNT, + pmbase + PM1_TMR, + pmbase + GPE0_STS(0), + 0, + 4, + 2, + 1, + 4, + 2 * GPE0_REG_MAX * sizeof(uint32_t), + 0, + 0); } static void write_c_state_entries(acpi_cstate_t *map, const int *set, size_t max_c_state) diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index 48ad374..1688ae3 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -108,19 +108,6 @@ fadt->header.revision = get_acpi_table_revision(FADT); fadt->sci_int = SCI_INT_NUM; - fadt->pm1a_evt_blk = pmbase + PM1_STS; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + PM1_CNT; - fadt->pm1b_cnt_blk = 0x0; - - fadt->gpe0_blk = pmbase + GPE0_STS(0); - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - - /* GPE0 STS/EN pairs each 32 bits wide. */ - fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); - fadt->flush_size = 0x400; /* twice of cache size */ fadt->flush_stride = 0x10; /* Cache line width */ fadt->duty_offset = 1; @@ -129,26 +116,6 @@ fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_RESET_REGISTER | ACPI_FADT_PLATFORM_CLOCK; - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.addrl = RST_CNT; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_value = RST_CPU | SYS_RST; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; - fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; - - fadt->x_pm1b_evt_blk.space_id = 1; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; - fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; - - fadt->x_pm1b_cnt_blk.space_id = 1; - - fadt->x_gpe1_blk.space_id = 1; - if (CONFIG(HAVE_SMI_HANDLER)) { fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; @@ -165,18 +132,19 @@ fadt->cst_cnt = 0; } - /* General-Purpose Event Registers */ - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + EventEnable */ - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0; - - fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = 0; - fadt->x_gpe1_blk.addrh = 0; + acpi_fill_fadt_x86_pm(fadt, + pmbase + PM1_STS, + 0, + pmbase + PM1_CNT, + 0, + 0, + 0, + pmbase + GPE0_STS(0), + 0, + 4, + 2, + 0, + 0, + 2 * GPE0_REG_MAX * sizeof(uint32_t), + 0); } diff --git a/src/soc/intel/xeon_sp/skx/acpi.c b/src/soc/intel/xeon_sp/skx/acpi.c index e9edc99..aab93b4 100644 --- a/src/soc/intel/xeon_sp/skx/acpi.c +++ b/src/soc/intel/xeon_sp/skx/acpi.c @@ -247,18 +247,6 @@ fadt->acpi_disable = 0x00; } - /* Power Control */ - fadt->pm2_cnt_blk = pmbase + PM2_CNT; - fadt->pm_tmr_blk = pmbase + PM1_TMR; - fadt->gpe1_blk = 0; - - /* Control Registers - Length */ - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - /* There are 4 GPE0 STS/EN pairs each 32 bits wide. */ - fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; fadt->cst_cnt = 0; fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; @@ -278,75 +266,21 @@ ACPI_FADT_RESET_REGISTER | ACPI_FADT_SLEEP_TYPE | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - /* Reset Register */ - fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xCF9; - fadt->reset_reg.addrh = 0x00; - fadt->reset_value = 6; - - /* PM1 Status & PM1 Enable */ - fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk; - fadt->x_pm1a_evt_blk.addrh = 0x00; - - fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk; - fadt->x_pm1b_evt_blk.addrh = 0x00; - - /* PM1 Control Registers */ - fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; - fadt->x_pm1a_cnt_blk.addrh = 0x00; - - fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk; - fadt->x_pm1b_cnt_blk.addrh = 0x00; - - /* PM2 Control Registers */ - fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk; - fadt->x_pm2_cnt_blk.addrh = 0x00; - - /* PM1 Timer Register */ - fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; - fadt->x_pm_tmr_blk.addrh = 0x00; - - /* General-Purpose Event Registers */ - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + EventEnable */ - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0x00; - - fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; - fadt->x_gpe1_blk.addrh = 0x00; + acpi_fill_fadt_x86_pm(fadt, + pmbase + PM1_STS, + 0, + pmbase + PM1_CNT, + 0, + pmbase + PM2_CNT, + pmbase + PM1_TMR, + pmbase + GPE0_STS(0), + 0, + 4, + 2, + 1, + 4, + 2 * GPE0_REG_MAX * sizeof(uint32_t), + 0); motherboard_fill_fadt(fadt); } @@ -355,8 +289,6 @@ { const uint16_t pmbase = ACPI_BASE_ADDRESS; - fadt->header.revision = get_acpi_table_revision(FADT); - fadt->sci_int = acpi_sci_irq(); /* TODO: enabled SMM mode switch when SMM handlers are set up. @@ -370,23 +302,6 @@ fadt->s4bios_req = 0x0; fadt->pstate_cnt = 0; - fadt->pm1a_evt_blk = pmbase + PM1_STS; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + PM1_CNT; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + PM2_CNT; - fadt->pm_tmr_blk = pmbase + PM1_TMR; - fadt->gpe0_blk = pmbase + GPE0_STS(0); - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - /* There are 4 GPE0 STS/EN pairs each 32 bits wide. */ - fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; fadt->cst_cnt = 0; fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = 87; @@ -406,69 +321,21 @@ ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - fadt->reset_value = 6; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; + acpi_fill_fadt_x86_pm(fadt, + pmbase + PM1_STS, + 0, + pmbase + PM1_CNT, + 0, + pmbase + PM2_CNT, + pmbase + PM1_TMR, + pmbase + GPE0_STS(0), + 0, + 4, + 2, + 1, + 4, + 2 * GPE0_REG_MAX * sizeof(uint32_t), + 0); soc_fill_fadt(fadt); } diff --git a/src/southbridge/amd/cimx/sb800/fadt.c b/src/southbridge/amd/cimx/sb800/fadt.c index 08fbecb..5b3fee6 100644 --- a/src/southbridge/amd/cimx/sb800/fadt.c +++ b/src/southbridge/amd/cimx/sb800/fadt.c @@ -104,22 +104,6 @@ /* RTC_En_En, TMR_En_En, GBL_EN_EN */ outl(0x1, PM1_CNT_BLK_ADDRESS); /* set SCI_EN */ - fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS; - fadt->pm1b_evt_blk = 0x0000; - fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS; - fadt->pm1b_cnt_blk = 0x0000; - fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS; - fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS; - fadt->gpe0_blk = GPE0_BLK_ADDRESS; - fadt->gpe1_blk = 0; /* No gpe1 block in hudson1 */ - - fadt->pm1_evt_len = 4; /* 32 bits */ - fadt->pm1_cnt_len = 2; /* 16 bits */ - fadt->pm2_cnt_len = 1; /* 8 bits */ - fadt->pm_tmr_len = 4; /* 32 bits */ - fadt->gpe0_blk_len = 8; /* 64 bits */ - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; fadt->cst_cnt = 0x00; /* unused if SMI_CMD = 0 */ fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; @@ -143,17 +127,6 @@ ACPI_FADT_S4_RTC_VALID | ACPI_FADT_REMOTE_POWER_ON; - /* Format is from 5.2.3.1: Generic Address Structure */ - /* reset_reg: see section 4.7.3.6 ACPI 3.0a spec */ - /* 8 bit write of value 0x06 to 0xCF9 in IO space */ - fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0x0; - fadt->reset_value = 6; - fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */ fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */ @@ -162,66 +135,22 @@ fadt->x_dsdt_l = ((uintptr_t)dsdt) & 0xffffffff; fadt->x_dsdt_h = ((uint64_t)(uintptr_t)dsdt) >> 32; - fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - - fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = 0; - fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - - fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm2_cnt_blk.bit_width = 8; /* Hudson 1 Pm2Control is 8 bits */ - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - - fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS; - fadt->x_pm_tmr_blk.addrh = 0x0; - - - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */ - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS; - fadt->x_gpe0_blk.addrh = 0x0; - - - fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = 0; - fadt->x_gpe1_blk.addrh = 0x0; + acpi_fill_fadt_x86_pm(fadt, + PM1_EVT_BLK_ADDRESS, + 0x0000, + PM1_CNT_BLK_ADDRESS, + 0x0000, + ACPI_PMA_CNT_BLK_ADDRESS, + PM1_TMR_BLK_ADDRESS, + GPE0_BLK_ADDRESS, + 0, + 4, + 2, + 1, + 4, + 2 * sizeof(uint32_t), + 0, + 0); header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); diff --git a/src/southbridge/amd/pi/hudson/fadt.c b/src/southbridge/amd/pi/hudson/fadt.c index 8573c8b..b7192f9 100644 --- a/src/southbridge/amd/pi/hudson/fadt.c +++ b/src/southbridge/amd/pi/hudson/fadt.c @@ -77,23 +77,6 @@ fadt->cst_cnt = 0x00; /* unused if SMI_CMD = 0 */ } - fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; - fadt->pm1b_evt_blk = 0x0000; - fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; - fadt->pm1b_cnt_blk = 0x0000; - fadt->pm2_cnt_blk = 0x0000; - fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; - fadt->gpe0_blk = ACPI_GPE0_BLK; - fadt->gpe1_blk = 0x0000; /* No gpe1 block in hudson */ - - fadt->pm1_evt_len = 4; /* 32 bits */ - fadt->pm1_cnt_len = 2; /* 16 bits */ - fadt->pm2_cnt_len = 0; - fadt->pm_tmr_len = 4; /* 32 bits */ - fadt->gpe0_blk_len = 8; /* 64 bits */ - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */ @@ -116,89 +99,31 @@ ACPI_FADT_S4_RTC_VALID | ACPI_FADT_REMOTE_POWER_ON; - /* Format is from 5.2.3.1: Generic Address Structure */ - /* reset_reg: see section 4.7.3.6 ACPI 3.0a spec */ - /* 8 bit write of value 0x06 to 0xCF9 in IO space */ - fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0x0; - - fadt->reset_value = 6; - - fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */ - fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */ - fadt->x_firmware_ctl_l = 0; /* set to 0 if firmware_ctrl is used */ fadt->x_firmware_ctl_h = 0; fadt->x_dsdt_l = (u32) dsdt; fadt->x_dsdt_h = 0; - fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - - fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = 0; - fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - /* * Note: Under this current AMD C state implementation, this is no longer * used and should not be reported to OS. */ - fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm2_cnt_blk.bit_width = 0; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = 0; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - - fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK; - fadt->x_pm_tmr_blk.addrh = 0x0; - - - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */ - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK; - fadt->x_gpe0_blk.addrh = 0x0; - - - fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = 0; - fadt->x_gpe1_blk.addrh = 0x0; + acpi_fill_fadt_x86_pm(fadt, + ACPI_PM_EVT_BLK, + 0x0000, + ACPI_PM1_CNT_BLK, + 0x0000, + 0x0000, + ACPI_PM_TMR_BLK, + ACPI_GPE0_BLK, + 0x0000, + 4, + 2, + 0, + 4, + 2 * sizeof(uint32_t), + 0, + 0); header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); } diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 46ab5fc..9aec7db 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -717,22 +717,6 @@ fadt->s4bios_req = 0x0; fadt->pstate_cnt = 0; - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 16; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; fadt->cst_cnt = 0; c2_latency = chip->c2_latency; if (!c2_latency) { @@ -765,70 +749,22 @@ fadt->flags |= ACPI_FADT_C2_MP_SUPPORTED; } - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 128; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; + acpi_fill_fadt_x86_pm(fadt, + pmbase, + 0x0, + pmbase + 0x4, + 0x0, + pmbase + 0x50, + pmbase + 0x8, + pmbase + 0x20, + 0, + 4, + 2, + 1, + 4, + 2 * 2 * sizeof(uint32_t), + 0, + 0); } static const char *lpc_acpi_name(const struct device *dev) diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index db1071a..4b27b97 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -52,25 +52,6 @@ fadt->s4bios_req = 0x0; fadt->pstate_cnt = 0x0; - fadt->pm1a_evt_blk = DEFAULT_PMBASE; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = DEFAULT_PMBASE + PMCNTRL; - fadt->pm1b_cnt_blk = 0x0; - - fadt->pm2_cnt_blk = 0; - fadt->pm_tmr_blk = DEFAULT_PMBASE + PMTMR; - fadt->gpe0_blk = DEFAULT_PMBASE + GPSTS; - fadt->gpe1_blk = 0x0; - fadt->gpe1_base = 0; - fadt->gpe1_blk_len = 0; - - /* *_len define register width in bytes */ - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 0; /* not supported */ - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 4; - fadt->cst_cnt = 0; /* smi command to indicate c state changed notification */ fadt->p_lvl2_lat = 101; /* >100 means c2 not supported */ fadt->p_lvl3_lat = 1001; /* >1000 means c3 not supported */ @@ -141,74 +122,22 @@ */ fadt->flags = 0xa5; - fadt->reset_reg.space_id = 0; - fadt->reset_reg.bit_width = 0; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = 0; - fadt->reset_reg.addrl = 0x0; - fadt->reset_reg.addrh = 0x0; - fadt->reset_value = 0; - - fadt->x_firmware_ctl_l = (uintptr_t)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (uintptr_t)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = fadt->pm1_evt_len * 8; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = 0; - fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; - fadt->x_gpe1_blk.addrh = 0x0; + acpi_fill_fadt_x86_pm(fadt, + DEFAULT_PMBASE, + 0, + DEFAULT_PMBASE + PMCNTRL, + 0, + 0, + DEFAULT_PMBASE + PMTMR, + DEFAULT_PMBASE + GPSTS, + 0, + 4, + 2, + 0, + 4, + 2 * sizeof(uint16_t), + 0, + 0); header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); } diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 743dbba..8977228 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -452,87 +452,6 @@ config_t *chip = dev->chip_info; u16 pmbase = lpc_get_pmbase(); - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + PM1_CNT; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + PM2_CNT; - fadt->pm_tmr_blk = pmbase + PM1_TMR; - fadt->gpe0_blk = pmbase + GPE0_STS; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 8; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 0; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 0; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 64; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = pmbase + GPE0_STS; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 0; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; fadt->day_alrm = 0xd; fadt->mon_alrm = 0x00; fadt->century = 0x32; @@ -562,6 +481,23 @@ | ACPI_FADT_C2_MP_SUPPORTED); if (chip->docking_supported) fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; + + acpi_fill_fadt_x86_pm(fadt, + pmbase, + 0, + pmbase + PM1_CNT, + 0, + pmbase + PM2_CNT, + pmbase + PM1_TMR, + pmbase + GPE0_STS, + 0, + 4, + 2, + 1, + 4, + 2 * sizeof(uint32_t), + 0, + 0); } static void i82801gx_lpc_read_resources(struct device *dev) diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index e3fdde7..ae40a42 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -460,86 +460,6 @@ config_t *chip = dev->chip_info; u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 16; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - fadt->reset_value = 6; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 0; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 0; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 128; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 0; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; fadt->day_alrm = 0xd; fadt->mon_alrm = 0x00; fadt->century = 0x32; @@ -569,6 +489,23 @@ | ACPI_FADT_C2_MP_SUPPORTED); if (chip->docking_supported) fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; + + acpi_fill_fadt_x86_pm(fadt, + pmbase, + 0, + pmbase + 0x4, + 0, + pmbase + 0x50, + pmbase + 0x8, + pmbase + 0x20, + 0, + 4, + 2, + 1, + 4, + 2 * 2 * sizeof(uint32_t), + 0, + 0); } static void i82801jx_lpc_read_resources(struct device *dev) diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 0062e09..29a263a 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -617,22 +617,6 @@ fadt->s4bios_req = 0x0; fadt->pstate_cnt = 0; - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 16; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; fadt->cst_cnt = 0; c2_latency = chip->c2_latency; if (!c2_latency) { @@ -664,70 +648,22 @@ fadt->flags |= ACPI_FADT_C2_MP_SUPPORTED; } - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 128; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; + acpi_fill_fadt_x86_pm(fadt, + pmbase, + 0, + pmbase + 0x4, + 0, + pmbase + 0x50, + pmbase + 0x8, + pmbase + 0x20, + 0, + 4, + 2, + 1, + 4, + 2 * 2 * sizeof(uint32_t), + 0, + 0); } static const char *lpc_acpi_name(const struct device *dev) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 0bfca35..589c4fa 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -767,35 +767,6 @@ fadt->s4bios_req = 0x0; fadt->pstate_cnt = 0; - fadt->pm1a_evt_blk = pmbase + PM1_STS; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + PM1_CNT; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + PM2_CNT; - fadt->pm_tmr_blk = pmbase + PM1_TMR; - if (pch_is_lp()) - fadt->gpe0_blk = pmbase + LP_GPE0_STS_1; - else - fadt->gpe0_blk = pmbase + GPE0_STS; - fadt->gpe1_blk = 0; - - /* - * Some of the lengths here are doubled. This is because they describe - * blocks containing two registers, where the size of each register - * is found by halving the block length. See Table 5-34 and section - * 4.8.3 of the ACPI specification for details. - */ - fadt->pm1_evt_len = 2 * 2; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - if (pch_is_lp()) - fadt->gpe0_blk_len = 2 * 16; - else - fadt->gpe0_blk_len = 2 * 8; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = 87; @@ -820,76 +791,21 @@ if (cfg->docking_supported) fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; - fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - - fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_evt_blk.bit_width = 2 * 16; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; - fadt->x_pm_tmr_blk.addrh = 0x0; - - /* - * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5. - * The bit_width field intentionally overflows here. - * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which - * seems to work fine on Linux 5.0 and Windows 10. - */ - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; + acpi_fill_fadt_x86_pm(fadt, + pmbase + PM1_STS, + 0, + pmbase + PM1_CNT, + 0, + pmbase + PM2_CNT, + pmbase + PM1_TMR, + pch_is_lp() ? (pmbase + LP_GPE0_STS_1) : (pmbase + GPE0_STS), + 0, + 4, + 2, + 1, + 4, + pch_is_lp() ? (2 * 4 * sizeof(uint32_t)) : (2 * 2 * sizeof(uint32_t)), + 0); } static const char *lpc_acpi_name(const struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/40036 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If58fcf9a1c39c159dfa08339cb931e552d499747 Gerrit-Change-Number: 40036 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: soc/intel/cannonlake: Add debugging of a number of FSPM parameters
by Jeremy Soller (Code Review) 13 Apr '21

13 Apr '21

Jeremy Soller has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35802 ) Change subject: soc/intel/cannonlake: Add debugging of a number of FSPM parameters ...................................................................... soc/intel/cannonlake: Add debugging of a number of FSPM parameters This implements soc_display_fspm_upd_params for soc/intel/cannonlake Some parameters are available only on Coffee Lake FSP or Comet Lake FSP Tested on System76 galp3-c (Coffee Lake FSP) and System76 galp4 (Comet Lake FSP) Change-Id: I01c7a07ce7446ff762849c64600e728339a4974f Signed-Of-By: Jeremy Soller <jeremy(a)system76.com> --- M src/soc/intel/cannonlake/romstage/romstage.c 1 file changed, 313 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/35802/1 diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index f782f63..af278cf 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -141,3 +141,316 @@ if (!s3wake) save_dimm_info(); } + +void soc_display_fspm_upd_params(const FSPM_UPD *fspm_old_upd, + const FSPM_UPD *fspm_new_upd) +{ + const FSP_M_CONFIG *new; + const FSP_M_CONFIG *old; + + old = &fspm_old_upd->FspmConfig; + new = &fspm_new_upd->FspmConfig; + + /* Display the parameters for MemoryInit */ + printk(BIOS_SPEW, "UPD values for MemoryInit:\n"); + + //TODO: Add more Comet Lake values + fsp_display_upd_value("PlatformMemorySize", 8, + old->PlatformMemorySize, new->PlatformMemorySize); + fsp_display_upd_value("MemorySpdPtr00", 4, old->MemorySpdPtr00, + new->MemorySpdPtr00); + fsp_display_upd_value("MemorySpdPtr01", 4, old->MemorySpdPtr01, + new->MemorySpdPtr01); + fsp_display_upd_value("MemorySpdPtr10", 4, old->MemorySpdPtr10, + new->MemorySpdPtr10); + fsp_display_upd_value("MemorySpdPtr11", 4, old->MemorySpdPtr11, + new->MemorySpdPtr11); + fsp_display_upd_value("MemorySpdDataLen", 2, old->MemorySpdDataLen, + new->MemorySpdDataLen); + fsp_display_upd_value("DqByteMapCh0[0]", 1, old->DqByteMapCh0[0], + new->DqByteMapCh0[0]); + fsp_display_upd_value("DqByteMapCh0[1]", 1, old->DqByteMapCh0[1], + new->DqByteMapCh0[1]); + fsp_display_upd_value("DqByteMapCh0[2]", 1, old->DqByteMapCh0[2], + new->DqByteMapCh0[2]); + fsp_display_upd_value("DqByteMapCh0[3]", 1, old->DqByteMapCh0[3], + new->DqByteMapCh0[3]); + fsp_display_upd_value("DqByteMapCh0[4]", 1, old->DqByteMapCh0[4], + new->DqByteMapCh0[4]); + fsp_display_upd_value("DqByteMapCh0[5]", 1, old->DqByteMapCh0[5], + new->DqByteMapCh0[5]); + fsp_display_upd_value("DqByteMapCh0[6]", 1, old->DqByteMapCh0[6], + new->DqByteMapCh0[6]); + fsp_display_upd_value("DqByteMapCh0[7]", 1, old->DqByteMapCh0[7], + new->DqByteMapCh0[7]); + fsp_display_upd_value("DqByteMapCh0[8]", 1, old->DqByteMapCh0[8], + new->DqByteMapCh0[8]); + fsp_display_upd_value("DqByteMapCh0[9]", 1, old->DqByteMapCh0[9], + new->DqByteMapCh0[9]); + fsp_display_upd_value("DqByteMapCh0[10]", 1, old->DqByteMapCh0[10], + new->DqByteMapCh0[10]); + fsp_display_upd_value("DqByteMapCh0[11]", 1, old->DqByteMapCh0[11], + new->DqByteMapCh0[11]); + fsp_display_upd_value("DqByteMapCh1[0]", 1, old->DqByteMapCh1[0], + new->DqByteMapCh1[0]); + fsp_display_upd_value("DqByteMapCh1[1]", 1, old->DqByteMapCh1[1], + new->DqByteMapCh1[1]); + fsp_display_upd_value("DqByteMapCh1[2]", 1, old->DqByteMapCh1[2], + new->DqByteMapCh1[2]); + fsp_display_upd_value("DqByteMapCh1[3]", 1, old->DqByteMapCh1[3], + new->DqByteMapCh1[3]); + fsp_display_upd_value("DqByteMapCh1[4]", 1, old->DqByteMapCh1[4], + new->DqByteMapCh1[4]); + fsp_display_upd_value("DqByteMapCh1[5]", 1, old->DqByteMapCh1[5], + new->DqByteMapCh1[5]); + fsp_display_upd_value("DqByteMapCh1[6]", 1, old->DqByteMapCh1[6], + new->DqByteMapCh1[6]); + fsp_display_upd_value("DqByteMapCh1[7]", 1, old->DqByteMapCh1[7], + new->DqByteMapCh1[7]); + fsp_display_upd_value("DqByteMapCh1[8]", 1, old->DqByteMapCh1[8], + new->DqByteMapCh1[8]); + fsp_display_upd_value("DqByteMapCh1[9]", 1, old->DqByteMapCh1[9], + new->DqByteMapCh1[9]); + fsp_display_upd_value("DqByteMapCh1[10]", 1, old->DqByteMapCh1[10], + new->DqByteMapCh1[10]); + fsp_display_upd_value("DqByteMapCh1[11]", 1, old->DqByteMapCh1[11], + new->DqByteMapCh1[11]); + fsp_display_upd_value("DqsMapCpu2DramCh0[0]", 1, + old->DqsMapCpu2DramCh0[0], new->DqsMapCpu2DramCh0[0]); + fsp_display_upd_value("DqsMapCpu2DramCh0[1]", 1, + old->DqsMapCpu2DramCh0[1], new->DqsMapCpu2DramCh0[1]); + fsp_display_upd_value("DqsMapCpu2DramCh0[2]", 1, + old->DqsMapCpu2DramCh0[2], new->DqsMapCpu2DramCh0[2]); + fsp_display_upd_value("DqsMapCpu2DramCh0[3]", 1, + old->DqsMapCpu2DramCh0[3], new->DqsMapCpu2DramCh0[3]); + fsp_display_upd_value("DqsMapCpu2DramCh0[4]", 1, + old->DqsMapCpu2DramCh0[4], new->DqsMapCpu2DramCh0[4]); + fsp_display_upd_value("DqsMapCpu2DramCh0[5]", 1, + old->DqsMapCpu2DramCh0[5], new->DqsMapCpu2DramCh0[5]); + fsp_display_upd_value("DqsMapCpu2DramCh0[6]", 1, + old->DqsMapCpu2DramCh0[6], new->DqsMapCpu2DramCh0[6]); + fsp_display_upd_value("DqsMapCpu2DramCh0[7]", 1, + old->DqsMapCpu2DramCh0[7], new->DqsMapCpu2DramCh0[7]); + fsp_display_upd_value("DqsMapCpu2DramCh1[0]", 1, + old->DqsMapCpu2DramCh1[0], new->DqsMapCpu2DramCh1[0]); + fsp_display_upd_value("DqsMapCpu2DramCh1[1]", 1, + old->DqsMapCpu2DramCh1[1], new->DqsMapCpu2DramCh1[1]); + fsp_display_upd_value("DqsMapCpu2DramCh1[2]", 1, + old->DqsMapCpu2DramCh1[2], new->DqsMapCpu2DramCh1[2]); + fsp_display_upd_value("DqsMapCpu2DramCh1[3]", 1, + old->DqsMapCpu2DramCh1[3], new->DqsMapCpu2DramCh1[3]); + fsp_display_upd_value("DqsMapCpu2DramCh1[4]", 1, + old->DqsMapCpu2DramCh1[4], new->DqsMapCpu2DramCh1[4]); + fsp_display_upd_value("DqsMapCpu2DramCh1[5]", 1, + old->DqsMapCpu2DramCh1[5], new->DqsMapCpu2DramCh1[5]); + fsp_display_upd_value("DqsMapCpu2DramCh1[6]", 1, + old->DqsMapCpu2DramCh1[6], new->DqsMapCpu2DramCh1[6]); + fsp_display_upd_value("DqsMapCpu2DramCh1[7]", 1, + old->DqsMapCpu2DramCh1[7], new->DqsMapCpu2DramCh1[7]); + fsp_display_upd_value("RcompResistor[0]", 2, old->RcompResistor[0], + new->RcompResistor[0]); + fsp_display_upd_value("RcompResistor[1]", 2, old->RcompResistor[1], + new->RcompResistor[1]); + fsp_display_upd_value("RcompResistor[2]", 2, old->RcompResistor[2], + new->RcompResistor[2]); + fsp_display_upd_value("RcompTarget[0]", 2, old->RcompTarget[0], + new->RcompTarget[0]); + fsp_display_upd_value("RcompTarget[1]", 2, old->RcompTarget[1], + new->RcompTarget[1]); + fsp_display_upd_value("RcompTarget[2]", 2, old->RcompTarget[2], + new->RcompTarget[2]); + fsp_display_upd_value("RcompTarget[3]", 2, old->RcompTarget[3], + new->RcompTarget[3]); + fsp_display_upd_value("RcompTarget[4]", 2, old->RcompTarget[4], + new->RcompTarget[4]); + fsp_display_upd_value("DqPinsInterleaved", 1, old->DqPinsInterleaved, + new->DqPinsInterleaved); + fsp_display_upd_value("CaVrefConfig", 1, old->CaVrefConfig, + new->CaVrefConfig); + fsp_display_upd_value("SmramMask", 1, old->SmramMask, new->SmramMask); +#if CONFIG(SOC_INTEL_COMETLAKE) + // Value only exists on Comet Lake + fsp_display_upd_value("MrcTimeMeasure", 1, old->MrcTimeMeasure, + new->MrcTimeMeasure); +#endif + fsp_display_upd_value("MrcFastBoot", 1, old->MrcFastBoot, + new->MrcFastBoot); + fsp_display_upd_value("RmtPerTask", 1, old->RmtPerTask, + new->RmtPerTask); + fsp_display_upd_value("TrainTrace", 1, old->TrainTrace, + new->TrainTrace); + fsp_display_upd_value("IedSize", 4, old->IedSize, new->IedSize); + fsp_display_upd_value("TsegSize", 4, old->TsegSize, new->TsegSize); + fsp_display_upd_value("MmioSize", 2, old->MmioSize, new->MmioSize); + fsp_display_upd_value("ProbelessTrace", 1, old->ProbelessTrace, + new->ProbelessTrace); + fsp_display_upd_value("GdxcIotSize", 1, old->GdxcIotSize, + new->GdxcIotSize); + fsp_display_upd_value("GdxcMotSize", 1, old->GdxcMotSize, + new->GdxcMotSize); + fsp_display_upd_value("SmbusEnable", 1, old->SmbusEnable, + new->SmbusEnable); + fsp_display_upd_value("SpdAddressTable[0]", 1, old->SpdAddressTable[0], + new->SpdAddressTable[0]); + fsp_display_upd_value("SpdAddressTable[1]", 1, old->SpdAddressTable[1], + new->SpdAddressTable[1]); + fsp_display_upd_value("SpdAddressTable[2]", 1, old->SpdAddressTable[2], + new->SpdAddressTable[2]); + fsp_display_upd_value("SpdAddressTable[3]", 1, old->SpdAddressTable[3], + new->SpdAddressTable[3]); + fsp_display_upd_value("PlatformDebugConsent", 1, + old->PlatformDebugConsent, new->PlatformDebugConsent); + fsp_display_upd_value("DciUsb3TypecUfpDbg", 1, old->DciUsb3TypecUfpDbg, + new->DciUsb3TypecUfpDbg); + fsp_display_upd_value("PchTraceHubMode", 1, old->PchTraceHubMode, + new->PchTraceHubMode); + fsp_display_upd_value("PchTraceHubMemReg0Size", 1, + old->PchTraceHubMemReg0Size, new->PchTraceHubMemReg0Size); + fsp_display_upd_value("PchTraceHubMemReg1Size", 1, + old->PchTraceHubMemReg1Size, new->PchTraceHubMemReg1Size); + // Skip PchPreMemRsvd[9] + fsp_display_upd_value("IgdDvmt50PreAlloc", 1, old->IgdDvmt50PreAlloc, + new->IgdDvmt50PreAlloc); + fsp_display_upd_value("InternalGfx", 1, old->InternalGfx, + new->InternalGfx); + fsp_display_upd_value("ApertureSize", 1, old->ApertureSize, + new->ApertureSize); + fsp_display_upd_value("UserBd", 1, old->UserBd, + new->UserBd); + fsp_display_upd_value("SaGv", 1, old->SaGv, + new->SaGv); + // Skip UnusedUpdSpace0 + fsp_display_upd_value("DdrFreqLimit", 2, old->DdrFreqLimit, + new->DdrFreqLimit); + fsp_display_upd_value("FreqSaGvLow", 2, old->FreqSaGvLow, + new->FreqSaGvLow); +#if ! CONFIG(SOC_INTEL_COMETLAKE) + // Value does not exist on Comet Lake + fsp_display_upd_value("FreqSaGvMid", 2, old->FreqSaGvMid, + new->FreqSaGvMid); +#endif + fsp_display_upd_value("RMT", 1, old->RMT, + new->RMT); + fsp_display_upd_value("DisableDimmChannel0", 1, + old->DisableDimmChannel0, new->DisableDimmChannel0); + fsp_display_upd_value("DisableDimmChannel1", 1, + old->DisableDimmChannel1, new->DisableDimmChannel1); + fsp_display_upd_value("ScramblerSupport", 1, old->ScramblerSupport, + new->ScramblerSupport); + fsp_display_upd_value("SkipMpInit", 1, old->SkipMpInit, + new->SkipMpInit); + // Skip UnusedUpdSpace1[15] + fsp_display_upd_value("SpdProfileSelected", 1, + old->SpdProfileSelected, new->SpdProfileSelected); + fsp_display_upd_value("RefClk", 1, old->RefClk, + new->RefClk); + fsp_display_upd_value("VddVoltage", 2, old->VddVoltage, + new->VddVoltage); + fsp_display_upd_value("Ratio", 1, old->Ratio, + new->Ratio); + fsp_display_upd_value("OddRatioMode", 1, old->OddRatioMode, + new->OddRatioMode); + fsp_display_upd_value("tCL", 1, old->tCL, + new->tCL); + fsp_display_upd_value("tCWL", 1, old->tCWL, + new->tCWL); + fsp_display_upd_value("tRCDtRP", 1, old->tRCDtRP, + new->tRCDtRP); + fsp_display_upd_value("tRRD", 1, old->tRRD, + new->tRRD); + fsp_display_upd_value("tFAW", 2, old->tFAW, + new->tFAW); + fsp_display_upd_value("tRAS", 2, old->tRAS, + new->tRAS); + fsp_display_upd_value("tREFI", 2, old->tREFI, + new->tREFI); + fsp_display_upd_value("tRFC", 2, old->tRFC, + new->tRFC); + fsp_display_upd_value("tRTP", 1, old->tRTP, + new->tRTP); + fsp_display_upd_value("tWR", 1, old->tWR, + new->tWR); + fsp_display_upd_value("NModeSupport", 1, old->NModeSupport, + new->NModeSupport); + fsp_display_upd_value("DllBwEn0", 1, old->DllBwEn0, + new->DllBwEn0); + fsp_display_upd_value("DllBwEn1", 1, old->DllBwEn1, + new->DllBwEn1); + fsp_display_upd_value("DllBwEn2", 1, old->DllBwEn2, + new->DllBwEn2); + fsp_display_upd_value("DllBwEn3", 1, old->DllBwEn3, + new->DllBwEn3); + fsp_display_upd_value("IsvtIoPort", 1, old->IsvtIoPort, + new->IsvtIoPort); + fsp_display_upd_value("CpuTraceHubMode", 1, old->CpuTraceHubMode, + new->CpuTraceHubMode); + fsp_display_upd_value("CpuTraceHubMemReg0Size", 1, + old->CpuTraceHubMemReg0Size, new->CpuTraceHubMemReg0Size); + fsp_display_upd_value("CpuTraceHubMemReg1Size", 1, + old->CpuTraceHubMemReg1Size, new->CpuTraceHubMemReg1Size); + fsp_display_upd_value("PeciC10Reset", 1, old->PeciC10Reset, + new->PeciC10Reset); + fsp_display_upd_value("PeciSxReset", 1, old->PeciSxReset, + new->PeciSxReset); + // Skip UnusedUpdSpace2[4] + fsp_display_upd_value("PchHdaEnable", 1, old->PchHdaEnable, + new->PchHdaEnable); + fsp_display_upd_value("PchIshEnable", 1, old->PchIshEnable, + new->PchIshEnable); + fsp_display_upd_value("HeciTimeouts", 1, old->HeciTimeouts, + new->HeciTimeouts); + // Skip UnusedUpdSpace3 + fsp_display_upd_value("Heci1BarAddress", 4, old->Heci1BarAddress, + new->Heci1BarAddress); + fsp_display_upd_value("Heci2BarAddress", 4, old->Heci2BarAddress, + new->Heci2BarAddress); + fsp_display_upd_value("Heci3BarAddress", 4, old->Heci3BarAddress, + new->Heci3BarAddress); + fsp_display_upd_value("SgDelayAfterPwrEn", 2, old->SgDelayAfterPwrEn, + new->SgDelayAfterPwrEn); + fsp_display_upd_value("SgDelayAfterHoldReset", 2, old->SgDelayAfterHoldReset, + new->SgDelayAfterHoldReset); + fsp_display_upd_value("MmioSizeAdjustment", 2, old->MmioSizeAdjustment, + new->MmioSizeAdjustment); + fsp_display_upd_value("DmiGen3ProgramStaticEq", 1, + old->DmiGen3ProgramStaticEq, new->DmiGen3ProgramStaticEq); + fsp_display_upd_value("Peg0Enable", 1, old->Peg0Enable, + new->Peg0Enable); + fsp_display_upd_value("Peg1Enable", 1, old->Peg1Enable, + new->Peg1Enable); + fsp_display_upd_value("Peg2Enable", 1, old->Peg2Enable, + new->Peg2Enable); + fsp_display_upd_value("Peg3Enable", 1, old->Peg3Enable, + new->Peg3Enable); + fsp_display_upd_value("Peg0MaxLinkSpeed", 1, old->Peg0MaxLinkSpeed, + new->Peg0MaxLinkSpeed); + fsp_display_upd_value("Peg1MaxLinkSpeed", 1, old->Peg1MaxLinkSpeed, + new->Peg1MaxLinkSpeed); + fsp_display_upd_value("Peg2MaxLinkSpeed", 1, old->Peg2MaxLinkSpeed, + new->Peg2MaxLinkSpeed); + fsp_display_upd_value("Peg3MaxLinkSpeed", 1, old->Peg3MaxLinkSpeed, + new->Peg3MaxLinkSpeed); + fsp_display_upd_value("Peg0MaxLinkWidth", 1, old->Peg0MaxLinkWidth, + new->Peg0MaxLinkWidth); + fsp_display_upd_value("Peg1MaxLinkWidth", 1, old->Peg1MaxLinkWidth, + new->Peg1MaxLinkWidth); + fsp_display_upd_value("Peg2MaxLinkWidth", 1, old->Peg2MaxLinkWidth, + new->Peg2MaxLinkWidth); + fsp_display_upd_value("Peg3MaxLinkWidth", 1, old->Peg3MaxLinkWidth, + new->Peg3MaxLinkWidth); + fsp_display_upd_value("Peg0PowerDownUnusedLanes", 1, + old->Peg0PowerDownUnusedLanes, new->Peg0PowerDownUnusedLanes); + fsp_display_upd_value("Peg1PowerDownUnusedLanes", 1, + old->Peg1PowerDownUnusedLanes, new->Peg1PowerDownUnusedLanes); + fsp_display_upd_value("Peg2PowerDownUnusedLanes", 1, + old->Peg2PowerDownUnusedLanes, new->Peg2PowerDownUnusedLanes); + fsp_display_upd_value("Peg3PowerDownUnusedLanes", 1, + old->Peg3PowerDownUnusedLanes, new->Peg3PowerDownUnusedLanes); + fsp_display_upd_value("InitPcieAspmAfterOprom", 1, + old->InitPcieAspmAfterOprom, new->InitPcieAspmAfterOprom); + fsp_display_upd_value("PegDisableSpreadSpectrumClocking", 1, + old->PegDisableSpreadSpectrumClocking, + new->PegDisableSpreadSpectrumClocking); + // Skip UnusedUpdSpace4[3] + //TODO: Offset 0x128 and up +} -- To view, visit https://review.coreboot.org/c/coreboot/+/35802 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01c7a07ce7446ff762849c64600e728339a4974f Gerrit-Change-Number: 35802 Gerrit-PatchSet: 1 Gerrit-Owner: Jeremy Soller <jackpot51(a)gmail.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: mb/ocp/tiogapass: Add UART init in bootblock
by David Hendricks (Code Review) 12 Apr '21

12 Apr '21

Hello Andrey Petrov, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39270 to review the following change. Change subject: mb/ocp/tiogapass: Add UART init in bootblock ...................................................................... mb/ocp/tiogapass: Add UART init in bootblock Based off code from CB:38840 Signed-off-by: Andrey Petrov <anpetrov(a)fb.com> Signed-off-by: David Hendricks <dhendrix(a)fb.com> Change-Id: I9a5c17e29173110429d66ec551be5a77b1c15538 --- M src/mainboard/ocp/tiogapass/Kconfig M src/mainboard/ocp/tiogapass/Makefile.inc A src/mainboard/ocp/tiogapass/bootblock.c M src/soc/intel/xeon_sp/bootblock/bootblock.c 4 files changed, 49 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/39270/1 diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig index dfa8f54..0a35697 100644 --- a/src/mainboard/ocp/tiogapass/Kconfig +++ b/src/mainboard/ocp/tiogapass/Kconfig @@ -25,6 +25,7 @@ select SOC_INTEL_XEON_SP select MAINBOARD_USES_FSP2_0 select FSP_CAR + select SUPERIO_ASPEED_AST2400 config MAINBOARD_DIR string diff --git a/src/mainboard/ocp/tiogapass/Makefile.inc b/src/mainboard/ocp/tiogapass/Makefile.inc index f5ea591..ae5fb70 100644 --- a/src/mainboard/ocp/tiogapass/Makefile.inc +++ b/src/mainboard/ocp/tiogapass/Makefile.inc @@ -15,6 +15,8 @@ ## GNU General Public License for more details. ## +bootblock-y += bootblock.c + ramstage-y += ramstage.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c diff --git a/src/mainboard/ocp/tiogapass/bootblock.c b/src/mainboard/ocp/tiogapass/bootblock.c new file mode 100644 index 0000000..bed8b1a --- /dev/null +++ b/src/mainboard/ocp/tiogapass/bootblock.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <bootblock_common.h> +#include <console/console.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <intelblocks/lpc_lib.h> +#include <intelblocks/pcr.h> +#include <intelblocks/uart.h> +#include <soc/pci_devs.h> +#include <superio/aspeed/ast2400/ast2400.h> +#include <superio/aspeed/common/aspeed.h> + +#define PID_DMI 0xef + +void bootblock_mainboard_init(void) +{ + /* + * Set up decoding windows on PCH over PCR. The CPUs use two of AST2500 SIO ports, + * one is connected to debug header and another is used as SOL. + */ + pcr_write32(PID_DMI, PCR_DMI_LPCIOD, (0 << 0) | (1 << 4)); + pcr_write32(PID_DMI, PCR_DMI_LPCIOE, (1 << 0) | (1 << 1)); + /* for unidentified reason lpc_io_setup_comm_a_b() doesn't work */ + /* enable com1 and com2 and 0x3f8 and 0x2f8, and 0x2e */ + pci_mmio_write_config32(PCH_DEV_LPC, 0x80, + (1<<28) | (1<<16) | (1<<17) | (0 << 0) | (1 << 4)); + + const pnp_devfn_t serial_dev = PNP_DEV(0x2e, AST2400_SUART1); + aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); + + if (CONFIG(BOOTBLOCK_CONSOLE)) { + console_init(); + } +} diff --git a/src/soc/intel/xeon_sp/bootblock/bootblock.c b/src/soc/intel/xeon_sp/bootblock/bootblock.c index 9eb7ff9..a3b7bce 100644 --- a/src/soc/intel/xeon_sp/bootblock/bootblock.c +++ b/src/soc/intel/xeon_sp/bootblock/bootblock.c @@ -15,11 +15,11 @@ */ #include <bootblock_common.h> +#include <console/console.h> #include <device/pci.h> #include <FsptUpd.h> #include <intelblocks/fast_spi.h> #include <soc/iomap.h> -#include <console/console.h> const FSPT_UPD temp_ram_init_params = { .FspUpdHeader = { @@ -56,6 +56,9 @@ void bootblock_soc_init(void) { - if (CONFIG(BOOTBLOCK_CONSOLE)) + bootblock_mainboard_init(); + + if (CONFIG(BOOTBLOCK_CONSOLE)) { printk(BIOS_DEBUG, "FSP TempRamInit successful...\n"); + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/39270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a5c17e29173110429d66ec551be5a77b1c15538 Gerrit-Change-Number: 39270 Gerrit-PatchSet: 1 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: payloads/LinuxBoot: make linux kernel build reproducible
by Alexander Couzens (Code Review) 09 Apr '21

09 Apr '21

Alexander Couzens has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35393 ) Change subject: payloads/LinuxBoot: make linux kernel build reproducible ...................................................................... payloads/LinuxBoot: make linux kernel build reproducible Reproducible builds have to be independent from user, host, domain, time. Taken from OpenWrt (GPL2). Change-Id: I420588acc66647051c08e4da6fbedc205cd62877 --- M payloads/external/LinuxBoot/targets/linux.mk 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/35393/1 diff --git a/payloads/external/LinuxBoot/targets/linux.mk b/payloads/external/LinuxBoot/targets/linux.mk index 8be0926..c676f68 100644 --- a/payloads/external/LinuxBoot/targets/linux.mk +++ b/payloads/external/LinuxBoot/targets/linux.mk @@ -30,7 +30,11 @@ OBJCOPY:=$(LINUXBOOT_CROSS_COMPILE)objcopy KERNEL_MAKE_FLAGS = \ - ARCH=$(ARCH-y) + ARCH=$(ARCH-y) \ + KBUILD_BUILD_USER="coreboot" \ + KBUILD_BUILD_HOST="reproducible" \ + KBUILD_BUILD_TIMESTAMP="$(shell perl -e 'print scalar gmtime($(SOURCE_DATE_EPOCH))')" \ + KBUILD_BUILD_VERSION="0" ifeq ($(CONFIG_LINUXBOOT_KERNEL_CUSTOM),y) kernel_version:=$(CONFIG_LINUXBOOT_KERNEL_CUSTOM_VERSION) -- To view, visit https://review.coreboot.org/c/coreboot/+/35393 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I420588acc66647051c08e4da6fbedc205cd62877 Gerrit-Change-Number: 35393 Gerrit-PatchSet: 1 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-MessageType: newchange

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