coreboot-gerrit June 2020

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Change in coreboot[master]: mb/intel/coffeelake_rvp: Fix display issues on CFL-H, CFL-S, WHL Inte...
by Lean Sheng Tan (Code Review) 25 Jun '21

25 Jun '21

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34159 ) Change subject: mb/intel/coffeelake_rvp: Fix display issues on CFL-H, CFL-S, WHL Intel RVP ...................................................................... mb/intel/coffeelake_rvp: Fix display issues on CFL-H, CFL-S, WHL Intel RVP This patch fixes display issues on both CFL-H & S, and WHL Intel RVP platform where display are not showing up in UEFI shell, by configuring DDi ports in device tree. This patches also fixes no eDP display observed in UEFI shell on UEFI Payload. Root cause is eDP requires minimum delay between GPIO programming and eDP initialisation, which was not sufficient during FSP initialisation which causes VBT to return error during eDP init. This issue is fixed by programming eDP GPIO's in bootblock stage and skipping FSP GPIO programming by setting 'DdiPortEdp=0' in devicetree. TEST= verified eDP display, HDMI and DP functionalities on CFL-H, CFL-S & WHL Intel RVP platforms. Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Change-Id: Iee87649492f7803210f9a35cd46b4f9826cbc93c --- M src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c M src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb 4 files changed, 52 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/34159/1 diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c index ec8f58b..aa009bb 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c @@ -593,6 +593,19 @@ /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + #if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) + /* I4 : EDP_HPD */ + PAD_CFG_NF(GPP_I4, NONE, PLTRST, NF1), + + /* F19 : EDP_VDDEN */ + PAD_CFG_NF(GPP_F19, NONE, PLTRST, NF1), + + /* F20 : EDP_BKLTEN */ + PAD_CFG_NF(GPP_F20, NONE, PLTRST, NF1), + + /* F21 : EDP_BKLTCTL */ + PAD_CFG_NF(GPP_F21, NONE, PLTRST, NF1), + #endif }; diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb index 9648ac3..40da8eb 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb @@ -9,6 +9,19 @@ register "RMT" = "1" register "ScsEmmcHs400Enabled" = "1" + # Enable eDP device + register "DdiPortEdp" = "0" + # Enable HPD for DDI ports B/C + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" + register "DdiPortDHpd" = "1" + register "DdiPortFHpd" = "0" + # Enable DDC for DDI ports B/C + register "DdiPortBDdc" = "1" + register "DdiPortCDdc" = "1" + register "DdiPortDDdc" = "1" + register "DdiPortFDdc" = "0" + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC5)" register "usb2_ports[1]" = "USB2_PORT_MID(OC6)" register "usb2_ports[2]" = "USB2_PORT_MID(OC4)" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb index 126cab0..6ee52a4 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb @@ -9,6 +9,19 @@ register "RMT" = "1" register "ScsEmmcHs400Enabled" = "1" + # Enable eDP device + register "DdiPortEdp" = "0" + # Enable HPD for DDI ports B/C + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" + register "DdiPortDHpd" = "1" + register "DdiPortFHpd" = "1" + # Enable DDC for DDI ports B/C + register "DdiPortBDdc" = "0" + register "DdiPortCDdc" = "1" + register "DdiPortDDdc" = "1" + register "DdiPortFDdc" = "1" + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC4)" register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb index 429d5da..e824ac9 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb @@ -9,6 +9,19 @@ register "ScsEmmcHs400Enabled" = "1" register "HeciEnabled" = "1" + # Enable eDP device + register "DdiPortEdp" = "1" + # Enable HPD for DDI ports B/C + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" + register "DdiPortDHpd" = "0" + register "DdiPortFHpd" = "0" + # Enable DDC for DDI ports B/C + register "DdiPortBDdc" = "1" + register "DdiPortCDdc" = "1" + register "DdiPortDDdc" = "1" + register "DdiPortFDdc" = "0" + # Enable eDP device register "DdiPortEdp" = "1" # Enable HPD for DDI ports B/C/D/F -- To view, visit https://review.coreboot.org/c/coreboot/+/34159 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee87649492f7803210f9a35cd46b4f9826cbc93c Gerrit-Change-Number: 34159 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-MessageType: newchange

6 15

Change in coreboot[master]: [WIP]soc/intel/car: Add support for bootguard CAR
by Arthur Heymans (Code Review) 23 Jun '21

23 Jun '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36682 ) Change subject: [WIP]soc/intel/car: Add support for bootguard CAR ...................................................................... [WIP]soc/intel/car: Add support for bootguard CAR Bootguard sets up CAR on its own so the only thing needed is to find a free MTRR for our own CAR region. Change-Id: Ifac5267f8f4b820a61519fb4a497e2ce7075cc40 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/cpu/car/cache_as_ram.S 1 file changed, 66 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/36682/1 diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index d5f5081..3ae4829 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -23,11 +23,20 @@ #include <rules.h> #include <intelblocks/msr.h> +#define BOOTGUARD_MSR 0x13a + .global bootblock_pre_c_entry bootblock_pre_c_entry: post_code(0x20) +/* Bootguard setups up it's own CAR and needs separate handling */ +check_boot_guard: + movl $BOOTGUARD_MSR, %ecx + rdmsr + andl $1, %eax + jnz bootguard_car_setup + movl $no_reset, %esp /* return address */ jmp check_mtrr /* Check if CPU properly reset */ @@ -456,3 +465,60 @@ jmp car_init_done #endif + +bootguard_car_setup: + /* Configure MTRR_PHYS_MASK_HIGH for proper addressing above 4GB + * based on the physical address size supported for this processor + * This is based on read from CPUID EAX = 080000008h, EAX bits [7:0] + */ + movl $0x80000008, %eax /* Address sizes leaf */ + cpuid + sub $32, %al + movzx %al, %eax + xorl %esi, %esi + bts %eax, %esi + dec %esi /* esi <- MTRR_PHYS_MASK_HIGH */ + + /* Figure put how many MTRRs we have */ + mov $MTRR_CAP_MSR, %ecx + rdmsr + movzb %al, %ebx /* Number of variable MTRRs */ + + /* Find a free variable MTRR */ + movl $MTRR_PHYS_MASK(0), %ecx +test_is_free_mtrr: + rdmsr + test $MTRR_PHYS_MASK_VALID, %eax + jz found_free_mtrr + addl $2, %ecx + dec %ebx + jnz test_is_free_mtrr + + jmp .halt_forever + +found_free_mtrr: + /* Assume one MTRR is enough for now */ + decl %ecx /* MTRR_PHYS_BASE */ + movl $CONFIG_DCACHE_RAM_BASE, %eax + orl $MTRR_TYPE_WRBACK, %eax + xorl %edx, %edx + wrmsr + + /* Configure the MTRR mask for the size region */ + incl %ecx + mov $CONFIG_DCACHE_RAM_SIZE, %eax /* size mask */ + decl %eax + not %eax + or $MTRR_PHYS_MASK_VALID, %eax + movl %esi, %edx /* edx <- MTRR_PHYS_MASK_HIGH */ + wrmsr + +clear_cache_region: + /* Clear the cache memory region. This will also fill up the cache */ + movl $CONFIG_DCACHE_RAM_BASE, %edi + movl $CONFIG_DCACHE_RAM_SIZE, %ecx + shr $0x02, %ecx + xor %eax, %eax + cld + rep stosl + jmp car_init_done -- To view, visit https://review.coreboot.org/c/coreboot/+/36682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifac5267f8f4b820a61519fb4a497e2ce7075cc40 Gerrit-Change-Number: 36682 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

12 62

Change in coreboot[master]: soc/intel/common/cache_as_ram.S: Add macro to clear CAR
by Arthur Heymans (Code Review) 22 Jun '21

22 Jun '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37191 ) Change subject: soc/intel/common/cache_as_ram.S: Add macro to clear CAR ...................................................................... soc/intel/common/cache_as_ram.S: Add macro to clear CAR Add a macro to clear CAR which is replicated 3 times in this code. Change-Id: Iec28e3f393c4fe222bfb0d5358f815691ec199ae Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/cpu/car/cache_as_ram.S 1 file changed, 15 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/37191/1 diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index d1ae6ca..6a0728d 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -48,6 +48,17 @@ 3: .endm + .macro clear_car + /* Clear the cache memory region. This will also fill up the cache */ + movl $CONFIG_DCACHE_RAM_BASE, %edi + movl $CONFIG_DCACHE_RAM_SIZE, %ecx + shr $0x02, %ecx + xor %eax, %eax + cld + rep stosl + .endm + + .global bootblock_pre_c_entry bootblock_pre_c_entry: @@ -256,13 +267,7 @@ post_code(0x26) - /* Clear the cache memory region. This will also fill up the cache */ - movl $CONFIG_DCACHE_RAM_BASE, %edi - movl $CONFIG_DCACHE_RAM_SIZE, %ecx - shr $0x02, %ecx - xor %eax, %eax - cld - rep stosl + clear_car post_code(0x27) @@ -353,13 +358,7 @@ post_code(0x26) - /* Clear the cache memory region. This will also fill up the cache */ - movl $CONFIG_DCACHE_RAM_BASE, %edi - movl $CONFIG_DCACHE_RAM_SIZE, %ecx - shr $0x02, %ecx - xor %eax, %eax - cld - rep stosl + clear_car post_code(0x27) @@ -462,12 +461,8 @@ xorl %edx, %edx wrmsr - movl $CONFIG_DCACHE_RAM_BASE, %edi - movl $CONFIG_DCACHE_RAM_SIZE, %ecx - shr $0x02, %ecx - xor %eax, %eax - cld - rep stosl + clear_car + /* * Set IA32_PQR_ASSOC = 0x01 * At this stage we apply LLC_WAY_MASK_1 to the cache. -- To view, visit https://review.coreboot.org/c/coreboot/+/37191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec28e3f393c4fe222bfb0d5358f815691ec199ae Gerrit-Change-Number: 37191 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 16

Change in coreboot[master]: soc/intel/common/cache_as_ram.S: Add macro to find a free MTRR
by Arthur Heymans (Code Review) 22 Jun '21

22 Jun '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37190 ) Change subject: soc/intel/common/cache_as_ram.S: Add macro to find a free MTRR ...................................................................... soc/intel/common/cache_as_ram.S: Add macro to find a free MTRR This adds a macro to find an available MTRR(s) to set up CAR. This added complexity is not required on bootpaths without bootguard but with bootguard MTRR's have already been set up by the ACM so we need to figure out at runtime which ones are available. Change-Id: I7d5442c75464cfb2b3611c63a472c8ee521c014d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/cpu/car/cache_as_ram.S 1 file changed, 43 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/37190/1 diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 0992d85..d1ae6ca 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -23,6 +23,31 @@ #include <rules.h> #include <intelblocks/msr.h> + /* puts 1 to eax if not found, 0 if found */ + .macro find_free_mtrr + /* Figure put how many MTRRs we have */ + mov $MTRR_CAP_MSR, %ecx + rdmsr + movzb %al, %ebx /* Number of variable MTRRs */ + + /* Find a free variable MTRR */ + movl $MTRR_PHYS_MASK(0), %ecx +1: + rdmsr + test $MTRR_PHYS_MASK_VALID, %eax + jz 2f + addl $2, %ecx + dec %ebx + jnz 1b + + movl $1, %eax + jmp 3f +2: + movl $0, %eax + decl %ecx +3: + .endm + .global bootblock_pre_c_entry bootblock_pre_c_entry: @@ -93,15 +118,19 @@ post_code(0x24) #if ((CONFIG_DCACHE_RAM_SIZE & (CONFIG_DCACHE_RAM_SIZE - 1)) == 0) + find_free_mtrr + cmp $1, %eax + jne 1f + jmp .halt_forever +1: /* Configure CAR region as write-back (WB) */ - mov $MTRR_PHYS_BASE(0), %ecx mov $CONFIG_DCACHE_RAM_BASE, %eax or $MTRR_TYPE_WRBACK, %eax xor %edx,%edx wrmsr /* Configure the MTRR mask for the size region */ - mov $MTRR_PHYS_MASK(0), %ecx + inc %ecx mov $CONFIG_DCACHE_RAM_SIZE, %eax /* size mask */ dec %eax not %eax @@ -109,14 +138,18 @@ movl %esi, %edx /* edx <- MTRR_PHYS_MASK_HIGH */ wrmsr #elif (CONFIG_DCACHE_RAM_SIZE == 768 * KiB) /* 768 KiB */ + find_free_mtrr + cmp $1, %eax + jne 1f + jmp .halt_forever +1: /* Configure CAR region as write-back (WB) */ - mov $MTRR_PHYS_BASE(0), %ecx mov $CONFIG_DCACHE_RAM_BASE, %eax or $MTRR_TYPE_WRBACK, %eax xor %edx,%edx wrmsr - mov $MTRR_PHYS_MASK(0), %ecx + incl %ecx mov $(512 * KiB), %eax /* size mask */ dec %eax not %eax @@ -124,13 +157,17 @@ movl %esi, %edx /* edx <- MTRR_PHYS_MASK_HIGH */ wrmsr - mov $MTRR_PHYS_BASE(1), %ecx + find_free_mtrr + cmp $1, %eax + jne 1f + jmp .halt_forever +1: mov $(CONFIG_DCACHE_RAM_BASE + 512 * KiB), %eax or $MTRR_TYPE_WRBACK, %eax xor %edx,%edx wrmsr - mov $MTRR_PHYS_MASK(1), %ecx + incl %ecx mov $(256 * KiB), %eax /* size mask */ dec %eax not %eax -- To view, visit https://review.coreboot.org/c/coreboot/+/37190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d5442c75464cfb2b3611c63a472c8ee521c014d Gerrit-Change-Number: 37190 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

6 23

Change in coreboot[master]: ec/google/wilco: Fix comment about enclosure type
by Kyösti Mälkki (Code Review) 21 Jun '21

21 Jun '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42141 ) Change subject: ec/google/wilco: Fix comment about enclosure type ...................................................................... ec/google/wilco: Fix comment about enclosure type SYSTEM_TYPE_CONVERTIBLE is not valid SMBIOS enclosure type, but selecting it implies SMBIOS_ENCLOSURE_CONVERTIBLE. Change-Id: Ib658af7b80586428b22f08a738964637e1fbd17a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/ec/google/wilco/acpi/vbtn.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/42141/1 diff --git a/src/ec/google/wilco/acpi/vbtn.asl b/src/ec/google/wilco/acpi/vbtn.asl index 6227367..bc9dd34 100644 --- a/src/ec/google/wilco/acpi/vbtn.asl +++ b/src/ec/google/wilco/acpi/vbtn.asl @@ -5,7 +5,7 @@ * the Linux kernel at drivers/platform/x86/intel-vbtn.c * * For tablet/laptop and dock/undock events to work the board must - * select SYSTEM_TYPE_CONVERTIBLE for the SMBIOS enclosure type to + * have SMBIOS_ENCLOSURE_CONVERTIBLE for the SMBIOS enclosure type to * indicate the device is a convertible. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42141 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib658af7b80586428b22f08a738964637e1fbd17a Gerrit-Change-Number: 42141 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: cpu/x86/smm: Drop now unused `num_cpus` param
by Name of user not set (Code Review) 17 Jun '21

17 Jun '21

cedarhouse1(a)comcast.net has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40439 ) Change subject: cpu/x86/smm: Drop now unused `num_cpus` param ...................................................................... cpu/x86/smm: Drop now unused `num_cpus` param Suggested by Nico Huber in CL 38767 Change-Id: Ib5c646a380bf8d8ca001a5f821f89998b21e9957 Signed-off-by: Eugene D Myers <cedarhouse(a)comcast.net> --- M src/cpu/x86/smm/smm_module_loader.c M src/cpu/x86/smm/smm_stub.S M src/include/cpu/x86/smm.h 3 files changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/40439/1 diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index c50e97d..2279fe8 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -262,7 +262,6 @@ stub_params->runtime.smbase = (uintptr_t)smbase; stub_params->runtime.smm_size = smm_size; stub_params->runtime.save_state_size = params->per_cpu_save_state_size; - stub_params->runtime.num_cpus = params->num_concurrent_stacks; /* Initialize the APIC id to CPU number table to be 1:1 */ for (i = 0; i < params->num_concurrent_stacks; i++) diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index 7e32036..edb8719 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -35,8 +35,6 @@ .long 0 save_state_size: .long 0 -num_cpus: -.long 0 /* allows the STM to bring up SMM in 32-bit mode */ start32_offset: .long smm_trampoline32 - _start diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index afa8cf4..0ed3847 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -54,7 +54,6 @@ u32 smbase; u32 smm_size; u32 save_state_size; - u32 num_cpus; /* STM's 32bit entry into SMI handler */ u32 start32_offset; /* The apic_id_to_cpu provides a mapping from APIC id to CPU number. -- To view, visit https://review.coreboot.org/c/coreboot/+/40439 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5c646a380bf8d8ca001a5f821f89998b21e9957 Gerrit-Change-Number: 40439 Gerrit-PatchSet: 1 Gerrit-Owner: cedarhouse1(a)comcast.net Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: [RFC] treewide: Configure PCI Bus Master based on config option
by Felix Singer (Code Review) 17 Jun '21

17 Jun '21

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42460 ) Change subject: [RFC] treewide: Configure PCI Bus Master based on config option ...................................................................... [RFC] treewide: Configure PCI Bus Master based on config option Change-Id: I25565315a5ddf8d53097ac4cb4884ecebcc9c0a9 Signed-off-by: Felix Singer <felix.singer(a)secunet.com> --- M src/northbridge/intel/gm45/gma.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/haswell/minihd.c M src/northbridge/intel/i945/gma.c M src/northbridge/intel/ironlake/early_init.c M src/northbridge/intel/ironlake/gma.c M src/northbridge/intel/pineview/gma.c M src/northbridge/intel/sandybridge/gma.c M src/northbridge/intel/x4x/gma.c M src/soc/amd/stoneyridge/psp.c M src/soc/intel/apollolake/bootblock/bootblock.c M src/soc/intel/braswell/southcluster.c M src/soc/intel/broadwell/adsp.c M src/soc/intel/broadwell/hda.c M src/soc/intel/broadwell/igd.c M src/soc/intel/broadwell/me.c M src/soc/intel/broadwell/minihd.c M src/soc/intel/broadwell/pcie.c M src/soc/intel/broadwell/serialio.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/gspi/gspi.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/scs/early_mmc.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/denverton_ns/bootblock/uart.c M src/soc/intel/denverton_ns/lpc.c M src/soc/intel/denverton_ns/pmc.c M src/soc/intel/denverton_ns/sata.c M src/soc/intel/denverton_ns/xhci.c M src/southbridge/amd/cimx/sb800/late.c M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/bd82x6x/pci.c M src/southbridge/intel/bd82x6x/pcie.c M src/southbridge/intel/bd82x6x/usb_ehci.c M src/southbridge/intel/i82801dx/usb.c M src/southbridge/intel/i82801dx/usb2.c M src/southbridge/intel/i82801gx/azalia.c M src/southbridge/intel/i82801gx/ide.c M src/southbridge/intel/i82801gx/pci.c M src/southbridge/intel/i82801gx/pcie.c M src/southbridge/intel/i82801gx/usb.c M src/southbridge/intel/i82801gx/usb_ehci.c M src/southbridge/intel/i82801ix/hdaudio.c M src/southbridge/intel/i82801ix/pcie.c M src/southbridge/intel/i82801ix/sata.c M src/southbridge/intel/i82801ix/usb_ehci.c M src/southbridge/intel/i82801jx/hdaudio.c M src/southbridge/intel/i82801jx/pcie.c M src/southbridge/intel/i82801jx/sata.c M src/southbridge/intel/i82801jx/usb_ehci.c M src/southbridge/intel/i82870/ioapic.c M src/southbridge/intel/ibexpeak/azalia.c M src/southbridge/intel/ibexpeak/me.c M src/southbridge/intel/ibexpeak/usb_ehci.c M src/southbridge/intel/lynxpoint/azalia.c M src/southbridge/intel/lynxpoint/me_9.x.c M src/southbridge/intel/lynxpoint/pcie.c M src/southbridge/intel/lynxpoint/serialio.c M src/southbridge/intel/lynxpoint/usb_ehci.c 65 files changed, 101 insertions(+), 82 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/42460/1 diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 3d48ca2..af21802 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -157,7 +157,7 @@ mmio = res2mmio(gtt_res, 0, 0); if (!CONFIG(NO_GFX_INIT)) - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); if (!CONFIG(MAINBOARD_USE_LIBGFXINIT)) { /* PCI Init, will run VBIOS */ diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 68072ff..8320f59 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -468,7 +468,7 @@ gma_setup_panel(dev); if (!CONFIG(NO_GFX_INIT)) - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); int vga_disable = (pci_read_config16(dev, GGC) & 2) >> 1; diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c index c6b5a12..64a843e 100644 --- a/src/northbridge/intel/haswell/minihd.c +++ b/src/northbridge/intel/haswell/minihd.c @@ -59,7 +59,7 @@ printk(BIOS_DEBUG, "Mini-HD: base = %p\n", base); /* Set Bus Master */ - pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); /* Mini-HD configuration */ reg32 = read32(base + 0x100c); diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 929968e..f677d50 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -671,7 +671,7 @@ ; if (!CONFIG(NO_GFX_INIT)) - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); if (CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) { int vga_disable = (pci_read_config16(dev, GGC) & 2) >> 1; @@ -711,7 +711,7 @@ u8 val; if (!CONFIG(NO_GFX_INIT)) - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); if (get_option(&val, "tft_brightness") == CB_SUCCESS) pci_write_config8(dev, 0xf4, val); diff --git a/src/northbridge/intel/ironlake/early_init.c b/src/northbridge/intel/ironlake/early_init.c index b6c5f0f..908ff8d 100644 --- a/src/northbridge/intel/ironlake/early_init.c +++ b/src/northbridge/intel/ironlake/early_init.c @@ -132,8 +132,8 @@ early_cpu_init(); pci_write_config32(PCI_DEV(0, 0x16, 0), 0x10, (uintptr_t)DEFAULT_HECIBAR); - pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_configure_bus_master(dev); /* Magic for S3 resume. Must be done early. */ if (s3_resume) { diff --git a/src/northbridge/intel/ironlake/gma.c b/src/northbridge/intel/ironlake/gma.c index 8baccb2..9fabe74 100644 --- a/src/northbridge/intel/ironlake/gma.c +++ b/src/northbridge/intel/ironlake/gma.c @@ -138,7 +138,7 @@ intel_gma_init_igd_opregion(); if (!CONFIG(NO_GFX_INIT)) - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); if (!gtt_res || !gtt_res->base) diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c index e46bd7c..12a1b7c 100644 --- a/src/northbridge/intel/pineview/gma.c +++ b/src/northbridge/intel/pineview/gma.c @@ -221,7 +221,7 @@ intel_gma_init_igd_opregion(); if (!CONFIG(NO_GFX_INIT)) - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); if (!CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) { /* PCI init, will run VBIOS */ diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 83a0279..fbf25b3 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -591,7 +591,7 @@ gma_pm_init_pre_vbios(dev); if (!CONFIG(NO_GFX_INIT)) - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); if (!CONFIG(MAINBOARD_USE_LIBGFXINIT)) /* PCI Init, will run VBIOS */ diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 68d382e..1e77b4b 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -25,7 +25,7 @@ intel_gma_init_igd_opregion(); if (!CONFIG(NO_GFX_INIT)) - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); /* configure GMBUSFREQ */ pci_update_config16(dev, 0xcc, ~0x1ff, 0xbc); diff --git a/src/soc/amd/stoneyridge/psp.c b/src/soc/amd/stoneyridge/psp.c index c24b8be..f7bed62 100644 --- a/src/soc/amd/stoneyridge/psp.c +++ b/src/soc/amd/stoneyridge/psp.c @@ -26,8 +26,9 @@ /* Enable memory access and master */ cmd = pci_read_config16(SOC_PSP_DEV, PCI_COMMAND); - cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; + cmd |= PCI_COMMAND_MEMORY; pci_write_config16(SOC_PSP_DEV, PCI_COMMAND, cmd); + pci_configure_bus_master(dev); }; void *soc_get_mbox_address(void) diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 2137e49..828d0b7 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -68,8 +68,8 @@ pci_write_config32(pmc, PCI_BASE_ADDRESS_3, 0); /* 64-bit BAR */ pci_write_config16(pmc, PCI_BASE_ADDRESS_4, ACPI_BASE_ADDRESS); pci_write_config16(pmc, PCI_COMMAND, - PCI_COMMAND_IO | PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER); + PCI_COMMAND_IO | PCI_COMMAND_MEMORY); + pci_configure_bus_master(dev); } void bootblock_soc_early_init(void) diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index 094e1c2..d66d543 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -267,7 +267,8 @@ /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_SPECIAL); + pci_configure_bus_master(dev); /* Use IRQ9 for SCI Interrupt */ write32((void *)(ilb_base + ACTL), 0); diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/adsp.c index b8699a2..dcff272 100644 --- a/src/soc/intel/broadwell/adsp.c +++ b/src/soc/intel/broadwell/adsp.c @@ -23,7 +23,8 @@ u32 tmp32; /* Ensure memory and bus master are enabled */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_configure_bus_master(dev); /* Find BAR0 and BAR1 */ bar0 = find_resource(dev, PCI_BASE_ADDRESS_0); diff --git a/src/soc/intel/broadwell/hda.c b/src/soc/intel/broadwell/hda.c index 1640825..569dc26 100644 --- a/src/soc/intel/broadwell/hda.c +++ b/src/soc/intel/broadwell/hda.c @@ -93,7 +93,7 @@ printk(BIOS_DEBUG, "HDA: base = %p\n", base); /* Set Bus Master */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); hda_pch_init(dev, base); diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index 41167b1..6a81f53 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -501,7 +501,7 @@ return; if (!CONFIG(NO_GFX_INIT)) - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); /* Wait for any configured pre-graphics delay */ if (!acpi_is_wakeup_s3()) { diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index 7449902..c903605 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -721,7 +721,8 @@ mei_base_address = res2mmio(res, 0, 0); /* Ensure Memory and Bus Master bits are set */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_configure_bus_master(dev); /* Clean up status for next message */ read_host_csr(&host); diff --git a/src/soc/intel/broadwell/minihd.c b/src/soc/intel/broadwell/minihd.c index b91d73d..725e9dc 100644 --- a/src/soc/intel/broadwell/minihd.c +++ b/src/soc/intel/broadwell/minihd.c @@ -61,7 +61,7 @@ printk(BIOS_DEBUG, "Mini-HD: base = %p\n", base); /* Set Bus Master */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); /* Mini-HD configuration */ reg32 = read32(base + 0x100c); diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index 9eb14d9..9271fe1 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -580,7 +580,7 @@ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); /* Enable Bus Master */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); /* Set Cache Line Size to 0x10 */ pci_write_config8(dev, 0x0c, 0x10); diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c index 20a5d9a..cd33d55 100644 --- a/src/soc/intel/broadwell/serialio.c +++ b/src/soc/intel/broadwell/serialio.c @@ -163,7 +163,8 @@ printk(BIOS_DEBUG, "Initializing Serial IO device\n"); /* Ensure memory and bus master are enabled */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_configure_bus_master(dev); /* Find BAR0 and BAR1 */ bar0 = find_resource(dev, PCI_BASE_ADDRESS_0); diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index fecc71e..5c355a5 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -95,7 +95,8 @@ pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0x0); /* Enable Bus Master and MMIO Space */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_configure_bus_master(dev); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); cse.sec_bar = tempbar; } diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 655d113..e741892 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -272,7 +272,8 @@ spi_base_address | PCI_BASE_ADDRESS_SPACE_MEMORY); /* Enable Bus Master and MMIO Space */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_configure_bus_master(dev); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); /* Initialize SPI to allow BIOS to write/erase on flash. */ fast_spi_init(); diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index f232ee5..8e3b1a3 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -55,7 +55,7 @@ return; if (!CONFIG(NO_GFX_INIT)) - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { if (!acpi_is_wakeup_s3() && display_init_required()) { diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index 599ab7e..65bd287 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -172,8 +172,8 @@ static void gspi_set_base_addr(int devfn, struct device *dev, uintptr_t base) { pci_write_config32(dev, PCI_BASE_ADDRESS_0, base); - pci_write_config32(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER); + pci_write_config32(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_configure_bus_master(dev); } #endif diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index f7c241d..8931731 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -68,8 +68,9 @@ /* Prepare early base address for access before memory */ base = dw_i2c_get_soc_early_base(bus); pci_write_config32(dev, PCI_BASE_ADDRESS_0, base); - pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + + pci_configure_bus_master(dev); /* Take device out of reset */ lpss_reset_release(base); diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 4f4ab43..128be7a 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -22,8 +22,8 @@ pci_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_1, 0); /* Enable P2SB MSE */ - pci_write_config16(PCH_DEV_P2SB, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_write_config16(PCH_DEV_P2SB, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_configure_bus_master(dev); } /* diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index f36366a..b06f86c 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -19,7 +19,7 @@ pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_SERR); /* Enable Bus Master */ - pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); /* Set Cache Line Size to 0x10 */ pci_write_config8(dev, PCI_CACHE_LINE_SIZE, CACHE_LINE_SIZE); diff --git a/src/soc/intel/common/block/scs/early_mmc.c b/src/soc/intel/common/block/scs/early_mmc.c index caee7d9..69d035d 100644 --- a/src/soc/intel/common/block/scs/early_mmc.c +++ b/src/soc/intel/common/block/scs/early_mmc.c @@ -31,8 +31,9 @@ { pci_write_config32(PCH_DEV_EMMC, PCI_BASE_ADDRESS_0, PRERAM_MMC_BASE_ADDRESS); - pci_write_config16(PCH_DEV_EMMC, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_write_config16(PCH_DEV_EMMC, PCI_COMMAND, PCI_COMMAND_MEMORY); + + pci_configure_bus_master(dev); } static void disable_mmc_controller_bar(void) diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index cc5e485..9a8eb1d 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -14,7 +14,7 @@ #include <soc/iomap.h> #include <soc/nvs.h> -#define UART_PCI_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER) +#define UART_PCI_ENABLE (PCI_COMMAND_MEMORY) #define UART_CONSOLE_INVALID_INDEX 0xFF extern const struct uart_gpio_pad_config uart_gpio_pads[]; @@ -68,6 +68,7 @@ /* Enable memory access and bus master */ pci_write_config16(dev, PCI_COMMAND, UART_PCI_ENABLE); + pci_configure_bus_master(dev); uart_lpss_init(device, baseaddr); } diff --git a/src/soc/intel/denverton_ns/bootblock/uart.c b/src/soc/intel/denverton_ns/bootblock/uart.c index 7514fee..e8b8c7a 100644 --- a/src/soc/intel/denverton_ns/bootblock/uart.c +++ b/src/soc/intel/denverton_ns/bootblock/uart.c @@ -42,7 +42,8 @@ #if (CONFIG(NON_LEGACY_UART_MODE)) PCI_COMMAND_MEMORY | #endif - PCI_COMMAND_MASTER | PCI_COMMAND_IO); + PCI_COMMAND_IO); + pci_configure_bus_master(dev); #if (CONFIG(CONSOLE_SERIAL_230400)) /* Change the highest speed to 230400 */ diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index 05c6484..8918c2d 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -452,8 +452,9 @@ /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_SPECIAL | PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + PCI_COMMAND_SPECIAL | PCI_COMMAND_MEMORY | + PCI_COMMAND_IO); + pci_configure_bus_master(dev); /* Serial IRQ initialization. */ pch_enable_serial_irqs(dev); diff --git a/src/soc/intel/denverton_ns/pmc.c b/src/soc/intel/denverton_ns/pmc.c index 25a0e59..92dbf59 100644 --- a/src/soc/intel/denverton_ns/pmc.c +++ b/src/soc/intel/denverton_ns/pmc.c @@ -40,9 +40,9 @@ pwrm_base = pci_read_config32(dev, PMC_PWRM_BASE) & MASK_PMC_PWRM_BASE; /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | - PCI_COMMAND_IO); + pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | + PCI_COMMAND_IO); + pci_configure_bus_master(dev); /* Setup power options. */ pch_power_options(dev); diff --git a/src/soc/intel/denverton_ns/sata.c b/src/soc/intel/denverton_ns/sata.c index d631117..0797cc3 100644 --- a/src/soc/intel/denverton_ns/sata.c +++ b/src/soc/intel/denverton_ns/sata.c @@ -23,9 +23,9 @@ /* SATA configuration is handled by the FSP */ /* Enable BARs */ - pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | - PCI_COMMAND_IO); + pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | + PCI_COMMAND_IO); + pci_configure_bus_master(dev); printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); diff --git a/src/soc/intel/denverton_ns/xhci.c b/src/soc/intel/denverton_ns/xhci.c index abdeb60..a6874ff 100644 --- a/src/soc/intel/denverton_ns/xhci.c +++ b/src/soc/intel/denverton_ns/xhci.c @@ -16,8 +16,8 @@ printk(BIOS_NOTICE, "pch: %s\n", __func__); /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_configure_bus_master(dev); } static struct device_operations usb_xhci_ops = { diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 43a88b7..4191a1a 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -97,8 +97,7 @@ write32(bar5 + HOST_CTL, val | HOST_CTL_AHCI_EN); } - dev->command |= PCI_COMMAND_MASTER; - pci_write_config8(dev, PCI_COMMAND, dev->command); + pci_configure_bus_master(dev); printk(BIOS_DEBUG, "AHCI/RAID controller initialized\n"); } diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index 4f5d8ca..530a896 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -261,7 +261,7 @@ } /* Set Bus Master */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); pci_write_config8(dev, 0x3c, 0x0a); // unused? diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 40b0cc2b..fd5f7d8 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -564,7 +564,8 @@ mei_base_address = (u32 *)(uintptr_t)res->base; /* Ensure Memory and Bus Master bits are set */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_configure_bus_master(dev); /* Clean up status for next message */ read_host_csr(&host); diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index e65b8e5..f03e91b 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -550,7 +550,8 @@ mei_base_address = (u32 *)(uintptr_t)res->base; /* Ensure Memory and Bus Master bits are set */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_configure_bus_master(dev); /* Clean up status for next message */ read_host_csr(&host); diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c index 895135b..2c90581 100644 --- a/src/southbridge/intel/bd82x6x/pci.c +++ b/src/southbridge/intel/bd82x6x/pci.c @@ -14,7 +14,7 @@ printk(BIOS_DEBUG, "PCI init.\n"); /* Enable Bus Master */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); /* This device has no interrupt */ pci_write_config8(dev, INTR, 0xff); diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index c381d33..663fc08 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -210,7 +210,7 @@ printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n"); /* Enable Bus Master */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); /* Set Cache Line Size to 0x10 */ // This has no effect but the OS might expect it diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c index 8bc45f6..496892a 100644 --- a/src/southbridge/intel/bd82x6x/usb_ehci.c +++ b/src/southbridge/intel/bd82x6x/usb_ehci.c @@ -30,7 +30,7 @@ pci_write_config32(dev, 0xfc, 0x205b1708); #endif - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); //pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); /* For others, done in MRC. */ diff --git a/src/southbridge/intel/i82801dx/usb.c b/src/southbridge/intel/i82801dx/usb.c index 2abfa8a..1c62372 100644 --- a/src/southbridge/intel/i82801dx/usb.c +++ b/src/southbridge/intel/i82801dx/usb.c @@ -11,7 +11,8 @@ { printk(BIOS_DEBUG, "USB: Setting up controller.. "); pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE); + PCI_COMMAND_INVALIDATE); + pci_configure_bus_master(dev); printk(BIOS_DEBUG, "done.\n"); } diff --git a/src/southbridge/intel/i82801dx/usb2.c b/src/southbridge/intel/i82801dx/usb2.c index e333bb6..508c1ee 100644 --- a/src/southbridge/intel/i82801dx/usb2.c +++ b/src/southbridge/intel/i82801dx/usb2.c @@ -12,7 +12,8 @@ { printk(BIOS_DEBUG, "USB: Setting up controller.. "); pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE); + PCI_COMMAND_INVALIDATE); + pci_configure_bus_master(dev); printk(BIOS_DEBUG, "done.\n"); } diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index 205fb0d..af0b0f2 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -229,7 +229,7 @@ pci_write_config32(dev, 0x120, reg32); /* Set Bus Master */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); pci_write_config8(dev, 0x3c, 0x0a); // unused? diff --git a/src/southbridge/intel/i82801gx/ide.c b/src/southbridge/intel/i82801gx/ide.c index 7fb489d..93d7177 100644 --- a/src/southbridge/intel/i82801gx/ide.c +++ b/src/southbridge/intel/i82801gx/ide.c @@ -29,7 +29,8 @@ enable_secondary = config->ide_enable_secondary; } - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MASTER); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); + pci_configure_bus_master(dev); /* Native Capable, but not enabled. */ pci_write_config8(dev, 0x09, 0x8a); diff --git a/src/southbridge/intel/i82801gx/pci.c b/src/southbridge/intel/i82801gx/pci.c index 7472438..363bfa6 100644 --- a/src/southbridge/intel/i82801gx/pci.c +++ b/src/southbridge/intel/i82801gx/pci.c @@ -13,9 +13,7 @@ u8 reg8; /* Enable Bus Master */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 |= PCI_COMMAND_MASTER; - pci_write_config16(dev, PCI_COMMAND, reg16); + pci_configure_bus_master(dev); /* This device has no interrupt */ pci_write_config8(dev, INTR, 0xff); diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c index adf0e49..b3223b4 100644 --- a/src/southbridge/intel/i82801gx/pcie.c +++ b/src/southbridge/intel/i82801gx/pcie.c @@ -46,7 +46,7 @@ printk(BIOS_DEBUG, "Initializing ICH7 PCIe bridge.\n"); /* Enable Bus Master */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); /* Set Cache Line Size to 0x10 */ // This has no effect but the OS might expect it diff --git a/src/southbridge/intel/i82801gx/usb.c b/src/southbridge/intel/i82801gx/usb.c index 8ce57df..791ae1d 100644 --- a/src/southbridge/intel/i82801gx/usb.c +++ b/src/southbridge/intel/i82801gx/usb.c @@ -14,7 +14,7 @@ /* USB Specification says the device must be Bus Master */ printk(BIOS_DEBUG, "UHCI: Setting up controller.. "); - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); // Erratum pci_write_config8(dev, 0xca, 0x00); diff --git a/src/southbridge/intel/i82801gx/usb_ehci.c b/src/southbridge/intel/i82801gx/usb_ehci.c index f665ab7..fe581e1 100644 --- a/src/southbridge/intel/i82801gx/usb_ehci.c +++ b/src/southbridge/intel/i82801gx/usb_ehci.c @@ -17,7 +17,8 @@ u8 reg8; printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_SERR); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); + pci_configure_bus_master(dev); reg32 = pci_read_config32(dev, 0xdc); reg32 |= (1 << 31) | (1 << 27); diff --git a/src/southbridge/intel/i82801ix/hdaudio.c b/src/southbridge/intel/i82801ix/hdaudio.c index 6f82cb4..487507e 100644 --- a/src/southbridge/intel/i82801ix/hdaudio.c +++ b/src/southbridge/intel/i82801ix/hdaudio.c @@ -229,7 +229,7 @@ pci_or_config32(dev, 0x120, (1 << 31) | (1 << 24) | (0x80 << 0)); /* VCi ID and map */ /* Set Bus Master */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); // Docking not supported pci_and_config8(dev, 0x4d, (u8)~(1 << 7)); // Docking Status diff --git a/src/southbridge/intel/i82801ix/pcie.c b/src/southbridge/intel/i82801ix/pcie.c index a8e7b11..6b07d8a 100644 --- a/src/southbridge/intel/i82801ix/pcie.c +++ b/src/southbridge/intel/i82801ix/pcie.c @@ -17,7 +17,7 @@ printk(BIOS_DEBUG, "Initializing ICH9 PCIe root port.\n"); /* Enable Bus Master */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); /* Set Cache Line Size to 0x10 */ // This has no effect but the OS might expect it diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c index cac0375..0621fdc 100644 --- a/src/southbridge/intel/i82801ix/sata.c +++ b/src/southbridge/intel/i82801ix/sata.c @@ -166,9 +166,9 @@ */ pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | /* read-only in IDE modes */ PCI_COMMAND_IO); + pci_configure_bus_master(dev); if (sata_mode != 0) /* No AHCI: clear AHCI base */ pci_write_config32(dev, PCI_BASE_ADDRESS_5, 0x00000000); diff --git a/src/southbridge/intel/i82801ix/usb_ehci.c b/src/southbridge/intel/i82801ix/usb_ehci.c index 64f23f6..6297f0e 100644 --- a/src/southbridge/intel/i82801ix/usb_ehci.c +++ b/src/southbridge/intel/i82801ix/usb_ehci.c @@ -11,7 +11,7 @@ static void usb_ehci_init(struct device *dev) { printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); printk(BIOS_DEBUG, "done.\n"); } diff --git a/src/southbridge/intel/i82801jx/hdaudio.c b/src/southbridge/intel/i82801jx/hdaudio.c index 4ba7828..68c3023 100644 --- a/src/southbridge/intel/i82801jx/hdaudio.c +++ b/src/southbridge/intel/i82801jx/hdaudio.c @@ -229,7 +229,7 @@ pci_or_config32(dev, 0x120, (1 << 31) | (1 << 24) | (0x80 << 0)); /* VCi ID and map */ /* Set Bus Master */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); // Docking not supported pci_and_config8(dev, 0x4d, (u8)~(1 << 7)); // Docking Status diff --git a/src/southbridge/intel/i82801jx/pcie.c b/src/southbridge/intel/i82801jx/pcie.c index 5195522..23649a1 100644 --- a/src/southbridge/intel/i82801jx/pcie.c +++ b/src/southbridge/intel/i82801jx/pcie.c @@ -17,7 +17,7 @@ printk(BIOS_DEBUG, "Initializing ICH10 PCIe root port.\n"); /* Enable Bus Master */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); /* Set Cache Line Size to 0x10 */ // This has no effect but the OS might expect it diff --git a/src/southbridge/intel/i82801jx/sata.c b/src/southbridge/intel/i82801jx/sata.c index 73a7d82..2bf6809 100644 --- a/src/southbridge/intel/i82801jx/sata.c +++ b/src/southbridge/intel/i82801jx/sata.c @@ -160,9 +160,9 @@ */ pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | /* read-only in IDE modes */ PCI_COMMAND_IO); + pci_configure_bus_master(dev); if (sata_mode != 0) /* No AHCI: clear AHCI base */ pci_write_config32(dev, PCI_BASE_ADDRESS_5, 0x00000000); diff --git a/src/southbridge/intel/i82801jx/usb_ehci.c b/src/southbridge/intel/i82801jx/usb_ehci.c index 893bb29..51c71a7 100644 --- a/src/southbridge/intel/i82801jx/usb_ehci.c +++ b/src/southbridge/intel/i82801jx/usb_ehci.c @@ -11,7 +11,7 @@ static void usb_ehci_init(struct device *dev) { printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); printk(BIOS_DEBUG, "done.\n"); } diff --git a/src/southbridge/intel/i82870/ioapic.c b/src/southbridge/intel/i82870/ioapic.c index 4763703..f544c73 100644 --- a/src/southbridge/intel/i82870/ioapic.c +++ b/src/southbridge/intel/i82870/ioapic.c @@ -13,9 +13,9 @@ static void p64h2_ioapic_enable(struct device *dev) { /* We have to enable MEM and Bus Master for IOAPIC */ - uint16_t command = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - + uint16_t command = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MEMORY; pci_write_config16(dev, PCI_COMMAND, command); + pci_configure_bus_master(dev); } /** diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index 59a384a..5a7a8cf 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -261,7 +261,7 @@ pci_write_config32(dev, 0xd0, reg32); /* Set Bus Master */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); pci_write_config8(dev, 0x3c, 0x0a); // unused? diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index 2c9c87c..f413ec3 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -487,8 +487,9 @@ /* Ensure Memory and Bus Master bits are set */ reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + reg16 |= PCI_COMMAND_MEMORY; pci_write_config16(dev, PCI_COMMAND, reg16); + pci_configure_bus_master(dev); /* Clean up status for next message */ read_host_csr(&host); diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c index 7ad9929..1be011e 100644 --- a/src/southbridge/intel/ibexpeak/usb_ehci.c +++ b/src/southbridge/intel/ibexpeak/usb_ehci.c @@ -29,7 +29,7 @@ pci_write_config32(dev, 0xf4, 0x00808588); pci_write_config32(dev, 0xfc, 0x301b1728); - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); access_cntl = pci_read_config8(dev, 0x80); diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c index f415170..0410cf5 100644 --- a/src/southbridge/intel/lynxpoint/azalia.c +++ b/src/southbridge/intel/lynxpoint/azalia.c @@ -125,7 +125,7 @@ printk(BIOS_DEBUG, "Azalia: base = %p\n", base); /* Set Bus Master */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); azalia_pch_init(dev, base); diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index aeab0c7..45f9c71 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -735,7 +735,8 @@ mei_base_address = (u32 *)(uintptr_t)res->base; /* Ensure Memory and Bus Master bits are set */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_configure_bus_master(dev); /* Clean up status for next message */ read_host_csr(&host); diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index d957e8d..f7308a5 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -659,7 +659,7 @@ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); /* Enable Bus Master */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); /* Set Cache Line Size to 0x10 */ // This has no effect but the OS might expect it diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index cdb1f35..03584c2 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -137,7 +137,8 @@ printk(BIOS_DEBUG, "Initializing Serial IO device\n"); /* Ensure memory and bus master are enabled */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_configure_bus_master(dev); /* Find BAR0 and BAR1 */ bar0 = find_resource(dev, PCI_BASE_ADDRESS_0); diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c index 52b3ed8..02ad4c0 100644 --- a/src/southbridge/intel/lynxpoint/usb_ehci.c +++ b/src/southbridge/intel/lynxpoint/usb_ehci.c @@ -72,7 +72,8 @@ /* Make sure memory space is enabled */ pci_write_config16(dev, PCI_COMMAND, pci_cmd | - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + PCI_COMMAND_MEMORY); + pci_configure_bus_master(dev); } /* -- To view, visit https://review.coreboot.org/c/coreboot/+/42460 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25565315a5ddf8d53097ac4cb4884ecebcc9c0a9 Gerrit-Change-Number: 42460 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

7 23

Change in coreboot[master]: uti/cbfstool: Add option --pow2page
by Kyösti Mälkki (Code Review) 17 Jun '21

17 Jun '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41832 ) Change subject: uti/cbfstool: Add option --pow2page ...................................................................... uti/cbfstool: Add option --pow2page For add-stage command, --pow2page is equivalent of passing -P log2ceil(sizeof stage). The sizeof stage can be hard to determine in Makefile to be passed on the commandline. Change-Id: If4b5329c1df5afe49d27ab10220095d747024ad6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M util/cbfstool/cbfstool.c 1 file changed, 15 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/41832/1 diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 4ec8c90..dd87a04 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -65,6 +65,7 @@ bool fill_partial_downward; bool show_immutable; bool stage_xip; + bool force_pow2_pagesize; bool autogen_attr; bool machine_parseable; bool unprocessed; @@ -169,6 +170,14 @@ DEBUG("File size is %zd (0x%zx)\n", data_size, data_size); + /* Use a page size that can fit the entire file. */ + if (param.force_pow2_pagesize) { + param.pagesize = 1; + while (param.pagesize < data_size) + param.pagesize <<= 1; + DEBUG("Page size is %d (0x%x)\n", param.pagesize, param.pagesize); + } + /* Include cbfs_file size along with space for with name. */ metadata_size += cbfs_calculate_file_header_size(param.name); /* Adjust metadata_size if additional attributes were added */ @@ -1259,7 +1268,7 @@ true, true}, {"add-payload", "H:r:f:n:c:b:C:I:p:vA:gh?", cbfs_add_payload, true, true}, - {"add-stage", "a:H:r:f:n:t:c:b:P:S:p:yvA:gh?", cbfs_add_stage, + {"add-stage", "a:H:r:f:n:t:c:b:P:Q:S:p:yvA:gh?", cbfs_add_stage, true, true}, {"add-int", "H:r:i:n:b:vgh?", cbfs_add_integer, true, true}, {"add-master-header", "H:r:vh?j:", cbfs_add_master_header, true, true}, @@ -1311,6 +1320,7 @@ {"offset", required_argument, 0, 'o' }, {"padding", required_argument, 0, 'p' }, {"page-size", required_argument, 0, 'P' }, + {"pow2page", no_argument, 0, 'Q' }, {"ucode-region", required_argument, 0, 'q' }, {"size", required_argument, 0, 's' }, {"top-aligned", required_argument, 0, 'T' }, @@ -1405,7 +1415,7 @@ "Add a payload to the ROM\n" " add-stage [-r image,regions] -f FILE -n NAME [-A hash] \\\n" " [-c compression] [-b base] [-S section-to-ignore] \\\n" - " [-a alignment] [-y|--xip] [-P page-size] [--ibb] " + " [-a alignment] [-y|--xip] [-P page-size] [-Q] [--ibb] " "Add a stage to the ROM\n" " add-flat-binary [-r image,regions] -f FILE -n NAME \\\n" " [-A hash] -l load-address -e entry-point \\\n" @@ -1664,6 +1674,9 @@ return 1; } break; + case 'Q': + param.force_pow2_pagesize = 1; + break; case 'o': param.cbfsoffset = strtoul(optarg, &suffix, 0); if (!*optarg || (suffix && *suffix)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/41832 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4b5329c1df5afe49d27ab10220095d747024ad6 Gerrit-Change-Number: 41832 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: Add support for USB Type-C ports
by John Zhao (Code Review) 15 Jun '21

15 Jun '21

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40425 ) Change subject: mb/google/volteer: Add support for USB Type-C ports ...................................................................... mb/google/volteer: Add support for USB Type-C ports Two usb type-c ports under the actual Mux device. Each port has its own ACPI device entry (node). These nodes are the ones that the USB Type-C port/connnector devices will refer to in order to configure the mux. BUG=b:151646486 BRANCH=None TEST=Verify USB Type-C alternate mode (DP or TBT) along wth PMC control. Change-Id: I4b443a1ca1c5361652a69586b340b1c95e9c3f06 Signed-off-by: John Zhao <john.zhao(a)intel.com> --- A src/mainboard/google/volteer/acpi/usbc.asl M src/mainboard/google/volteer/dsdt.asl 2 files changed, 46 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/40425/1 diff --git a/src/mainboard/google/volteer/acpi/usbc.asl b/src/mainboard/google/volteer/acpi/usbc.asl new file mode 100644 index 0000000..b185b2f --- /dev/null +++ b/src/mainboard/google/volteer/acpi/usbc.asl @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +Scope (\_SB.PCI0.PMC.MUX) { + /* + * Mux driver looks for usb type-C devices underneath it through + * _DSD and _ADR, where _ADR specifies the device address on the + * parent bus. CON0 is representing the first type-C port and CON1 + * is representing the second. + */ + Device (CON0) + { + Name (_ADR, 0) + /* + * These properties should have the values that the driver needs + * to supply to the PMC via IPC when the muxes are being + * configured. + */ + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package() { + Package () { "usb2-port", 6 }, + Package () { "usb3-port", 3 }, + Package () { "sbu-orientation", "normal" }, + Package () { "hsl-orientation", "normal" }, + }, + }) + } + + Device (CON1) + { + Name (_ADR, 1) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package() { + Package () { "usb2-port", 5 }, + Package () { "usb3-port", 2 }, + Package () { "sbu-orientation", "normal" }, + Package () { "hsl-orientation", "normal" }, + }, + }) + } +} diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl index 640f7cd..1888267 100644 --- a/src/mainboard/google/volteer/dsdt.asl +++ b/src/mainboard/google/volteer/dsdt.asl @@ -50,4 +50,7 @@ /* Camera */ #include <soc/intel/tigerlake/acpi/ipu.asl> #include "acpi/mipi_camera.asl" + + /* usbc */ + #include "acpi/usbc.asl" } -- To view, visit https://review.coreboot.org/c/coreboot/+/40425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b443a1ca1c5361652a69586b340b1c95e9c3f06 Gerrit-Change-Number: 40425 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP, HACK] broadwell: make uart support build again
by Angel Pons (Code Review) 14 Jun '21

14 Jun '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37553 ) Change subject: [WIP, HACK] broadwell: make uart support build again ...................................................................... [WIP, HACK] broadwell: make uart support build again @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ @ @ @ DO NOT MERGE AS-IS! @ @ @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ I am fully aware this is an atrociously hideous kludge. Moreover, this change won't be properly build-tested by Mr. Jenkins, and it has not been tested on real hardware either. It only exists for backup purposes. Change-Id: I527024098738700d5fbaf3e27cf4db331a0322bd Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/Makefile.inc M src/soc/intel/broadwell/romstage/uart.c M src/soc/intel/broadwell/serialio.c 3 files changed, 17 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/37553/1 diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 03aa3fb..61b62c8 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -9,6 +9,7 @@ subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/common +bootblock-y += romstage/uart.c bootblock-y += bootblock/cpu.c bootblock-y += bootblock/pch.c bootblock-y += bootblock/systemagent.c @@ -16,6 +17,9 @@ bootblock-y += ../../../cpu/intel/car/non-evict/cache_as_ram.S bootblock-y += ../../../cpu/x86/early_reset.S +postcar-y += romstage/uart.c +ramstage-y += romstage/uart.c + ramstage-y += acpi.c ramstage-y += adsp.c ramstage-y += chip.c diff --git a/src/soc/intel/broadwell/romstage/uart.c b/src/soc/intel/broadwell/romstage/uart.c index a1a29b6..43c62a9 100644 --- a/src/soc/intel/broadwell/romstage/uart.c +++ b/src/soc/intel/broadwell/romstage/uart.c @@ -14,13 +14,15 @@ */ #include <device/pci_def.h> +#include <console/uart.h> #include <reg_script.h> #include <stdint.h> -#include <uart8250.h> #include <soc/iobp.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> #include <soc/serialio.h> -const struct reg_script uart_init[] = { +const struct reg_script uart_init_script[] = { /* Set MMIO BAR */ REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, CONFIG_TTYS0_BASE), /* Enable Memory access and Bus Master */ @@ -41,6 +43,11 @@ REG_SCRIPT_END }; +uintptr_t uart_platform_base(int idx) +{ + return CONFIG_TTYS0_BASE; +} + void pch_uart_init(void) { /* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b */ @@ -72,11 +79,11 @@ pch_iobp_update(0xcb000180, ~0x0000003f, 0x0000003f); /* Initialize chipset uart interface */ - reg_script_run_on_dev(dev, uart_init); + reg_script_run_on_dev(dev, uart_init_script); /* * Perform standard UART initialization * Divisor 1 is 115200 BAUD */ - uart8250_mem_init(CONFIG_TTYS0_BASE, 1); + uart_init(0); } diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c index 161c875..50daa3f 100644 --- a/src/soc/intel/broadwell/serialio.c +++ b/src/soc/intel/broadwell/serialio.c @@ -282,7 +282,8 @@ if (serialio_uart_is_debug(dev)) { struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) - uartmem_setbaseaddr(res->base); + printk(BIOS_ERR, "UART base address changed\n"); + //uartmem_setbaseaddr(res->base); } #endif } -- To view, visit https://review.coreboot.org/c/coreboot/+/37553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I527024098738700d5fbaf3e27cf4db331a0322bd Gerrit-Change-Number: 37553 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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