Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36696 )
Change subject: arch/x86/car.ld: Use REGION macro
......................................................................
arch/x86/car.ld: Use REGION macro
The advantages of using the REGION macro:
- less boilerplate for defining start and end symbols
- overlap between regions checking
- automatic alignment
Change-Id: I9c327343eb40d3e2cc8513354ec3a83d803ff1ee
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/arch/x86/car.ld
1 file changed, 4 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/36696/1
diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld
index 74fc74b..c601d2e 100644
--- a/src/arch/x86/car.ld
+++ b/src/arch/x86/car.ld
@@ -18,9 +18,7 @@
#if CONFIG(PAGING_IN_CACHE_AS_RAM)
/* Page table pre-allocation. CONFIG_DCACHE_RAM_BASE should be 4KiB
* aligned when using this option. */
- _pagetables = . ;
- . += 4096 * CONFIG_NUM_CAR_PAGE_TABLE_PAGES;
- _epagetables = . ;
+ REGION(pagetables, ., 4096 * CONFIG_NUM_CAR_PAGE_TABLE_PAGES, 4096)
#endif
/* Vboot work buffer only needs to be available when verified boot
* starts in bootblock. */
@@ -37,9 +35,7 @@
* use CAR it can be reused. The chipset/SoC is expected to provide
* the stack size. */
#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
- _car_stack = .;
- . += CONFIG_DCACHE_BSP_STACK_SIZE;
- _ecar_stack = .;
+ REGION(car_stack, ., CONFIG_DCACHE_BSP_STACK_SIZE, 16)
#endif
/* The pre-ram cbmem console as well as the timestamp region are fixed
* in size. Therefore place them above the car global section so that
@@ -47,22 +43,17 @@
* link address of these shared objects. */
PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE)
#if CONFIG(PAGING_IN_CACHE_AS_RAM)
- . = ALIGN(32);
/* Page directory pointer table resides here. There are 4 8-byte entries
* totalling 32 bytes that need to be 32-byte aligned. The reason the
* pdpt are not colocated with the rest of the page tables is to reduce
* fragmentation of the CAR space that persists across stages. */
- _pdpt = .;
- . += 32;
- _epdpt = .;
+ REGION(pdpt, ., 32, 32)
#endif
TIMESTAMP(., 0x200)
- _car_ehci_dbg_info = .;
/* Reserve sizeof(struct ehci_dbg_info). */
- . += 80;
- _ecar_ehci_dbg_info = .;
+ REGION(car_ehci_dbg_info, ., 80, ARCH_POINTER_ALIGN_SIZE)
/* _bss and _ebss provide symbols to per-stage
* variables that are not shared like the timestamp and the pre-ram
@@ -114,9 +105,6 @@
}
_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
-#if CONFIG(PAGING_IN_CACHE_AS_RAM)
-_bogus2 = ASSERT(_pagetables == ALIGN(_pagetables, 4096), "_pagetables aren't 4KiB aligned");
-#endif
#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
_bogus3 = ASSERT(CONFIG_DCACHE_BSP_STACK_SIZE > 0x0, "BSP stack size not configured");
#endif
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I9c327343eb40d3e2cc8513354ec3a83d803ff1ee
Gerrit-Change-Number: 36696
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-MessageType: newchange
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37279 )
Change subject: src/soc/intel/fsp-car: Align stack before jumping to C code
......................................................................
src/soc/intel/fsp-car: Align stack before jumping to C code
GCC has had a 16 byte stack requirement since quite some time now...
Change-Id: I0f5b62b5fef3ca7ec6d9010723527a356eb566ed
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/37279/1
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
index d7ef834..4174f36 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
@@ -99,6 +99,10 @@
xorl %eax, %eax
rep stosl
+ /* Need to align stack to 16 bytes at call instruction. Account for
+ the two pushes below. */
+ andl $0xfffffff0, %esp
+ sub $8, %esp
/* Restore the timestamp from bootblock_crt0.S (ebp:mm1) */
push %ebp
movd %mm1, %eax
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I0f5b62b5fef3ca7ec6d9010723527a356eb566ed
Gerrit-Change-Number: 37279
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newchange
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37277 )
Change subject: soc/intel/fsp-car: Clear the whole usable CAR region
......................................................................
soc/intel/fsp-car: Clear the whole usable CAR region
Other symbols in car.ld likely expect to be zero initialized.
Change-Id: I44a0d3947eb6dd67dfd2d7f03e5c0766b043f61b
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
1 file changed, 6 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/37277/1
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
index 091fc4a..ec43311 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
@@ -89,13 +89,14 @@
/* Setup bootblock stack */
mov %edx, %esp
- /* clear .bss section as it is not shared */
+ /* coreboot assumes CAR region will be zero */
cld
- xor %eax, %eax
- movl $(_ebss), %ecx
- movl $(_bss), %edi
- sub %edi, %ecx
+ movl %ecx, %edi
+ neg %ecx
+ /* Clear up to Temp Ram top. */
+ add %edx, %ecx
shrl $2, %ecx
+ xorl %eax, %eax
rep stosl
/* Restore the timestamp from bootblock_crt0.S (ebp:mm1) */
--
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Gerrit-Change-Id: I44a0d3947eb6dd67dfd2d7f03e5c0766b043f61b
Gerrit-Change-Number: 37277
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-MessageType: newchange
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37276 )
Change subject: drivers/intel/fsp1.1: Use the coreboot symbols for the stack
......................................................................
drivers/intel/fsp1.1: Use the coreboot symbols for the stack
We want to know where the stack is, to make sure that it does not
override other CAR symbols.
Change-Id: I9edf615bff11aa38fc307b4e2e2c97f1757a05a1
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/drivers/intel/fsp1_1/cache_as_ram.S
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/37276/1
diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S
index fea7acb..fb39884 100644
--- a/src/drivers/intel/fsp1_1/cache_as_ram.S
+++ b/src/drivers/intel/fsp1_1/cache_as_ram.S
@@ -143,8 +143,8 @@
cmp $0, %eax
jne halt2
- /* Setup bootloader stack */
- movl %edx, %esp
+ /* Setup BSP stack */
+ movl _ecar_stack, %esp
/*
* ebp: FSP_INFO_HEADER address
--
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