coreboot-gerrit April 2020

coreboot-gerrit@coreboot.org

1 participants
2501 discussions

Change in coreboot[master]: mb/asus/p2-99: add Asus P2-99 as a variant of Asus P2B
by Branden Waldner (Code Review) 10 Jun '23

10 Jun '23

Branden Waldner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35530 ) Change subject: mb/asus/p2-99: add Asus P2-99 as a variant of Asus P2B ...................................................................... mb/asus/p2-99: add Asus P2-99 as a variant of Asus P2B Squash add Asus P2-99 as clone of Asus P2B and convert clone to variant Change-Id: I78bd3e215c9c35d272919850f52feac135d06ed8 --- M src/mainboard/asus/p2b/Kconfig M src/mainboard/asus/p2b/Kconfig.name 2 files changed, 11 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/35530/1 diff --git a/src/mainboard/asus/p2b/Kconfig b/src/mainboard/asus/p2b/Kconfig index f34b4dd..0c77779 100644 --- a/src/mainboard/asus/p2b/Kconfig +++ b/src/mainboard/asus/p2b/Kconfig @@ -12,7 +12,7 @@ ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## -if BOARD_ASUS_P2B +if BOARD_ASUS_P2B || BOARD_ASUS_P2_99 config BOARD_SPECIFIC_OPTIONS def_bool y @@ -28,12 +28,18 @@ string default asus/p2b +config VARIANT_DIR + string + default "p2-99" if BOARD_ASUS_P2_99 + default "p2b" if BOARD_ASUS_P2B + config MAINBOARD_PART_NUMBER string + default "P2-99" if BOARD_ASUS_P2_99 default "P2B" config IRQ_SLOT_COUNT int default 6 -endif # BOARD_ASUS_P2B +endif # BOARD_ASUS_P2B || BOARD_ASUS_P2_99 diff --git a/src/mainboard/asus/p2b/Kconfig.name b/src/mainboard/asus/p2b/Kconfig.name index 60d6028..a299a35 100644 --- a/src/mainboard/asus/p2b/Kconfig.name +++ b/src/mainboard/asus/p2b/Kconfig.name @@ -1,2 +1,5 @@ config BOARD_ASUS_P2B bool "P2B" + +config BOARD_ASUS_P2_99 + bool "P2-99" -- To view, visit https://review.coreboot.org/c/coreboot/+/35530 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78bd3e215c9c35d272919850f52feac135d06ed8 Gerrit-Change-Number: 35530 Gerrit-PatchSet: 1 Gerrit-Owner: Branden Waldner <scruffy99(a)gmail.com> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: [WIP] Add Multiple Segment support
by Subrata Banik (Code Review) 10 Jun '23

10 Jun '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40722 ) Change subject: [WIP] Add Multiple Segment support ...................................................................... [WIP] Add Multiple Segment support Test Patch for get feedback on design aspect Change-Id: Ide7e97aa7c48fd0e993b248b38b2ad6ad94a21cb Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/intel/tglrvp/dsdt.asl M src/soc/intel/apollolake/systemagent.c M src/soc/intel/cannonlake/systemagent.c M src/soc/intel/common/block/acpi/acpi.c A src/soc/intel/common/block/acpi/acpi/extrahostbridge.asl A src/soc/intel/common/block/acpi/acpi/pcisegment.asl M src/soc/intel/common/block/include/intelblocks/systemagent.h M src/soc/intel/common/block/systemagent/Kconfig M src/soc/intel/common/block/systemagent/systemagent_def.h M src/soc/intel/common/block/systemagent/systemagent_early.c A src/soc/intel/common/block/tcss/Kconfig M src/soc/intel/icelake/systemagent.c M src/soc/intel/jasperlake/systemagent.c M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/systemagent.c M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/acpi/pci_irqs.asl M src/soc/intel/tigerlake/include/soc/irq.h M src/soc/intel/tigerlake/systemagent.c 19 files changed, 195 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/40722/1 diff --git a/src/mainboard/intel/tglrvp/dsdt.asl b/src/mainboard/intel/tglrvp/dsdt.asl index af13d9f..c531baa 100644 --- a/src/mainboard/intel/tglrvp/dsdt.asl +++ b/src/mainboard/intel/tglrvp/dsdt.asl @@ -28,6 +28,9 @@ #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/tigerlake/acpi/southbridge.asl> } + #if CONFIG_SA_PCI_SEGMENT_GROUPS > 1 + #include <soc/intel/common/block/acpi/acpi/pcisegment.asl> + #endif } #if CONFIG(CHROMEOS) diff --git a/src/soc/intel/apollolake/systemagent.c b/src/soc/intel/apollolake/systemagent.c index a1b6b4d..a15200b 100644 --- a/src/soc/intel/apollolake/systemagent.c +++ b/src/soc/intel/apollolake/systemagent.c @@ -31,7 +31,8 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index) { static const struct sa_mmio_descriptor soc_fixed_resources[] = { - { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, + { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, + PCIEXBAR_LENGTH_MiB(CONFIG_SA_PCI_SEGMENT_GROUPS), "PCIEXBAR" }, { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, }; diff --git a/src/soc/intel/cannonlake/systemagent.c b/src/soc/intel/cannonlake/systemagent.c index 1ab365e..9d7e40e 100644 --- a/src/soc/intel/cannonlake/systemagent.c +++ b/src/soc/intel/cannonlake/systemagent.c @@ -20,7 +20,8 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index) { static const struct sa_mmio_descriptor soc_fixed_resources[] = { - { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, + { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, + PCIEXBAR_LENGTH_MiB(CONFIG_SA_PCI_SEGMENT_GROUPS), "PCIEXBAR" }, { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index fe127a2..9b0457f 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -35,10 +35,13 @@ __attribute__((weak)) unsigned long acpi_fill_mcfg(unsigned long current) { - /* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */ - current += acpi_create_mcfg_mmconfig((void *)current, - CONFIG_MMCONF_BASE_ADDRESS, 0, 0, - (CONFIG_SA_PCIEX_LENGTH >> 20) - 1); + /* + * PCI Segment Group depends on CONFIG_SA_PCI_SEGMENT_GROUPS, + * Start Bus Number 0, End Bus Number is 255 + */ + for (int i = 0; i < CONFIG_SA_PCI_SEGMENT_GROUPS; i++) + current += acpi_create_mcfg_mmconfig((void *)current, + CONFIG_MMCONF_BASE_ADDRESS, i, 0, 255); return current; } diff --git a/src/soc/intel/common/block/acpi/acpi/extrahostbridge.asl b/src/soc/intel/common/block/acpi/acpi/extrahostbridge.asl new file mode 100644 index 0000000..77c0248 --- /dev/null +++ b/src/soc/intel/common/block/acpi/acpi/extrahostbridge.asl @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method (_CRS, 0, Serialized) +{ + Name (MCRS, ResourceTemplate () + { + /* Bus Numbers */ + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100) + + /* IO Region 0 */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, + EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8) + + /* IO Region 1 */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, + EntireRange, + 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300) + + /* PCI Memory Region (TLUD - 0xdfffffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0x00000000, 0xdfffffff, 0x00000000, + 0xE0000000,,, PM01) + + /* PCI Memory Region (TUUD - (TUUD + ABOVE_4G_MMIO_SIZE)) */ + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0x10000, 0x1ffff, 0x00000000, + 0x10000,,, PM02) + }) + + /* Find PCI resource area in MCRS */ + CreateDwordField (MCRS, PM01._MIN, PMIN) + CreateDwordField (MCRS, PM01._MAX, PMAX) + CreateDwordField (MCRS, PM01._LEN, PLEN) + + /* + * Fix up PCI memory region + * Start with Top of Lower Usable DRAM + */ + Store (\_SB.PCI0.MCHC.TLUD, PMIN) + Add (Subtract (PMAX, PMIN), 1, PLEN) + + /* Patch PM02 range based on Memory Size */ + If (LEqual (A4GS, 0)) { + CreateQwordField (MCRS, PM02._LEN, MSEN) + Store (0, MSEN) + } Else { + CreateQwordField (MCRS, PM02._MIN, MMIN) + CreateQwordField (MCRS, PM02._MAX, MMAX) + CreateQwordField (MCRS, PM02._LEN, MLEN) + /* Set 64bit MMIO resource base and length */ + Store (A4GS, MLEN) + Store (A4GB, MMIN) + Subtract (Add (MMIN, MLEN), 1, MMAX) + } + + Return (MCRS) +} diff --git a/src/soc/intel/common/block/acpi/acpi/pcisegment.asl b/src/soc/intel/common/block/acpi/acpi/pcisegment.asl new file mode 100644 index 0000000..4efaf20 --- /dev/null +++ b/src/soc/intel/common/block/acpi/acpi/pcisegment.asl @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define TBT_PCIe0_IRQ 16 +#define TBT_PCIe1_IRQ 17 +#define TBT_PCIe2_IRQ 18 +#define TBT_PCIe3_IRQ 19 + +Device (PCI1) +{ + Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID + Name (_SEG, 1) // _SEG: PCI Segment + Name (_UID, 1) // _UID: Unique ID + Name (_ADR, 0x00000000) + + Name (PICN, Package () { + /* SEG1: PCIe Root Port*/ + Package(){0x0007FFFF, 0, 0, 11 }, + Package(){0x0007FFFF, 1, 0, 10 }, + Package(){0x0007FFFF, 2, 0, 11 }, + Package(){0x0007FFFF, 3, 0, 11 }, + }) + + Name (PICP, Package () { + /* SEG1: PCIe Root Port*/ + Package(){0x0007FFFF, 0, 0, TBT_PCIe0_IRQ }, + Package(){0x0007FFFF, 1, 0, TBT_PCIe1_IRQ }, + Package(){0x0007FFFF, 2, 0, TBT_PCIe2_IRQ }, + Package(){0x0007FFFF, 3, 0, TBT_PCIe3_IRQ }, + }) + + Method (_PRT) + { + If (PICM) { + Return (PICP) + } Else { + Return (PICN) + } + } + #include "extrahostbridge.asl" +} diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h index c6aa4b4..cfa96e3 100644 --- a/src/soc/intel/common/block/include/intelblocks/systemagent.h +++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h @@ -4,11 +4,14 @@ #ifndef SOC_INTEL_COMMON_BLOCK_SA_H #define SOC_INTEL_COMMON_BLOCK_SA_H +#include <commonlib/helpers.h> #include <device/device.h> #include <soc/iomap.h> #include <soc/nvs.h> #include <stddef.h> +#define PCIEXBAR_LENGTH_MiB(x) (x * 256 * MiB) + /* Device 0:0.0 PCI configuration space */ #define MCHBAR 0x48 #define PCIEXBAR 0x60 diff --git a/src/soc/intel/common/block/systemagent/Kconfig b/src/soc/intel/common/block/systemagent/Kconfig index 6dd1f3b..759abc9 100644 --- a/src/soc/intel/common/block/systemagent/Kconfig +++ b/src/soc/intel/common/block/systemagent/Kconfig @@ -9,23 +9,18 @@ hex default 0xe0000000 -config SA_PCIEX_LENGTH +config SA_PCI_SEGMENT_GROUPS hex - default 0x10000000 if (PCIEX_LENGTH_256MB) - default 0x8000000 if (PCIEX_LENGTH_128MB) - default 0x4000000 if (PCIEX_LENGTH_64MB) - default 0x10000000 + default 1 + default 2 if TCSS_PCIE_SEGMENT help - This option allows you to select length of PCIEX region. + This option allows you to select required PCI segment. -config PCIEX_LENGTH_256MB - bool - -config PCIEX_LENGTH_128MB - bool - -config PCIEX_LENGTH_64MB - bool + Each PCI segment supports up to 256 buses (0-255). + PCIE length selection is depends on PCI_SEGMENT_GROUPS. + Formula for PCIE Length = PCI_SEGMENT_GROUPS * 256 MB + If PCI segment is 1 then length of PCIEX region is 256MB to support 256 buses + else PCIEX region would be multiple of 256MB based on PCI_SEGMENT_GROUPS. config SA_ENABLE_IMR bool diff --git a/src/soc/intel/common/block/systemagent/systemagent_def.h b/src/soc/intel/common/block/systemagent/systemagent_def.h index 03f4de4..ef2f7b4 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_def.h +++ b/src/soc/intel/common/block/systemagent/systemagent_def.h @@ -4,7 +4,6 @@ #ifndef SOC_INTEL_COMMON_BLOCK_SA_DEF_H #define SOC_INTEL_COMMON_BLOCK_SA_DEF_H - /* Device 0:0.0 PCI configuration space */ /* GMCH Graphics Control Register */ @@ -19,8 +18,10 @@ #define DPR_PRS (1 << 1) #define DPR_SIZE_MASK 0xff0 -#define PCIEXBAR_LENGTH_64MB 2 -#define PCIEXBAR_LENGTH_128MB 1 +#define PCIEXBAR_LENGTH_4096MB 6 +#define PCIEXBAR_LENGTH_2048MB 5 +#define PCIEXBAR_LENGTH_1024MB 4 +#define PCIEXBAR_LENGTH_512MB 3 #define PCIEXBAR_LENGTH_256MB 0 #define PCIEXBAR_PCIEXBAREN (1 << 0) diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index cb0ed34..69b36f8 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -27,15 +27,21 @@ pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, reg); /* Get PCI Express Region Length */ - switch (CONFIG_SA_PCIEX_LENGTH) { - case 256 * MiB: + switch (CONFIG_SA_PCI_SEGMENT_GROUPS) { + case 1: pciexbar_length = PCIEXBAR_LENGTH_256MB; break; - case 128 * MiB: - pciexbar_length = PCIEXBAR_LENGTH_128MB; + case 2: + pciexbar_length = PCIEXBAR_LENGTH_512MB; break; - case 64 * MiB: - pciexbar_length = PCIEXBAR_LENGTH_64MB; + case 4: + pciexbar_length = PCIEXBAR_LENGTH_1024MB; + break; + case 8: + pciexbar_length = PCIEXBAR_LENGTH_2048MB; + break; + case 16: + pciexbar_length = PCIEXBAR_LENGTH_4096MB; break; default: pciexbar_length = PCIEXBAR_LENGTH_256MB; diff --git a/src/soc/intel/common/block/tcss/Kconfig b/src/soc/intel/common/block/tcss/Kconfig new file mode 100644 index 0000000..0f7fe7c --- /dev/null +++ b/src/soc/intel/common/block/tcss/Kconfig @@ -0,0 +1,9 @@ +config SOC_INTEL_COMMON_BLOCK_TCSS + bool + help + Intel Processor common TCSS support + +config TCSS_PCIE_SEGMENT + bool + help + Indicate the extra PCIE segment is required for iTBT or not diff --git a/src/soc/intel/icelake/systemagent.c b/src/soc/intel/icelake/systemagent.c index c07fd0a..6cf6354 100644 --- a/src/soc/intel/icelake/systemagent.c +++ b/src/soc/intel/icelake/systemagent.c @@ -16,7 +16,8 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index) { static const struct sa_mmio_descriptor soc_fixed_resources[] = { - { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, + { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, + PCIEXBAR_LENGTH_MiB(CONFIG_SA_PCI_SEGMENT_GROUPS), "PCIEXBAR" }, { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, diff --git a/src/soc/intel/jasperlake/systemagent.c b/src/soc/intel/jasperlake/systemagent.c index 7be471a..4c5efe7 100644 --- a/src/soc/intel/jasperlake/systemagent.c +++ b/src/soc/intel/jasperlake/systemagent.c @@ -17,7 +17,8 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index) { static const struct sa_mmio_descriptor soc_fixed_resources[] = { - { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, + { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, + PCIEXBAR_LENGTH_MiB(CONFIG_SA_PCI_SEGMENT_GROUPS), "PCIEXBAR" }, { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 75f6b69..5d95029 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -200,9 +200,13 @@ unsigned long acpi_fill_mcfg(unsigned long current) { - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, - CONFIG_MMCONF_BASE_ADDRESS, 0, 0, - (CONFIG_SA_PCIEX_LENGTH >> 20) - 1); + /* + * PCI Segment Group depends on CONFIG_SA_PCI_SEGMENT_GROUPS, + * Start Bus Number 0, End Bus Number is 255 + */ + for (int i = 0; i < CONFIG_SA_PCI_SEGMENT_GROUPS; i++) + current += acpi_create_mcfg_mmconfig((void *)current, + CONFIG_MMCONF_BASE_ADDRESS, i, 0, 255); return current; } diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c index 9a4c4de..a71dbb2 100644 --- a/src/soc/intel/skylake/systemagent.c +++ b/src/soc/intel/skylake/systemagent.c @@ -31,7 +31,8 @@ struct device *const igd_dev = pcidev_path_on_root(SA_DEVFN_IGD); static const struct sa_mmio_descriptor soc_fixed_resources[] = { - { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, + { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, + PCIEXBAR_LENGTH_MiB(CONFIG_SA_PCI_SEGMENT_GROUPS), "PCIEXBAR" }, { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index a690acf..93f12f9 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -60,6 +60,7 @@ select UDK_2017_BINDING select DISPLAY_FSP_VERSION_INFO select HECI_DISABLE_USING_SMM + select TCSS_PCIE_SEGMENT config DCACHE_RAM_BASE default 0xfef00000 diff --git a/src/soc/intel/tigerlake/acpi/pci_irqs.asl b/src/soc/intel/tigerlake/acpi/pci_irqs.asl index 62520b1..7603362 100644 --- a/src/soc/intel/tigerlake/acpi/pci_irqs.asl +++ b/src/soc/intel/tigerlake/acpi/pci_irqs.asl @@ -73,11 +73,6 @@ Package(){0x000DFFFF, 1, 0, xDCI_IRQ }, /* D8: GNA */ Package(){0x0008FFFF, 0, 0, GNA_IRQ }, - /* D7: TBT PCIe */ - Package(){0x0007FFFF, 0, 0, TBT_PCIe0_IRQ }, - Package(){0x0007FFFF, 1, 0, TBT_PCIe1_IRQ }, - Package(){0x0007FFFF, 2, 0, TBT_PCIe2_IRQ }, - Package(){0x0007FFFF, 3, 0, TBT_PCIe3_IRQ }, /* D6: PEG60 */ Package(){0x0006FFFF, 0, 0, PEG_IRQ }, /* D5: IPU Device */ @@ -142,11 +137,6 @@ Package(){0x000DFFFF, 1, 0, 10 }, /* D8: GNA */ Package(){0x0008FFFF, 0, 0, 11 }, - /* D7: TBT PCIe */ - Package(){0x0007FFFF, 0, 0, 11 }, - Package(){0x0007FFFF, 1, 0, 10 }, - Package(){0x0007FFFF, 2, 0, 11 }, - Package(){0x0007FFFF, 3, 0, 11 }, /* D6: PEG60 */ Package(){0x0006FFFF, 0, 0, 11 }, /* D5: IPU Device */ diff --git a/src/soc/intel/tigerlake/include/soc/irq.h b/src/soc/intel/tigerlake/include/soc/irq.h index 01ee10b..1057f91 100644 --- a/src/soc/intel/tigerlake/include/soc/irq.h +++ b/src/soc/intel/tigerlake/include/soc/irq.h @@ -54,11 +54,6 @@ #define ISH_IRQ 16 -#define TBT_PCIe0_IRQ 16 -#define TBT_PCIe1_IRQ 17 -#define TBT_PCIe2_IRQ 18 -#define TBT_PCIe3_IRQ 19 - #define HECI_1_IRQ 16 #define HECI_2_IRQ 17 #define HECI_3_IRQ 16 diff --git a/src/soc/intel/tigerlake/systemagent.c b/src/soc/intel/tigerlake/systemagent.c index 8859386..a6d7ae8 100644 --- a/src/soc/intel/tigerlake/systemagent.c +++ b/src/soc/intel/tigerlake/systemagent.c @@ -23,7 +23,8 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index) { static const struct sa_mmio_descriptor soc_fixed_resources[] = { - { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, + { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, + PCIEXBAR_LENGTH_MiB(CONFIG_SA_PCI_SEGMENT_GROUPS), "PCIEXBAR" }, { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, -- To view, visit https://review.coreboot.org/c/coreboot/+/40722 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide7e97aa7c48fd0e993b248b38b2ad6ad94a21cb Gerrit-Change-Number: 40722 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

5 16

Change in coreboot[master]: mb/kontron/986lcd-m: Use `winbond_enable_serial()`
by Paul Menzel (Code Review) 10 Jun '23

10 Jun '23

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39125 ) Change subject: mb/kontron/986lcd-m: Use `winbond_enable_serial()` ...................................................................... mb/kontron/986lcd-m: Use `winbond_enable_serial()` Note, the common function does not set the IRQ. pnp_set_irq(dev, PNP_IDX_IRQ0, 4); Change-Id: Ia437aa31ae92a299d0d0b35db15715997ee9bad3 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/kontron/986lcd-m/early_init.c 1 file changed, 6 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/39125/1 diff --git a/src/mainboard/kontron/986lcd-m/early_init.c b/src/mainboard/kontron/986lcd-m/early_init.c index 827f792..467d907 100644 --- a/src/mainboard/kontron/986lcd-m/early_init.c +++ b/src/mainboard/kontron/986lcd-m/early_init.c @@ -52,19 +52,15 @@ pnp_write_config(dev, 0x29, 0x43); /* GPIO settings */ pnp_write_config(dev, 0x2a, 0x40); /* GPIO settings */ + pnp_exit_conf_state(dev); + dev = PNP_DEV(0x2e, W83627THG_SP1); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); - pnp_set_irq(dev, PNP_IDX_IRQ0, 4); - pnp_set_enable(dev, 1); + winbond_enable_serial(dev, 0x3f8); dev = PNP_DEV(0x2e, W83627THG_SP2); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8); - pnp_set_irq(dev, PNP_IDX_IRQ0, 3); - pnp_set_enable(dev, 1); + winbond_enable_serial(dev, 0x2f8); + + pnp_enter_conf_state(dev); dev = PNP_DEV(0x2e, W83627THG_KBC); pnp_set_logical_device(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/39125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia437aa31ae92a299d0d0b35db15715997ee9bad3 Gerrit-Change-Number: 39125 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: mb/hatch + soc/intel/cannonlake: Enable TetonGlacierMode on hatch
by David Jimenez (Code Review) 10 Jun '23

10 Jun '23

David Jimenez has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38947 ) Change subject: mb/hatch + soc/intel/cannonlake: Enable TetonGlacierMode on hatch ...................................................................... mb/hatch + soc/intel/cannonlake: Enable TetonGlacierMode on hatch Enabling TetonGlacierMode allows for reconfiguring the PCIe lanes at runtime for hybrid drives. BUG=b:149171631 BRANCH=none TEST=Swap between x4 NVMe drives and 2x2 Teton Glacier hybrid drives and run lsblk, lspci, and nvme tools to confirm dynamic PCIe configuration Signed-off-by: David Jimenez <dvjimenez(a)chromium.org> Change-Id: If775b40e6922ac7d111ac00c7c51eec6623ed4df --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c 3 files changed, 15 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/38947/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index f7cf3cd..f360c10 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -50,6 +50,8 @@ register "PchUnlockGpioPads" = "1" # SD card WP pin confguration register "ScsSdCardWpPinEnabled" = "0" + # Auto-switch between X4 NVMe and X2 NVMe for hybrid storage support + register "TetonGlacierMode" = "1" # NOTE: if any variant wants to override this value, use the same format # as register "common_soc_config.pch_thermal_trip" = "value", instead of @@ -163,7 +165,7 @@ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN register "usb3_ports[5]" = "USB3_PORT_EMPTY" - # Enable Root port 9(x4) for NVMe. + # Enable Root port 9(x2) for NVMe. register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" # RP 9 uses CLK SRC 1 @@ -171,6 +173,10 @@ # ClkReq-to-ClkSrc mapping for CLK SRC 1 register "PcieClkSrcClkReq[1]" = "1" + # Enable Root port 11(x2) for NVMe hybrid storage devices. + register "PcieRpEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" + # PCIe port 14 for M.2 E-key WLAN register "PcieRpEnable[13]" = "1" register "PcieRpLtrEnable[13]" = "1" @@ -324,9 +330,9 @@ device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 (X4 NVME) + device pci 1d.0 on end # PCI Express Port 9 (X2 NVME) device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.2 on end # PCI Express Port 11 (x2 NVME) device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 off end # PCI Express port 13 device pci 1d.5 on diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index fd37d26..16265d2 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -242,6 +242,9 @@ * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled; + // Enables support for Teton Glacier hybrid storage device + uint8_t TetonGlacierMode; + /* PL1 Override value in Watts */ uint32_t tdp_pl1_override; /* PL2 Override value in Watts */ diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index dc4a2a8..e8ad62f 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -374,6 +374,9 @@ #endif params->Device4Enable = config->Device4Enable; + /* Teton Glacier hybrid storage support */ + params->TetonGlacierMode = config->TetonGlacierMode; + /* VrConfig Settings for 5 domains * 0 = System Agent, 1 = IA Core, 2 = Ring, * 3 = GT unsliced, 4 = GT sliced */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If775b40e6922ac7d111ac00c7c51eec6623ed4df Gerrit-Change-Number: 38947 Gerrit-PatchSet: 1 Gerrit-Owner: David Jimenez <dvjimenez(a)chromium.org> Gerrit-MessageType: newchange

7 8

Change in coreboot[master]: mb/intel: Add unaligned flag (%) sections that don't need alignment
by Hung-Te Lin (Code Review) 10 Jun '23

10 Jun '23

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37314 ) Change subject: mb/intel: Add unaligned flag (%) sections that don't need alignment ...................................................................... mb/intel: Add unaligned flag (%) sections that don't need alignment Sections that won't be updated independently and don't need to be aligned. Note: glkrvp/chromeos.fmd had unaligned RW_SECTION_{A,B} and is fixed now. leafhill/leafhill.8192.fmd had unaligned UNIFIED_MRC_CACHE and is fixed. Change-Id: I9333dddd9ead3610216009fb6fd1ad6df5f05cf3 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/mainboard/intel/baskingridge/chromeos.fmd M src/mainboard/intel/cannonlake_rvp/chromeos.fmd M src/mainboard/intel/coffeelake_rvp/chromeos.fmd M src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd M src/mainboard/intel/galileo/vboot.fmd M src/mainboard/intel/glkrvp/chromeos.fmd M src/mainboard/intel/icelake_rvp/chromeos.fmd M src/mainboard/intel/kblrvp/chromeos.fmd M src/mainboard/intel/kunimitsu/chromeos.fmd M src/mainboard/intel/leafhill/leafhill.16384.fmd M src/mainboard/intel/leafhill/leafhill.8192.fmd M src/mainboard/intel/minnow3/minnow3.fmd M src/mainboard/intel/strago/chromeos.fmd M src/mainboard/intel/wtm2/chromeos.fmd 14 files changed, 88 insertions(+), 88 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/37314/1 diff --git a/src/mainboard/intel/baskingridge/chromeos.fmd b/src/mainboard/intel/baskingridge/chromeos.fmd index 9852a22..a9675e6 100644 --- a/src/mainboard/intel/baskingridge/chromeos.fmd +++ b/src/mainboard/intel/baskingridge/chromeos.fmd @@ -13,23 +13,23 @@ } RW_SECTION_A@0x80000 0x100000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x7ffc0 - RW_FWID_A@0x8ffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x7ffc0 + RW_FWID_A@0x8ffc0% 0x40 RW_UNUSED_A@0x90000 0x70000 } RW_SECTION_B@0x180000 0x100000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x7ffc0 - RW_FWID_B@0x8ffc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x7ffc0 + RW_FWID_B@0x8ffc0% 0x40 RW_UNUSED_B@0x90000 0x70000 } RO_UNUSED_1@0x280000 0x170000 RO_VPD(PRESERVE)@0x3f0000 0x20000 RO_UNUSED_2@0x410000 0xe0000 RO_SECTION@0x4f0000 0x190000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_PADDING@0x840 0xf7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_PADDING@0x840% 0xf7c0 GBB@0x10000 0x80000 COREBOOT(CBFS)@0x90000 0x100000 } diff --git a/src/mainboard/intel/cannonlake_rvp/chromeos.fmd b/src/mainboard/intel/cannonlake_rvp/chromeos.fmd index 39bd6c5..b2a8f70 100644 --- a/src/mainboard/intel/cannonlake_rvp/chromeos.fmd +++ b/src/mainboard/intel/cannonlake_rvp/chromeos.fmd @@ -7,13 +7,13 @@ SI_BIOS@0x380000 0xc80000 { RW_SECTION_A@0x0 0x368000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x357fc0 - RW_FWID_A@0x367fc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x357fc0 + RW_FWID_A@0x367fc0% 0x40 } RW_SECTION_B@0x368000 0x368000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x357fc0 - RW_FWID_B@0x367fc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x357fc0 + RW_FWID_B@0x367fc0% 0x40 } RW_MISC@0x6d0000 0x30000 { UNIFIED_MRC_CACHE@0x0 0x20000 { @@ -34,9 +34,9 @@ RO_VPD(PRESERVE)@0x0 0x4000 RO_UNUSED@0x4000 0xc000 RO_SECTION@0x10000 0x370000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 GBB@0x1000 0xef000 COREBOOT(CBFS)@0xf0000 0x280000 } diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos.fmd b/src/mainboard/intel/coffeelake_rvp/chromeos.fmd index 39bd6c5..b2a8f70 100644 --- a/src/mainboard/intel/coffeelake_rvp/chromeos.fmd +++ b/src/mainboard/intel/coffeelake_rvp/chromeos.fmd @@ -7,13 +7,13 @@ SI_BIOS@0x380000 0xc80000 { RW_SECTION_A@0x0 0x368000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x357fc0 - RW_FWID_A@0x367fc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x357fc0 + RW_FWID_A@0x367fc0% 0x40 } RW_SECTION_B@0x368000 0x368000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x357fc0 - RW_FWID_B@0x367fc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x357fc0 + RW_FWID_B@0x367fc0% 0x40 } RW_MISC@0x6d0000 0x30000 { UNIFIED_MRC_CACHE@0x0 0x20000 { @@ -34,9 +34,9 @@ RO_VPD(PRESERVE)@0x0 0x4000 RO_UNUSED@0x4000 0xc000 RO_SECTION@0x10000 0x370000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 GBB@0x1000 0xef000 COREBOOT(CBFS)@0xf0000 0x280000 } diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd b/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd index 62e0f5d..0a7be5f 100644 --- a/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd +++ b/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd @@ -7,13 +7,13 @@ SI_BIOS@0x1400000 0xC00000 { RW_SECTION_A@0x0 0x2d0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x2bffc0 - RW_FWID_A@0x2cffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x2bffc0 + RW_FWID_A@0x2cffc0% 0x40 } RW_SECTION_B@0x2d0000 0x2d0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x2bffc0 - RW_FWID_B@0x2cffc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x2bffc0 + RW_FWID_B@0x2cffc0% 0x40 } RW_MISC@0x5a0000 0x30000 { UNIFIED_MRC_CACHE@0x0 0x20000 { @@ -33,9 +33,9 @@ WP_RO@0x7d0000 0x430000 { RO_VPD(PRESERVE)@0x0 0x4000 RO_SECTION@0x4000 0x42c000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 GBB@0x1000 0xef000 COREBOOT(CBFS)@0xf0000 0x33c000 } diff --git a/src/mainboard/intel/galileo/vboot.fmd b/src/mainboard/intel/galileo/vboot.fmd index 4d349bd..d4f9021 100644 --- a/src/mainboard/intel/galileo/vboot.fmd +++ b/src/mainboard/intel/galileo/vboot.fmd @@ -20,13 +20,13 @@ SI_BIOS@0x200000 0x600000 { RW_SECTION_A@0x0 0xf0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0xdffc0 - RW_FWID_A@0xeffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0xdffc0 + RW_FWID_A@0xeffc0% 0x40 } RW_SECTION_B@0xf0000 0xf0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0xdffc0 - RW_FWID_B@0xeffc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0xdffc0 + RW_FWID_B@0xeffc0% 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 RW_ELOG(PRESERVE)@0x1f0000 0x4000 @@ -40,11 +40,11 @@ RW_LEGACY(CBFS)@0x240000 0x1c0000 WP_RO@0x400000 0x200000 { RO_VPD(PRESERVE)@0x0 0x4000 - RO_UNUSED@0x4000 0xc000 + RO_UNUSED@0x4000% 0xc000 RO_SECTION@0x10000 0x1f0000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 GBB@0x1000 0x7f000 COREBOOT(CBFS)@0x80000 0x170000 } diff --git a/src/mainboard/intel/glkrvp/chromeos.fmd b/src/mainboard/intel/glkrvp/chromeos.fmd index 5d4ba46..fbaca9b 100644 --- a/src/mainboard/intel/glkrvp/chromeos.fmd +++ b/src/mainboard/intel/glkrvp/chromeos.fmd @@ -4,9 +4,9 @@ IFWI@0x1000 0x1ff000 RO_VPD(PRESERVE)@0x200000 0x4000 RO_SECTION@0x204000 0x1fc000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 COREBOOT(CBFS)@0x1000 0x1ab000 GBB@0x1ac000 0x40000 RO_UNUSED@0x1ec000 0x10000 @@ -27,17 +27,17 @@ FPF_STATUS@0x3B000 0x1000 TMP_UNUSED_HOLE@0x3C000 0xE000 } - RW_SECTION_A@0x44a000 0x477800 { + RW_SECTION_A@0x44a000 0x478000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x4677c0 - RW_FWID_A@0x4777c0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x467fc0 + RW_FWID_A@0x477fc0% 0x40 } - RW_SECTION_B@0x8c1800 0x477800 { + RW_SECTION_B@0x8c2000 0x478000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x4677c0 - RW_FWID_B@0x4777c0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x467fc0 + RW_FWID_B@0x477fc0% 0x40 } - RW_NVRAM(PRESERVE)@0xd39000 0x6000 + RW_NVRAM(PRESERVE)@0xd3a000 0x6000 SMMSTORE(PRESERVE)@0xd40000 0x40000 RW_LEGACY(CBFS)@0xd80000 0x1b0000 BIOS_UNUSABLE@0xf3f000 0x40000 diff --git a/src/mainboard/intel/icelake_rvp/chromeos.fmd b/src/mainboard/intel/icelake_rvp/chromeos.fmd index f4db8b4..037de53 100644 --- a/src/mainboard/intel/icelake_rvp/chromeos.fmd +++ b/src/mainboard/intel/icelake_rvp/chromeos.fmd @@ -7,13 +7,13 @@ SI_BIOS@0x400000 0xC00000 { RW_SECTION_A@0x0 0x2d0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x2bffc0 - RW_FWID_A@0x2cffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x2bffc0 + RW_FWID_A@0x2cffc0% 0x40 } RW_SECTION_B@0x2d0000 0x2d0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x2bffc0 - RW_FWID_B@0x2cffc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x2bffc0 + RW_FWID_B@0x2cffc0% 0x40 } RW_MISC@0x5a0000 0x30000 { UNIFIED_MRC_CACHE@0x0 0x20000 { @@ -33,9 +33,9 @@ WP_RO@0x7d0000 0x430000 { RO_VPD(PRESERVE)@0x0 0x4000 RO_SECTION@0x4000 0x42c000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 GBB@0x1000 0xef000 COREBOOT(CBFS)@0xf0000 0x33c000 } diff --git a/src/mainboard/intel/kblrvp/chromeos.fmd b/src/mainboard/intel/kblrvp/chromeos.fmd index 9ba1bf7..6be2a40 100644 --- a/src/mainboard/intel/kblrvp/chromeos.fmd +++ b/src/mainboard/intel/kblrvp/chromeos.fmd @@ -6,13 +6,13 @@ SI_BIOS@0x200000 0xe00000 { RW_SECTION_A@0x0 0x3f0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x3dffc0 - RW_FWID_A@0x3effc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x3dffc0 + RW_FWID_A@0x3effc0% 0x40 } RW_SECTION_B@0x3f0000 0x3f0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x3dffc0 - RW_FWID_B@0x3effc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x3dffc0 + RW_FWID_B@0x3effc0% 0x40 } RW_MRC_CACHE@0x7e0000 0x10000 RW_ELOG(PRESERVE)@0x7f0000 0x4000 @@ -28,9 +28,9 @@ RO_VPD(PRESERVE)@0x0 0x4000 RO_UNUSED@0x4000 0xc000 RO_SECTION@0x10000 0x3f0000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 GBB@0x1000 0xef000 COREBOOT(CBFS)@0xf0000 0x300000 } diff --git a/src/mainboard/intel/kunimitsu/chromeos.fmd b/src/mainboard/intel/kunimitsu/chromeos.fmd index 9ba1bf7..6be2a40 100644 --- a/src/mainboard/intel/kunimitsu/chromeos.fmd +++ b/src/mainboard/intel/kunimitsu/chromeos.fmd @@ -6,13 +6,13 @@ SI_BIOS@0x200000 0xe00000 { RW_SECTION_A@0x0 0x3f0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x3dffc0 - RW_FWID_A@0x3effc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x3dffc0 + RW_FWID_A@0x3effc0% 0x40 } RW_SECTION_B@0x3f0000 0x3f0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x3dffc0 - RW_FWID_B@0x3effc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x3dffc0 + RW_FWID_B@0x3effc0% 0x40 } RW_MRC_CACHE@0x7e0000 0x10000 RW_ELOG(PRESERVE)@0x7f0000 0x4000 @@ -28,9 +28,9 @@ RO_VPD(PRESERVE)@0x0 0x4000 RO_UNUSED@0x4000 0xc000 RO_SECTION@0x10000 0x3f0000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 GBB@0x1000 0xef000 COREBOOT(CBFS)@0xf0000 0x300000 } diff --git a/src/mainboard/intel/leafhill/leafhill.16384.fmd b/src/mainboard/intel/leafhill/leafhill.16384.fmd index a91ba9a..a7a6b26 100644 --- a/src/mainboard/intel/leafhill/leafhill.16384.fmd +++ b/src/mainboard/intel/leafhill/leafhill.16384.fmd @@ -1,8 +1,8 @@ FLASH 16M { SI_DESC@0x0 0x1000 IFWI@0x1000 0x2ff000 - FMAP@0x300000 0x800 - COREBOOT(CBFS)@0x300800 0xc1d800 + FMAP@0x300000% 0x800 + COREBOOT(CBFS)@0x300800% 0xc1d800 UNIFIED_MRC_CACHE@0xf1e000 0x21000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 diff --git a/src/mainboard/intel/leafhill/leafhill.8192.fmd b/src/mainboard/intel/leafhill/leafhill.8192.fmd index 3f4d21b..3fe71e0 100644 --- a/src/mainboard/intel/leafhill/leafhill.8192.fmd +++ b/src/mainboard/intel/leafhill/leafhill.8192.fmd @@ -1,9 +1,9 @@ FLASH 8M { SI_DESC@0x0 0x1000 IFWI@0x1000 0x300000 - FMAP@0x321000 0x800 - COREBOOT(CBFS)@0x321800 0x300000 - UNIFIED_MRC_CACHE@0x621800 0x21000 { + FMAP@0x321000% 0x800 + COREBOOT(CBFS)@0x321800% 0x300800 + UNIFIED_MRC_CACHE@0x622000 0x21000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 RW_VAR_MRC_CACHE@0x20000 0x1000 diff --git a/src/mainboard/intel/minnow3/minnow3.fmd b/src/mainboard/intel/minnow3/minnow3.fmd index d51b5ee..9733567 100644 --- a/src/mainboard/intel/minnow3/minnow3.fmd +++ b/src/mainboard/intel/minnow3/minnow3.fmd @@ -1,8 +1,8 @@ FLASH 16M { SI_DESC@0x0 0x1000 IFWI@0x1000 0x300000 - FMAP@0x301000 0x800 - COREBOOT(CBFS)@0x301800 0x3dc800 + FMAP@0x301000% 0x800 + COREBOOT(CBFS)@0x301800% 0x3dc800 UNIFIED_MRC_CACHE@0x6de000 0x21000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 diff --git a/src/mainboard/intel/strago/chromeos.fmd b/src/mainboard/intel/strago/chromeos.fmd index 923c8ee..5dec9ec 100644 --- a/src/mainboard/intel/strago/chromeos.fmd +++ b/src/mainboard/intel/strago/chromeos.fmd @@ -6,13 +6,13 @@ SI_BIOS@0x200000 0x600000 { RW_SECTION_A@0x0 0xf0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0xdffc0 - RW_FWID_A@0xeffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0xdffc0 + RW_FWID_A@0xeffc0% 0x40 } RW_SECTION_B@0xf0000 0xf0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0xdffc0 - RW_FWID_B@0xeffc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0xdffc0 + RW_FWID_B@0xeffc0% 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 RW_ELOG(PRESERVE)@0x1f0000 0x4000 @@ -28,9 +28,9 @@ RO_VPD(PRESERVE)@0x0 0x4000 RO_UNUSED@0x4000 0xc000 RO_SECTION@0x10000 0x1f0000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 GBB@0x1000 0x6f000 COREBOOT(CBFS)@0x70000 0x180000 } diff --git a/src/mainboard/intel/wtm2/chromeos.fmd b/src/mainboard/intel/wtm2/chromeos.fmd index 9852a22..a9675e6 100644 --- a/src/mainboard/intel/wtm2/chromeos.fmd +++ b/src/mainboard/intel/wtm2/chromeos.fmd @@ -13,23 +13,23 @@ } RW_SECTION_A@0x80000 0x100000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x7ffc0 - RW_FWID_A@0x8ffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x7ffc0 + RW_FWID_A@0x8ffc0% 0x40 RW_UNUSED_A@0x90000 0x70000 } RW_SECTION_B@0x180000 0x100000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x7ffc0 - RW_FWID_B@0x8ffc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x7ffc0 + RW_FWID_B@0x8ffc0% 0x40 RW_UNUSED_B@0x90000 0x70000 } RO_UNUSED_1@0x280000 0x170000 RO_VPD(PRESERVE)@0x3f0000 0x20000 RO_UNUSED_2@0x410000 0xe0000 RO_SECTION@0x4f0000 0x190000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_PADDING@0x840 0xf7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_PADDING@0x840% 0xf7c0 GBB@0x10000 0x80000 COREBOOT(CBFS)@0x90000 0x100000 } -- To view, visit https://review.coreboot.org/c/coreboot/+/37314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9333dddd9ead3610216009fb6fd1ad6df5f05cf3 Gerrit-Change-Number: 37314 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: mb: Add unaligned flag (%) sections that don't need alignment
by Hung-Te Lin (Code Review) 10 Jun '23

10 Jun '23

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37317 ) Change subject: mb: Add unaligned flag (%) sections that don't need alignment ...................................................................... mb: Add unaligned flag (%) sections that don't need alignment Fix all FMD files with unaligned sections. Change-Id: Icfd1e68990a272fbde9a0238f8a8b75db1549b05 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd M src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd M src/mainboard/lenovo/t400/vboot-rwa.fmd M src/mainboard/lenovo/t410/vboot-rwa.fmd M src/mainboard/lenovo/t420/vboot-rwa.fmd M src/mainboard/lenovo/t420s/vboot-rwa.fmd M src/mainboard/lenovo/t520/vboot-rwa.fmd M src/mainboard/lenovo/x200/vboot-rwa.fmd M src/mainboard/lenovo/x201/vboot-rwa.fmd M src/mainboard/lenovo/x220/vboot-rwa.fmd M src/mainboard/opencellular/elgon/vboot.fmd M src/mainboard/samsung/lumpy/chromeos.fmd M src/mainboard/samsung/stumpy/chromeos.fmd M src/mainboard/siemens/mc_apl1/mc_apl1.fmd M src/mainboard/siemens/mc_apl1/mc_apl_vboot.fmd M src/mainboard/supermicro/x11-lga1151-series/vboot-ro-rwab.fmd M src/mainboard/up/squared/vboot-ro.fmd M src/mainboard/up/squared/vboot-roa.fmd M src/mainboard/up/squared/vboot-roab.fmd 19 files changed, 104 insertions(+), 104 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/37317/1 diff --git a/src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd b/src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd index 0d2c9da..fb8960b 100644 --- a/src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd +++ b/src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd @@ -2,15 +2,15 @@ SI_BIOS 0x1000000 { RW_SECTION_A 0x7c0000 { VBLOCK_A 0x10000 - FW_MAIN_A(CBFS) 0x74ffc0 - RW_FWID_A 0x40 + FW_MAIN_A(CBFS)% 0x74ffc0 + RW_FWID_A% 0x40 } RW_VPD(PRESERVE) 0x1000 WP_RO { - FMAP 0x800 - RO_FRID 0x40 - RO_PADDING 0x7c0 + FMAP% 0x800 + RO_FRID% 0x40 + RO_PADDING% 0x7c0 RO_VPD(PRESERVE) 0x1000 GBB 0x1e000 COREBOOT(CBFS) diff --git a/src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd b/src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd index 0d2c9da..fb8960b 100644 --- a/src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd +++ b/src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd @@ -2,15 +2,15 @@ SI_BIOS 0x1000000 { RW_SECTION_A 0x7c0000 { VBLOCK_A 0x10000 - FW_MAIN_A(CBFS) 0x74ffc0 - RW_FWID_A 0x40 + FW_MAIN_A(CBFS)% 0x74ffc0 + RW_FWID_A% 0x40 } RW_VPD(PRESERVE) 0x1000 WP_RO { - FMAP 0x800 - RO_FRID 0x40 - RO_PADDING 0x7c0 + FMAP% 0x800 + RO_FRID% 0x40 + RO_PADDING% 0x7c0 RO_VPD(PRESERVE) 0x1000 GBB 0x1e000 COREBOOT(CBFS) diff --git a/src/mainboard/lenovo/t400/vboot-rwa.fmd b/src/mainboard/lenovo/t400/vboot-rwa.fmd index 4af3fcd..9112721 100644 --- a/src/mainboard/lenovo/t400/vboot-rwa.fmd +++ b/src/mainboard/lenovo/t400/vboot-rwa.fmd @@ -8,16 +8,16 @@ SI_BIOS@0x600000 0x200000 { RW_SECTION_A 0x100000 { VBLOCK_A 0x10000 - FW_MAIN_A(CBFS) - RW_FWID_A 0x40 + FW_MAIN_A(CBFS)% + RW_FWID_A% 0x40 } RW_VPD(PRESERVE) 0x1000 CONSOLE 0x10000 SMMSTORE(PRESERVE) 0x40000 WP_RO { - FMAP 0x800 - RO_FRID 0x40 - RO_PADDING 0x7c0 + FMAP% 0x800 + RO_FRID% 0x40 + RO_PADDING% 0x7c0 RO_VPD(PRESERVE) 0x1000 GBB 0x1e000 COREBOOT(CBFS) diff --git a/src/mainboard/lenovo/t410/vboot-rwa.fmd b/src/mainboard/lenovo/t410/vboot-rwa.fmd index 8f50d33..885aa0d 100644 --- a/src/mainboard/lenovo/t410/vboot-rwa.fmd +++ b/src/mainboard/lenovo/t410/vboot-rwa.fmd @@ -7,8 +7,8 @@ SI_BIOS@0x500000 0x300000 { RW_SECTION_A 0x180000 { VBLOCK_A 0x10000 - FW_MAIN_A(CBFS) - RW_FWID_A 0x40 + FW_MAIN_A(CBFS)% + RW_FWID_A% 0x40 } UNIFIED_MRC_CACHE 0x20000 { RECOVERY_MRC_CACHE 0x10000 @@ -20,9 +20,9 @@ WP_RO { RO_VPD(PRESERVE) 0x1000 RO_SECTION 0x11e000 { - FMAP 0x800 - RO_FRID 0x40 - RO_PADDING 0x7c0 + FMAP% 0x800 + RO_FRID% 0x40 + RO_PADDING% 0x7c0 GBB 0x1e000 COREBOOT(CBFS) } diff --git a/src/mainboard/lenovo/t420/vboot-rwa.fmd b/src/mainboard/lenovo/t420/vboot-rwa.fmd index 8a4cd3b..0f3fe32 100644 --- a/src/mainboard/lenovo/t420/vboot-rwa.fmd +++ b/src/mainboard/lenovo/t420/vboot-rwa.fmd @@ -7,8 +7,8 @@ SI_BIOS@0x500000 0x300000 { RW_SECTION_A@0x00000 0x180000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x16ffc0 - RW_FWID_A@0x17ffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x16ffc0 + RW_FWID_A@0x17ffc0% 0x40 } UNIFIED_MRC_CACHE@0x180000 0x20000 { RECOVERY_MRC_CACHE@0x0 0x10000 @@ -18,9 +18,9 @@ SMMSTORE(PRESERVE)@0x1a1000 0x40000 WP_RO@0x1e1000 0x11f000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_PADDING@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_PADDING@0x840% 0x7c0 RO_VPD(PRESERVE)@0x1000 0x1000 GBB@0x2000 0x1e000 COREBOOT(CBFS)@0x20000 0xff000 diff --git a/src/mainboard/lenovo/t420s/vboot-rwa.fmd b/src/mainboard/lenovo/t420s/vboot-rwa.fmd index 8a4cd3b..0f3fe32 100644 --- a/src/mainboard/lenovo/t420s/vboot-rwa.fmd +++ b/src/mainboard/lenovo/t420s/vboot-rwa.fmd @@ -7,8 +7,8 @@ SI_BIOS@0x500000 0x300000 { RW_SECTION_A@0x00000 0x180000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x16ffc0 - RW_FWID_A@0x17ffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x16ffc0 + RW_FWID_A@0x17ffc0% 0x40 } UNIFIED_MRC_CACHE@0x180000 0x20000 { RECOVERY_MRC_CACHE@0x0 0x10000 @@ -18,9 +18,9 @@ SMMSTORE(PRESERVE)@0x1a1000 0x40000 WP_RO@0x1e1000 0x11f000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_PADDING@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_PADDING@0x840% 0x7c0 RO_VPD(PRESERVE)@0x1000 0x1000 GBB@0x2000 0x1e000 COREBOOT(CBFS)@0x20000 0xff000 diff --git a/src/mainboard/lenovo/t520/vboot-rwa.fmd b/src/mainboard/lenovo/t520/vboot-rwa.fmd index 8a4cd3b..0f3fe32 100644 --- a/src/mainboard/lenovo/t520/vboot-rwa.fmd +++ b/src/mainboard/lenovo/t520/vboot-rwa.fmd @@ -7,8 +7,8 @@ SI_BIOS@0x500000 0x300000 { RW_SECTION_A@0x00000 0x180000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x16ffc0 - RW_FWID_A@0x17ffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x16ffc0 + RW_FWID_A@0x17ffc0% 0x40 } UNIFIED_MRC_CACHE@0x180000 0x20000 { RECOVERY_MRC_CACHE@0x0 0x10000 @@ -18,9 +18,9 @@ SMMSTORE(PRESERVE)@0x1a1000 0x40000 WP_RO@0x1e1000 0x11f000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_PADDING@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_PADDING@0x840% 0x7c0 RO_VPD(PRESERVE)@0x1000 0x1000 GBB@0x2000 0x1e000 COREBOOT(CBFS)@0x20000 0xff000 diff --git a/src/mainboard/lenovo/x200/vboot-rwa.fmd b/src/mainboard/lenovo/x200/vboot-rwa.fmd index 4af3fcd..9112721 100644 --- a/src/mainboard/lenovo/x200/vboot-rwa.fmd +++ b/src/mainboard/lenovo/x200/vboot-rwa.fmd @@ -8,16 +8,16 @@ SI_BIOS@0x600000 0x200000 { RW_SECTION_A 0x100000 { VBLOCK_A 0x10000 - FW_MAIN_A(CBFS) - RW_FWID_A 0x40 + FW_MAIN_A(CBFS)% + RW_FWID_A% 0x40 } RW_VPD(PRESERVE) 0x1000 CONSOLE 0x10000 SMMSTORE(PRESERVE) 0x40000 WP_RO { - FMAP 0x800 - RO_FRID 0x40 - RO_PADDING 0x7c0 + FMAP% 0x800 + RO_FRID% 0x40 + RO_PADDING% 0x7c0 RO_VPD(PRESERVE) 0x1000 GBB 0x1e000 COREBOOT(CBFS) diff --git a/src/mainboard/lenovo/x201/vboot-rwa.fmd b/src/mainboard/lenovo/x201/vboot-rwa.fmd index 0d1aa5d..dc035e9 100644 --- a/src/mainboard/lenovo/x201/vboot-rwa.fmd +++ b/src/mainboard/lenovo/x201/vboot-rwa.fmd @@ -7,8 +7,8 @@ SI_BIOS@0x500000 0x300000 { RW_SECTION_A 0x180000 { VBLOCK_A 0x10000 - FW_MAIN_A(CBFS) - RW_FWID_A 0x40 + FW_MAIN_A(CBFS)% + RW_FWID_A% 0x40 } UNIFIED_MRC_CACHE 0x20000 { RECOVERY_MRC_CACHE 0x10000 @@ -19,9 +19,9 @@ WP_RO { RO_VPD(PRESERVE) 0x1000 RO_SECTION { - FMAP 0x800 - RO_FRID 0x40 - RO_PADDING 0x7c0 + FMAP% 0x800 + RO_FRID% 0x40 + RO_PADDING% 0x7c0 GBB 0x1e000 COREBOOT(CBFS) } diff --git a/src/mainboard/lenovo/x220/vboot-rwa.fmd b/src/mainboard/lenovo/x220/vboot-rwa.fmd index 8a4cd3b..0f3fe32 100644 --- a/src/mainboard/lenovo/x220/vboot-rwa.fmd +++ b/src/mainboard/lenovo/x220/vboot-rwa.fmd @@ -7,8 +7,8 @@ SI_BIOS@0x500000 0x300000 { RW_SECTION_A@0x00000 0x180000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x16ffc0 - RW_FWID_A@0x17ffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x16ffc0 + RW_FWID_A@0x17ffc0% 0x40 } UNIFIED_MRC_CACHE@0x180000 0x20000 { RECOVERY_MRC_CACHE@0x0 0x10000 @@ -18,9 +18,9 @@ SMMSTORE(PRESERVE)@0x1a1000 0x40000 WP_RO@0x1e1000 0x11f000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_PADDING@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_PADDING@0x840% 0x7c0 RO_VPD(PRESERVE)@0x1000 0x1000 GBB@0x2000 0x1e000 COREBOOT(CBFS)@0x20000 0xff000 diff --git a/src/mainboard/opencellular/elgon/vboot.fmd b/src/mainboard/opencellular/elgon/vboot.fmd index 0d6af2d..dbb31cb 100644 --- a/src/mainboard/opencellular/elgon/vboot.fmd +++ b/src/mainboard/opencellular/elgon/vboot.fmd @@ -4,8 +4,8 @@ RO_SECTION@0x0 0x3fc000 { # 0 - 0x10000 is free for firmware usage. # bootblock starts at 0x20000 - FMAP@0x0 0x1000 - RO_FRID@0x1000 0x100 + FMAP@0x0% 0x1000 + RO_FRID@0x1000% 0x100 # bootblock includes trusted/non-trusted CLIB, CSIB, # and BL1FWs packaged in # src/soc/cavium/common/Makefile.inc. @@ -17,13 +17,13 @@ } RW_SECTION_A@0x400000 0x5fa000 { VBLOCK_A@0x0 0x2000 - FW_MAIN_A(CBFS)@0x2000 0x5f7f00 - RW_FWID_A@0x5f9f00 0x100 + FW_MAIN_A(CBFS)@0x2000% 0x5f7f00 + RW_FWID_A@0x5f9f00% 0x100 } RW_SECTION_B@0x9fa000 0x5fa000 { VBLOCK_B@0x0 0x2000 - FW_MAIN_B(CBFS)@0x2000 0x5f7f00 - RW_FWID_B@0x5f9f00 0x100 + FW_MAIN_B(CBFS)@0x2000% 0x5f7f00 + RW_FWID_B@0x5f9f00% 0x100 } RW_ELOG(PRESERVE)@0xff4000 0x4000 RW_VPD(PRESERVE)@0xff8000 0x8000 diff --git a/src/mainboard/samsung/lumpy/chromeos.fmd b/src/mainboard/samsung/lumpy/chromeos.fmd index 9852a22..95ec048 100644 --- a/src/mainboard/samsung/lumpy/chromeos.fmd +++ b/src/mainboard/samsung/lumpy/chromeos.fmd @@ -13,23 +13,23 @@ } RW_SECTION_A@0x80000 0x100000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x7ffc0 - RW_FWID_A@0x8ffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x7ffc0 + RW_FWID_A@0x8ffc0% 0x40 RW_UNUSED_A@0x90000 0x70000 } RW_SECTION_B@0x180000 0x100000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x7ffc0 - RW_FWID_B@0x8ffc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x7ffc0 + RW_FWID_B@0x8ffc0% 0x40 RW_UNUSED_B@0x90000 0x70000 } RO_UNUSED_1@0x280000 0x170000 RO_VPD(PRESERVE)@0x3f0000 0x20000 RO_UNUSED_2@0x410000 0xe0000 RO_SECTION@0x4f0000 0x190000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_PADDING@0x840 0xf7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_PADDING@0x840% 0xf7c0 GBB@0x10000 0x80000 COREBOOT(CBFS)@0x90000 0x100000 } diff --git a/src/mainboard/samsung/stumpy/chromeos.fmd b/src/mainboard/samsung/stumpy/chromeos.fmd index 9852a22..95ec048 100644 --- a/src/mainboard/samsung/stumpy/chromeos.fmd +++ b/src/mainboard/samsung/stumpy/chromeos.fmd @@ -13,23 +13,23 @@ } RW_SECTION_A@0x80000 0x100000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x7ffc0 - RW_FWID_A@0x8ffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x7ffc0 + RW_FWID_A@0x8ffc0% 0x40 RW_UNUSED_A@0x90000 0x70000 } RW_SECTION_B@0x180000 0x100000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x7ffc0 - RW_FWID_B@0x8ffc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x7ffc0 + RW_FWID_B@0x8ffc0% 0x40 RW_UNUSED_B@0x90000 0x70000 } RO_UNUSED_1@0x280000 0x170000 RO_VPD(PRESERVE)@0x3f0000 0x20000 RO_UNUSED_2@0x410000 0xe0000 RO_SECTION@0x4f0000 0x190000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_PADDING@0x840 0xf7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_PADDING@0x840% 0xf7c0 GBB@0x10000 0x80000 COREBOOT(CBFS)@0x90000 0x100000 } diff --git a/src/mainboard/siemens/mc_apl1/mc_apl1.fmd b/src/mainboard/siemens/mc_apl1/mc_apl1.fmd index 36772d6..2dd2173 100644 --- a/src/mainboard/siemens/mc_apl1/mc_apl1.fmd +++ b/src/mainboard/siemens/mc_apl1/mc_apl1.fmd @@ -1,8 +1,8 @@ FLASH 16M { SI_DESC@0x0 0x1000 IFWI 0x2ff000 - FMAP 0x800 - COREBOOT(CBFS) 0xb9d800 + FMAP% 0x800 + COREBOOT(CBFS)% 0xb9d800 UNIFIED_MRC_CACHE 0x21000 { RECOVERY_MRC_CACHE 0x10000 RW_MRC_CACHE 0x10000 diff --git a/src/mainboard/siemens/mc_apl1/mc_apl_vboot.fmd b/src/mainboard/siemens/mc_apl1/mc_apl_vboot.fmd index 8af2e9a..c9d1c148 100644 --- a/src/mainboard/siemens/mc_apl1/mc_apl_vboot.fmd +++ b/src/mainboard/siemens/mc_apl1/mc_apl_vboot.fmd @@ -4,9 +4,9 @@ IFWI 0x2ff000 RO_VPD 0x4000 RO_SECTION 0xb8f000 { - FMAP 0x800 - RO_FRID 0x40 - RO_FRID_PAD 0x7c0 + FMAP% 0x800 + RO_FRID% 0x40 + RO_FRID_PAD% 0x7c0 COREBOOT(CBFS) 0xb4e000 GBB 0x40000 } diff --git a/src/mainboard/supermicro/x11-lga1151-series/vboot-ro-rwab.fmd b/src/mainboard/supermicro/x11-lga1151-series/vboot-ro-rwab.fmd index a295680..96f359e 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/vboot-ro-rwab.fmd +++ b/src/mainboard/supermicro/x11-lga1151-series/vboot-ro-rwab.fmd @@ -6,13 +6,13 @@ SI_BIOS@0x500000 0xb00000 { RW_SECTION_A@0x0 0x33e000 { VBLOCK_A@0x0 0x20000 - FW_MAIN_A(CBFS)@0x20000 0x31dfc0 - RW_FWID_A@0x33dfc0 0x40 + FW_MAIN_A(CBFS)@0x20000% 0x31dfc0 + RW_FWID_A@0x33dfc0% 0x40 } RW_SECTION_B@0x33e000 0x33e000 { VBLOCK_B@0x0 0x20000 - FW_MAIN_B(CBFS)@0x20000 0x31dfc0 - RW_FWID_B@0x33dfc0 0x40 + FW_MAIN_B(CBFS)@0x20000% 0x31dfc0 + RW_FWID_B@0x33dfc0% 0x40 } MISC_RW@0x67d000 0x62000 { UNIFIED_MRC_CACHE@0x0 0x20000 { @@ -25,9 +25,9 @@ WP_RO@0x6df000 0x421000 { RO_VPD(PRESERVE)@0x0 0x4000 RO_SECTION@0x4000 0x41d000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 GBB@0x1000 0xef000 COREBOOT(CBFS)@0xf0000 0x32d000 } diff --git a/src/mainboard/up/squared/vboot-ro.fmd b/src/mainboard/up/squared/vboot-ro.fmd index 72f92fe..afebc8c 100644 --- a/src/mainboard/up/squared/vboot-ro.fmd +++ b/src/mainboard/up/squared/vboot-ro.fmd @@ -3,11 +3,11 @@ SI_BIOS@0x1000 0xefe000 { WP_RO@0x0 0xe91000 { IFWI@0x0 0x2ff000 - FMAP@0x2ff000 0x800 - RO_VPD(PRESERVE)@0x2ff800 0x4000 - RO_SECTION@0x303800 0xb8d800 { - RO_FRID@0x0 0x40 - RO_FRID_PAD@0x40 0x7c0 + FMAP@0x2ff000% 0x800 + RO_VPD(PRESERVE)@0x2ff800% 0x4000 + RO_SECTION@0x303800% 0xb8d800 { + RO_FRID@0x0% 0x40 + RO_FRID_PAD@0x40% 0x7c0 GBB@0x800 0x40000 COREBOOT(CBFS)@0x40800 0xb4d000 } diff --git a/src/mainboard/up/squared/vboot-roa.fmd b/src/mainboard/up/squared/vboot-roa.fmd index 330ce03..b23e69f 100644 --- a/src/mainboard/up/squared/vboot-roa.fmd +++ b/src/mainboard/up/squared/vboot-roa.fmd @@ -3,11 +3,11 @@ SI_BIOS@0x1000 0xefe000 { WP_RO@0x0 0x502000 { IFWI@0x0 0x2ff000 - FMAP@0x2ff000 0x800 - RO_VPD(PRESERVE)@0x2ff800 0x4000 - RO_SECTION@0x303800 0x1fe800 { - RO_FRID@0x0 0x40 - RO_FRID_PAD@0x40 0x7c0 + FMAP@0x2ff000% 0x800 + RO_VPD(PRESERVE)@0x2ff800% 0x4000 + RO_SECTION@0x303800% 0x1fe800 { + RO_FRID@0x0% 0x40 + RO_FRID_PAD@0x40% 0x7c0 GBB@0x800 0x40000 COREBOOT(CBFS)@0x40800 0x1be000 } @@ -28,8 +28,8 @@ } RW_SECTION_A@0x52f000 0x98f000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x97efc0 - RW_FWID_A@0x98efc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x97efc0 + RW_FWID_A@0x98efc0% 0x40 } BIOS_UNUSABLE@0xebe000 0x40000 } diff --git a/src/mainboard/up/squared/vboot-roab.fmd b/src/mainboard/up/squared/vboot-roab.fmd index 4ddcbc0..90e8e37 100644 --- a/src/mainboard/up/squared/vboot-roab.fmd +++ b/src/mainboard/up/squared/vboot-roab.fmd @@ -3,12 +3,12 @@ SI_BIOS@0x1000 0xefe000 { WP_RO@0x0 0x503000 { IFWI@0x0 0x2ff000 - FMAP@0x2ff000 0x800 - RO_VPD(PRESERVE)@0x2ff800 0x4000 - RO_SECTION@0x303800 0x1ff800 { - RO_FRID@0x0 0x40 - RO_FRID_PAD@0x40 0x7c0 - GBB@0x800 0x40000 + FMAP@0x2ff000% 0x800 + RO_VPD(PRESERVE)@0x2ff800% 0x4000 + RO_SECTION@0x303800% 0x1ff800 { + RO_FRID@0x0% 0x40 + RO_FRID_PAD@0x40% 0x7c0 + GBB@0x800% 0x40000 COREBOOT(CBFS)@0x40800 0x1bf000 } } @@ -28,13 +28,13 @@ } RW_SECTION_A@0x530000 0x4c7000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x4b6fc0 - RW_FWID_A@0x4c6fc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x4b6fc0 + RW_FWID_A@0x4c6fc0% 0x40 } RW_SECTION_B@0x9f7000 0x4c7000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x4b6fc0 - RW_FWID_B@0x4c6fc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x4b6fc0 + RW_FWID_B@0x4c6fc0% 0x40 } BIOS_UNUSABLE@0xebe000 0x40000 } -- To view, visit https://review.coreboot.org/c/coreboot/+/37317 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfd1e68990a272fbde9a0238f8a8b75db1549b05 Gerrit-Change-Number: 37317 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

6 8

Change in coreboot[master]: [WIP]security: Add option to lock regions for SMMSTORE
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40829 ) Change subject: [WIP]security: Add option to lock regions for SMMSTORE ...................................................................... [WIP]security: Add option to lock regions for SMMSTORE On many server boards the flash is updateable out of band using the BMC and the bios region doesn't need to be writeable except for the SMM_STORE. Add an option to write-protect the COREBOOT and FMAP region. UNTESTED. Change-Id: I1096be9650f2af3e886f12f7db50c5060e0d40e1 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/security/lockdown/Kconfig M src/security/lockdown/lockdown.c 2 files changed, 36 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/40829/1 diff --git a/src/security/lockdown/Kconfig b/src/security/lockdown/Kconfig index 30b5237..d24c5e5 100644 --- a/src/security/lockdown/Kconfig +++ b/src/security/lockdown/Kconfig @@ -72,6 +72,23 @@ is either triggered by coreboot (when INTEL_CHIPSET_LOCKDOWN is set) or has to be triggered later (e.g. by the payload or the OS). +config BOOTMEDIA_LOCK_COREBOOT_FMAP_RO + depends on BOOTMEDIA_LOCK_CONTROLLER + bool "Write-protect COREBOOT and FMAP region in boot medium" + help + Select this if you want to write-protect the COREBOOT and FMAP region + as specified in the FMAP. You will be able to write every region outside + of COREBOOT and FMAP using the internal controller (eg. SMM_STORE). + + The locking will take place during the chipset lockdown. + Chipset lockdown is platform specific und might be done unconditionally, + when INTEL_CHIPSET_LOCKDOWN is set or has to be triggered later + (e.g. by the payload or the OS). + + NOTE: If you trigger the chipset lockdown unconditionally, + you won't be able to write to update coreboot using the internal + controller any more. + endchoice config BOOTMEDIA_LOCK_IN_VERSTAGE diff --git a/src/security/lockdown/lockdown.c b/src/security/lockdown/lockdown.c index 62d0a29..b4698d7 100644 --- a/src/security/lockdown/lockdown.c +++ b/src/security/lockdown/lockdown.c @@ -28,8 +28,11 @@ } else if (CONFIG(BOOTMEDIA_LOCK_WPRO_VBOOT_RO)) { printk(BIOS_DEBUG, "'WP_RO only'"); lock_type = CTRLR_WP; + } else if (CONFIG(BOOTMEDIA_LOCK_COREBOOT_FMAP_RO)) { + printk(BIOS_DEBUG, "'COREBOOT and FMAP'"); + lock_type = CTRLR_WP; } - printk(BIOS_DEBUG, "using CTRL...\n"); + printk(BIOS_DEBUG, " using CTRL...\n"); } else { if (CONFIG(BOOTMEDIA_LOCK_WHOLE_RO)) { printk(BIOS_DEBUG, "'readonly'"); @@ -38,7 +41,7 @@ printk(BIOS_DEBUG, "'WP_RO only'"); lock_type = MEDIA_WP; } - printk(BIOS_DEBUG, "using flash chip...\n"); + printk(BIOS_DEBUG, " using flash chip...\n"); } if (CONFIG(BOOTMEDIA_LOCK_WPRO_VBOOT_RO)) { @@ -46,6 +49,11 @@ printk(BIOS_ERR, "BM-LOCKDOWN: Could not find region 'WP_RO'\n"); else rdev = &dev; + } else if (CONFIG(BOOTMEDIA_LOCK_COREBOOT_FMAP_RO)) { + if (fmap_locate_area_as_rdev("COREBOOT", &dev) < 0) + printk(BIOS_ERR, "BM-LOCKDOWN: Could not find region 'COREBOOT'\n"); + else + rdev = &dev; } else { rdev = boot_device_ro(); } @@ -54,6 +62,15 @@ printk(BIOS_INFO, "BM-LOCKDOWN: Enabled bootmedia protection\n"); else printk(BIOS_ERR, "BM-LOCKDOWN: Failed to enable bootmedia protection\n"); + + if (CONFIG(BOOTMEDIA_LOCK_COREBOOT_FMAP_RO)) { + if (fmap_locate_area_as_rdev("FMAP", &dev) < 0) + printk(BIOS_ERR, "BM-LOCKDOWN: Could not find region 'FMAP'\n"); + else if (boot_device_wp_region(&dev, lock_type) >= 0) + printk(BIOS_INFO, "BM-LOCKDOWN: Enabled bootmedia protection\n"); + else + printk(BIOS_ERR, "BM-LOCKDOWN: Failed to enable bootmedia protection\n"); + } } static void lock(void *unused) -- To view, visit https://review.coreboot.org/c/coreboot/+/40829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1096be9650f2af3e886f12f7db50c5060e0d40e1 Gerrit-Change-Number: 40829 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: mb/google/hatch:[DEBUG ONLY] Assert DEVSLP in S3
by Rizwan Qureshi (Code Review) 10 Jun '23

10 Jun '23

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32078 Change subject: mb/google/hatch:[DEBUG ONLY] Assert DEVSLP in S3 ...................................................................... mb/google/hatch:[DEBUG ONLY] Assert DEVSLP in S3 It was obsevred that the DEVSLP is keeping low in S3, and SDD is drawing some power, assert DEVSLP in S3 to indicate SSD to go into low power mode. Change-Id: I001781fd0e1e5763f6865966658fc9fccc3edff8 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/gpio.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/32078/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 5987abc..15038b5 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -410,6 +410,7 @@ /* Default GPIO settings before entering sleep. */ static const struct pad_config default_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_E5, 1, DEEP), }; /* -- To view, visit https://review.coreboot.org/c/coreboot/+/32078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I001781fd0e1e5763f6865966658fc9fccc3edff8 Gerrit-Change-Number: 32078 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: newchange

2 1

Change in ...coreboot[master]: [WIP]device/pci_rom: Add ATRM method
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31502 Change subject: [WIP]device/pci_rom: Add ATRM method ...................................................................... [WIP]device/pci_rom: Add ATRM method Add ATRM method for AMD GPUs, which is similar to _ROM. As both functions seem to have identical arguments and return values, redirect ATRM to _ROM. Don't depend on VGA devices, but display devices, as some AMD dGPUs identify themself as PCI_CLASS_DISPLAY_OTHER. Needs test on platforms with AMD display devices. Change-Id: Id2212f29f0de051f6cbd59f8332e86696c1166ab Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/device/pci_rom.c 1 file changed, 15 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/31502/1 diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 82d9a30..86c839c 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -272,8 +272,8 @@ { static size_t ngfx; - /* Only handle VGA devices */ - if ((device->class >> 8) != PCI_CLASS_DISPLAY_VGA) + /* Only handle display devices */ + if ((device->class >> 16) != PCI_BASE_CLASS_DISPLAY) return; /* Only handle enabled devices */ @@ -319,9 +319,21 @@ memcpy(cbrom, rom, cbrom_length); - /* write _ROM method */ + /* write ACPI methods */ acpigen_write_scope(scope); + + /* Nvidia uses _ROM */ acpigen_write_rom(cbrom, cbrom_length); + + /* AMD uses ATRM. Redirect ATRM to _ROM */ + acpigen_write_method_serialized("ATRM", 2); + acpigen_write_to_integer(ARG1_OP, LOCAL0_OP); + acpigen_emit_byte(RETURN_OP); + acpigen_emit_namestring("_ROM"); + acpigen_emit_byte(ARG0_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_pop_len(); /* pop method */ + acpigen_pop_len(); /* pop scope */ } #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2212f29f0de051f6cbd59f8332e86696c1166ab Gerrit-Change-Number: 31502 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 13

Change in ...coreboot[master]: Updated and converted to markdown doc from wiki on porting motherboards.
by Calvin (Code Review) 10 Jun '23

10 Jun '23

Calvin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31849 Change subject: Updated and converted to markdown doc from wiki on porting motherboards. ...................................................................... Updated and converted to markdown doc from wiki on porting motherboards. Some of the documentation from the wiki (https://www.coreboot.org/Motherboard_Porting_Guide) has been ported to markdown and updated as I was able to figure things out. Still a work in progress as there is more data from that page that I will need to convert as I work through it. If I get anywhere in my project of porting coreboot to an older Chromebook, I will document more of this process as I go. Signed-off-by: calvinrempel <calvin.rempel(a)gmail.com> Change-Id: Ie3b8a99c10808c7e7ebc826b4d2f992774cc9a75 --- M Documentation/index.md A Documentation/porting/index.md A Documentation/porting/motherboard_probe.md 3 files changed, 135 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/31849/1 diff --git a/Documentation/index.md b/Documentation/index.md index dd8714c..32635f9 100644 --- a/Documentation/index.md +++ b/Documentation/index.md @@ -164,6 +164,7 @@ * [Rookie Guide](lessons/index.md) * [Coding Style](coding_style.md) * [Project Ideas](contributing/project_ideas.md) +* [Porting](porting/index.md) * [Code of Conduct](community/code_of_conduct.md) * [Community forums](community/forums.md) * [coreboot at conferences](community/conferences.md) diff --git a/Documentation/porting/index.md b/Documentation/porting/index.md new file mode 100644 index 0000000..ed282e8 --- /dev/null +++ b/Documentation/porting/index.md @@ -0,0 +1,3 @@ +# Porting New Boards + +* [Motherboard Probing](motherboard_probe.md) diff --git a/Documentation/porting/motherboard_probe.md b/Documentation/porting/motherboard_probe.md new file mode 100644 index 0000000..7562f7c --- /dev/null +++ b/Documentation/porting/motherboard_probe.md @@ -0,0 +1,131 @@ +Motherboard Porting Guide +========================= + +Please note that this guide is very much a work in progress. + +Finding out What You Have +------------------------- + +### Tools +To begin the process of porting a motherboard to coreboot, you first +need to determine what all is on it: the chipset (ie, North and South +Bridge), Flash Rom, etc. To do this, you will need a suite of +tools provided by the coreboot project, as well as some that can be +found more readily in various repositories. + +For the sake of this page, it will be assumed you are using Debian or +Ubuntu. + +#### Build Environment +If you have not already done so, get your basic build environment +installed: + + $ sudo apt install build-essential git cvs subversion + +#### Probing Utilities - From Repos +Next, a number of utilities will need to be installed which will be used +later for probing the system as well as some dev libraries which will be +used in building some of the tools in the next step.These should be +available in your distro's repo: + + $ sudo apt install pciutils pciutils-dev flashrom acpitool \ + usbutils acpidump + +#### Probing Utilities - From Source +Once the base build system in place and what utilities along with what +libraries you can glean from your distro's repositories, it is time to +build some tools from source. If you have not already done so, checkout +the git repo as described in "[Rookie Guide: Lesson 1]". + +Once you have synced the coreboot repo, cd into the utilities folder: + + $cd coreboot/util + +##### superiotool + + $ cd ./superiotool + $ make + $ sudo make install + $ cd .. + +##### inteltool + + $ cd ./inteltool + $ make + $ sudo make install + $ cd .. + +##### ectool + + $ cd ./ectool + $ make + $ make install + $ cd .. + +##### dmidecode + + $ cvs -z3 -d:pserver:anonymous@cvs.savannah.nongnu.org:/sources/dmidecode \ + co dmidecode + $ cd dmidecode + $ make + $ sudo make install + $ cd .. + +##### msrtool + + $ cd ./msrtool + $ ./configure + $ make + $ sudo make install + $ cd .. + +##### nvramtool + + $ cd ./nvramtool + $ make + $ sudo make install + +##### acpica-unix + + $ wget http://deb.debian.org/debian/pool/main/a/acpica-unix/acpica-unix_20181213.o… + $ tar -xaf acpica-unix_20181213.orig.tar.gz + $ cd ./acpica-unix-2018-12-13/ + $ make + $ sudo make install + +### Probe the Board +Now we will begin to probe the board to see what we can find out about +it. First, become root: + + $ sudo su + +Then load the msr module into the kernel: + + $ sudo modprobe msr + +Finally, we probe the board: + + $ lspci -nnvvvxxxx > lspci.log 2> lspci.err.log + $ lsusb -vvv > lsusb.log 2> lsusb.err.log + $ superiotool -deV > superiotool.log 2> superiotool.err.log + $ inteltool -a > inteltool.log 2> inteltool.err.log + $ ectool -i > ectool.log 2> ectool.err.log + $ msrtool > msrtool.log 2> msrtool.err.log + $ dmidecode > dmidecode.log 2> dmidecode.err.log + $ biosdecode > biosdecode.log 2> biosdecode.err.log + $ nvramtool -x > nvramtool.log 2> nvramtool.err.log + $ dmesg > dmesg.log 2> dmesg.err.log + $ acpidump > acpidump.log 2> acpidump.err.log + $ for x in /sys/class/sound/card0/hw*; do cat "$x/init_pin_configs" \ + > pin_"$(basename "$x")"; done + $ for x in /proc/asound/card0/codec#*; do cat "$x" > \ + "$(basename "$x")"; done + $ cat /proc/cpuinfo > cpuinfo.log 2> cpuinfo.err.log + $ cat /proc/ioports > ioports.log 2> ioports.err.log + $ cat /sys/class/input/input*/id/bustype > input_bustypes.log + $flashrom -V -p internal:laptop=force_I_want_a_brick > \ + flashrom_info.log 2> flashrom_info.err.log + $ flashrom -V -p internal:laptop=force_I_want_a_brick -r rom.bin > \ + flashrom_read.log 2> flashrom_read.err.log + +[Rookie Guide: Lesson 1]: https://doc.coreboot.org/lessons/lesson1.html -- To view, visit https://review.coreboot.org/c/coreboot/+/31849 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3b8a99c10808c7e7ebc826b4d2f992774cc9a75 Gerrit-Change-Number: 31849 Gerrit-PatchSet: 1 Gerrit-Owner: Calvin <calvin.rempel(a)gmail.com> Gerrit-MessageType: newchange

2 1

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2020