coreboot-gerrit April 2020

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Change in ...coreboot[master]: RFC: smbios: allow setting BIOS-version string from VPD variable
by Łukasz Siudut (Code Review) 10 Jun '23

10 Jun '23

Łukasz Siudut has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32905 Change subject: RFC: smbios: allow setting BIOS-version string from VPD variable ...................................................................... RFC: smbios: allow setting BIOS-version string from VPD variable As in the title. Such approach allows for convenient setting of the firmware version and keep it in partition that is easily readable from both - coreboot binary and already running operating system. vpd_find is used directly as it returns pointer to vpd value which, by spec, is terminated by 0x00 (VPD_TYPE_TERMINATOR) anyway. This way we avoid copying string around and coming up with temporary buffer. Change-Id: If0e9d90ed0941c4e76e3e48cdcccf830ef789458 Signed-off-by: Lukasz Siudut <lsiudut(a)gmail.com> --- M src/arch/x86/smbios.c 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/32905/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 589f4f0..2ffd2dd 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -30,6 +30,9 @@ #include <memory_info.h> #include <spd.h> #include <cbmem.h> +#if CONFIG(VPD) +#include <drivers/vpd/vpd.h> +#endif #if CONFIG(CHROMEOS) #include <vendorcode/google/chromeos/gnvs.h> #endif @@ -347,6 +350,15 @@ const char *__weak smbios_mainboard_bios_version(void) { +#if CONFIG(VPD) + /* size is unused for now */ + int size; + const char *coreboot_vpd_version = vpd_find("version", &size, VPD_RO); + + /* if found, vpd value will be terminated by 0x00 (VPD_TYPE_TERMINATOR) */ + if(coreboot_vpd_version) + return coreboot_vpd_version; +#endif if (strlen(CONFIG_LOCALVERSION)) return CONFIG_LOCALVERSION; else -- To view, visit https://review.coreboot.org/c/coreboot/+/32905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0e9d90ed0941c4e76e3e48cdcccf830ef789458 Gerrit-Change-Number: 32905 Gerrit-PatchSet: 1 Gerrit-Owner: Łukasz Siudut Gerrit-MessageType: newchange

6 14

Change in coreboot[master]: [WIP]framebuffer_info: Add new method to specify an exact pixel format
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40798 ) Change subject: [WIP]framebuffer_info: Add new method to specify an exact pixel format ...................................................................... [WIP]framebuffer_info: Add new method to specify an exact pixel format Add an enum for framebuffer pixel formats. This allows to get rid of the imprecise BPP argument used for now. Add a test pattern generator to easily test the framebuffer format. Tested on qemu cirrus and bochs VGA. Change-Id: Ice6f3fa73d5d40e5e35073b85c53a76e35cc93ad Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/device/Kconfig M src/drivers/emulation/qemu/bochs.c M src/drivers/emulation/qemu/cirrus.c M src/drivers/intel/fsp1_1/fsp_gop.c M src/include/framebuffer_info.h M src/lib/framebuffer_info.c M src/mainboard/google/daisy/mainboard.c M src/mainboard/google/peach_pit/mainboard.c M src/soc/nvidia/tegra124/display.c 9 files changed, 162 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/40798/1 diff --git a/src/device/Kconfig b/src/device/Kconfig index 951062c..7e3a60c 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -467,6 +467,16 @@ image in the 'General' section or add it manually to CBFS, using, for example, cbfstool. +config FRAMEBUFFER_PATTERN + prompt "Show test pattern on screen" + bool + depends on LINEAR_FRAMEBUFFER + help + This option shows a red, green, blue, white test pattern on the screen + from the left to the right. + + Can be used for framebuffer debugging. + config LINEAR_FRAMEBUFFER_MAX_WIDTH int "Maximum width in pixels" depends on LINEAR_FRAMEBUFFER && MAINBOARD_USE_LIBGFXINIT diff --git a/src/drivers/emulation/qemu/bochs.c b/src/drivers/emulation/qemu/bochs.c index ad50a0b..bacc6c0 100644 --- a/src/drivers/emulation/qemu/bochs.c +++ b/src/drivers/emulation/qemu/bochs.c @@ -102,7 +102,7 @@ outb(0x20, 0x3c0); /* disable blanking */ /* Advertise new mode */ - fb_add_framebuffer_info(addr, width, height, 32, 1); + fb_add_framebuffer_info_pf(addr, width, height, PF_32BPP_XRGB8, 1); } static void bochs_init_text_mode(struct device *dev) diff --git a/src/drivers/emulation/qemu/cirrus.c b/src/drivers/emulation/qemu/cirrus.c index bb24e77..d920c89 100644 --- a/src/drivers/emulation/qemu/cirrus.c +++ b/src/drivers/emulation/qemu/cirrus.c @@ -311,7 +311,7 @@ vga_sr_write (CIRRUS_SR_EXTENDED_MODE, sr_ext); write_hidden_dac (hidden_dac); - fb_add_framebuffer_info(addr, width, height, 32, 8); + fb_add_framebuffer_info_pf(addr, width, height, PF_32BPP_XRGB8, 8); } static void cirrus_init_text_mode(struct device *dev) diff --git a/src/drivers/intel/fsp1_1/fsp_gop.c b/src/drivers/intel/fsp1_1/fsp_gop.c index 6b0d647..593e2d0 100644 --- a/src/drivers/intel/fsp1_1/fsp_gop.c +++ b/src/drivers/intel/fsp1_1/fsp_gop.c @@ -22,10 +22,10 @@ printk(BIOS_DEBUG, "FSP_DEBUG: Graphics Data HOB present\n"); vbt_gop = GET_GUID_HOB_DATA(vbt_hob); - fb_add_framebuffer_info(vbt_gop->FrameBufferBase, + fb_add_framebuffer_info_pf(vbt_gop->FrameBufferBase, vbt_gop->GraphicsMode.HorizontalResolution, vbt_gop->GraphicsMode.VerticalResolution, - 32, + PF_32BPP_BGRX8, 64); } diff --git a/src/include/framebuffer_info.h b/src/include/framebuffer_info.h index b4bdad6..8c34d56 100644 --- a/src/include/framebuffer_info.h +++ b/src/include/framebuffer_info.h @@ -24,6 +24,22 @@ uint32_t y_resolution, uint8_t bits_per_pixel, uint32_t row_alignment); +enum fb_pixelformat { + PF_UNKNOWN = 0, + PF_16BPP_B5G6R5, + PF_24BPP_RGB8, + PF_24BPP_BGR8, + PF_32BPP_XRGB8, + PF_32BPP_XBGR8, + PF_32BPP_BGRX8, + PF_32BPP_RGBX8, +}; + +struct fb_info *fb_add_framebuffer_info_pf(uintptr_t fb_addr, uint32_t x_resolution, + uint32_t y_resolution, enum fb_pixelformat pf, + uint32_t row_alignment); + + void fb_set_orientation(struct fb_info *info, enum lb_fb_orientation orientation); diff --git a/src/lib/framebuffer_info.c b/src/lib/framebuffer_info.c index b8a7bae..18a2e0b 100644 --- a/src/lib/framebuffer_info.c +++ b/src/lib/framebuffer_info.c @@ -51,6 +51,71 @@ return ret; } +static void fb_set_pixel(struct lb_framebuffer *fb, uint32_t x, uint32_t y, + uint8_t r, uint8_t g, uint8_t b) +{ + uint8_t *fb_ptr = (uint8_t *)(uintptr_t)fb->physical_address; + fb_ptr += fb->bytes_per_line * y; + fb_ptr += (fb->bits_per_pixel/8) * x; + uint32_t *tmp; + + if (fb->bits_per_pixel > 32) + return; + + if (fb->red_mask_size < sizeof(r) * 8) + r >>= sizeof(r) * 8 - fb->red_mask_size; + + if (fb->green_mask_size < sizeof(g) * 8) + g >>= sizeof(g) * 8 - fb->green_mask_size; + + if (fb->blue_mask_size < sizeof(b) * 8) + b >>= sizeof(b) * 8 - fb->blue_mask_size; + + tmp = (uint32_t *)fb_ptr; + for (uint8_t i = 0; i < sizeof(*tmp) * 8; i++) { + if (i >= fb->red_mask_pos && i < (fb->red_mask_pos + fb->red_mask_size)) { + if (r & 1) + *tmp |= 1 << i; + else + *tmp &= ~(1 << i); + r >>= 1; + } + if (i >= fb->green_mask_pos && i < (fb->green_mask_pos + fb->green_mask_size)) { + if (g & 1) + *tmp |= 1 << i; + else + *tmp &= ~(1 << i); + g >>= 1; + } + if (i >= fb->blue_mask_pos && i < (fb->blue_mask_pos + fb->blue_mask_size)) { + if (b & 1) + *tmp |= 1 << i; + else + *tmp &= ~(1 << i); + b >>= 1; + } + } +} + +/* Generate a red, green, blue, white test pattern from the left to the right */ +static void set_test_pattern(struct lb_framebuffer *fb) +{ + for (int y = fb->y_resolution / 4; y < fb->y_resolution / 4 * 3; y++) { + for (int x = 0; x < fb->x_resolution; x++) { + if (x < fb->x_resolution / 4) + fb_set_pixel(fb, x, y, 0xff, 0, 0); + else if ((x >= fb->x_resolution / 4) && + (x < fb->x_resolution / 2)) + fb_set_pixel(fb, x, y, 0, 0xff, 0); + else if ((x >= fb->x_resolution / 2) && + (x < fb->x_resolution / 4 * 3)) + fb_set_pixel(fb, x, y, 0, 0, 0xff); + else + fb_set_pixel(fb, x, y, 0xff, 0xff, 0xff); + } + } +} + /* * Fills a provided framebuffer info struct and adds it to the internal list if it's * valid. Returns NULL on error. @@ -131,6 +196,9 @@ { struct fb_info *info = NULL; + printk(BIOS_WARNING, "%s: The use of this function is deprecated." + "Please provide a meaningful pixel format.\n", __func__); + switch (bits_per_pixel) { case 32: case 24: /* FIXME: 24 BPP might be RGB8 or XRGB8 */ @@ -154,6 +222,65 @@ return info; } +struct fb_info *fb_add_framebuffer_info_pf(uintptr_t fb_addr, uint32_t x_resolution, + uint32_t y_resolution, enum fb_pixelformat pf, + uint32_t row_alignment) +{ + struct fb_info *info = NULL; + + switch (pf) { + case PF_32BPP_XBGR8: + /* packed into 4-byte words */ + info = fb_add_framebuffer_info_ex(fb_addr, x_resolution, y_resolution, + 32, row_alignment, 24, 8, 0, + 8, 8, 8, 16, 8); + break; + case PF_32BPP_XRGB8: + /* packed into 4-byte words */ + info = fb_add_framebuffer_info_ex(fb_addr, x_resolution, y_resolution, + 32, row_alignment, 24, 8, 16, + 8, 8, 8, 0, 8); + break; + case PF_32BPP_BGRX8: + /* packed into 4-byte words */ + info = fb_add_framebuffer_info_ex(fb_addr, x_resolution, y_resolution, + 32, row_alignment, 0, 8, 8, + 8, 16, 8, 24, 8); + break; + case PF_32BPP_RGBX8: + /* packed into 4-byte words */ + info = fb_add_framebuffer_info_ex(fb_addr, x_resolution, y_resolution, + 32, row_alignment, 0, 8, 24, + 8, 16, 8, 0, 8); + break; + case PF_24BPP_RGB8: + /* packed into 3-byte words */ + info = fb_add_framebuffer_info_ex(fb_addr, x_resolution, y_resolution, + 24, row_alignment, 0, 0, 16, + 8, 8, 8, 0, 8); + break; + case PF_24BPP_BGR8: + /* packed into 3-byte words */ + info = fb_add_framebuffer_info_ex(fb_addr, x_resolution, y_resolution, + 24, row_alignment, 0, 0, 0, + 8, 8, 8, 16, 8); + break; + case PF_16BPP_B5G6R5: + /* packed into 2-byte words */ + info = fb_add_framebuffer_info_ex(fb_addr, x_resolution, y_resolution, + 16, row_alignment, 0, 0, 11, + 5, 5, 6, 0, 5); + break; + default: + printk(BIOS_ERR, "%s: unsupported pixel format %d\n", __func__, pf); + } + if (!info) { + printk(BIOS_ERR, "%s: failed to add framebuffer info\n", __func__); + } + return info; + +} + void fb_set_orientation(struct fb_info *info, enum lb_fb_orientation orientation) { if (!info) @@ -191,6 +318,8 @@ unsigned int depth = framebuffer->bits_per_pixel; //FIXME: Temporary cache the bootsplash outside of this loop set_bootsplash(fb_ptr, width, height, depth); + } else if (CONFIG(FRAMEBUFFER_PATTERN)) { + set_test_pattern(framebuffer); } } diff --git a/src/mainboard/google/daisy/mainboard.c b/src/mainboard/google/daisy/mainboard.c index 7a51c7e..8f5f734 100644 --- a/src/mainboard/google/daisy/mainboard.c +++ b/src/mainboard/google/daisy/mainboard.c @@ -255,7 +255,7 @@ sdmmc_vdd(); - fb_add_framebuffer_info((uintptr_t)fb_addr, 1366, 768, 16, 0); + fb_add_framebuffer_info_pf((uintptr_t)fb_addr, 1366, 768, PF_16BPP_B5G6R5, 0); lcd_vdd(); diff --git a/src/mainboard/google/peach_pit/mainboard.c b/src/mainboard/google/peach_pit/mainboard.c index 1d60e3b..b5dd35f 100644 --- a/src/mainboard/google/peach_pit/mainboard.c +++ b/src/mainboard/google/peach_pit/mainboard.c @@ -394,7 +394,7 @@ sdmmc_vdd(); - fb_add_framebuffer_info((uintptr_t)fb_addr, 1366, 768, 16, 0); + fb_add_framebuffer_info_pf((uintptr_t)fb_addr, 1366, 768, PF_16BPP_B5G6R5, 0); /* * The reset value for FIMD SYSMMU register MMU_CTRL:0x14640000 diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index c64d19d..dd3a1ce 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -314,7 +314,7 @@ /* tell depthcharge ... */ - fb_add_framebuffer_info((uintptr_t)(framebuffer_base_mb*MiB), + fb_add_framebuffer_info_pf((uintptr_t)(framebuffer_base_mb*MiB), config->xres, config->yres, config->framebuffer_bits_per_pixel, -- To view, visit https://review.coreboot.org/c/coreboot/+/40798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice6f3fa73d5d40e5e35073b85c53a76e35cc93ad Gerrit-Change-Number: 40798 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

5 9

Change in coreboot[master]: soc/intel/common/block/systemagent: Add choice option for PCIEX_LENGTH
by Subrata Banik (Code Review) 10 Jun '23

10 Jun '23

Hello Usha P, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/40379 to review the following change. Change subject: soc/intel/common/block/systemagent: Add choice option for PCIEX_LENGTH ...................................................................... soc/intel/common/block/systemagent: Add choice option for PCIEX_LENGTH This patch adds choice option for PCIEX_LENGTH related Kconfig to avoid multiple selection from SoC Kconfig. Change-Id: Icb61e9a0263c058726cc07442af1985a96bf37c2 Signed-off-by: Usha P <usha.p(a)intel.com> --- M src/soc/intel/common/block/systemagent/Kconfig 1 file changed, 12 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/40379/1 diff --git a/src/soc/intel/common/block/systemagent/Kconfig b/src/soc/intel/common/block/systemagent/Kconfig index 6dd1f3b..ea75d5b 100644 --- a/src/soc/intel/common/block/systemagent/Kconfig +++ b/src/soc/intel/common/block/systemagent/Kconfig @@ -18,14 +18,23 @@ help This option allows you to select length of PCIEX region. +choice + prompt "Length of PCI Express Base Address Region" + default PCIEX_LENGTH_256MB + help + This is to provide new kconfig option that can be used to + select PCI Express Base Address Length. + config PCIEX_LENGTH_256MB - bool + bool "256 MiB" config PCIEX_LENGTH_128MB - bool + bool "128 MiB" config PCIEX_LENGTH_64MB - bool + bool "64 MiB" + +endchoice config SA_ENABLE_IMR bool -- To view, visit https://review.coreboot.org/c/coreboot/+/40379 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb61e9a0263c058726cc07442af1985a96bf37c2 Gerrit-Change-Number: 40379 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-MessageType: newchange

10 20

Change in coreboot[master]: mb/google/hatch: Make Nightfury variant alphabettically sorted
by Edward O'Callaghan (Code Review) 10 Jun '23

10 Jun '23

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40400 ) Change subject: mb/google/hatch: Make Nightfury variant alphabettically sorted ...................................................................... mb/google/hatch: Make Nightfury variant alphabettically sorted Change-Id: I21a710ee0df45188f1f43aad61967069faf88fdb Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name 2 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/40400/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 2419722..6eff9070 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -103,8 +103,8 @@ default "Kindred" if BOARD_GOOGLE_KINDRED default "Kohaku" if BOARD_GOOGLE_KOHAKU default "Mushu" if BOARD_GOOGLE_MUSHU - default "Palkia" if BOARD_GOOGLE_PALKIA default "Nightfury" if BOARD_GOOGLE_NIGHTFURY + default "Palkia" if BOARD_GOOGLE_PALKIA default "Puff" if BOARD_GOOGLE_PUFF default "Kaisa" if BOARD_GOOGLE_KAISA default "Stryke" if BOARD_GOOGLE_STRYKE @@ -131,8 +131,8 @@ default "kindred" if BOARD_GOOGLE_KINDRED default "kohaku" if BOARD_GOOGLE_KOHAKU default "mushu" if BOARD_GOOGLE_MUSHU - default "palkia" if BOARD_GOOGLE_PALKIA default "nightfury" if BOARD_GOOGLE_NIGHTFURY + default "palkia" if BOARD_GOOGLE_PALKIA default "puff" if BOARD_GOOGLE_PUFF default "kaisa" if BOARD_GOOGLE_KAISA default "stryke" if BOARD_GOOGLE_STRYKE diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index ce34211..f3f944f 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -60,6 +60,12 @@ select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP select BOARD_ROMSIZE_KB_16384 +config BOARD_GOOGLE_NIGHTFURY + bool "-> Nightfury" + select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP + select BOARD_ROMSIZE_KB_16384 + config BOARD_GOOGLE_PALKIA bool "-> Palkia" select BOARD_GOOGLE_BASEBOARD_HATCH @@ -68,12 +74,6 @@ select CHROMEOS_DSM_CALIB select DRIVERS_I2C_RT1011 -config BOARD_GOOGLE_NIGHTFURY - bool "-> Nightfury" - select BOARD_GOOGLE_BASEBOARD_HATCH - select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP - select BOARD_ROMSIZE_KB_16384 - config BOARD_GOOGLE_PUFF bool "-> Puff" select BOARD_GOOGLE_BASEBOARD_HATCH -- To view, visit https://review.coreboot.org/c/coreboot/+/40400 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21a710ee0df45188f1f43aad61967069faf88fdb Gerrit-Change-Number: 40400 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

5 8

Change in coreboot[master]: [TESTONLY]cpu/intel/socket_mPGA604: Run romstage from CAR
by Arthur Heymans (Code Review) 10 Jun '23

10 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36564 ) Change subject: [TESTONLY]cpu/intel/socket_mPGA604: Run romstage from CAR ...................................................................... [TESTONLY]cpu/intel/socket_mPGA604: Run romstage from CAR With a pentium 4 CPU running WP XIP is not possible. To speed up execution copying romstage to CAR might work? TEST: does it boot? is it faster? Change-Id: I4c35d09b87b545944a4465ff695953d1e8a811e4 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/memlayout.ld M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/intel/socket_mPGA604/Kconfig 3 files changed, 20 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/36564/1 diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index 9fd9889..ed89894 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -39,7 +39,7 @@ #elif ENV_ROMSTAGE /* The 1M size is not allocated. It's just for basic size checking. * Link at 32MiB address and rely on cbfstool to relocate to XIP. */ - ROMSTAGE(CONFIG_ROMSTAGE_ADDR, 1M) + ROMSTAGE(CONFIG_ROMSTAGE_ADDR, CONFIG_DCACHE_ROMSTAGE_SIZE) #include EARLY_MEMLAYOUT #elif ENV_VERSTAGE diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 2cd0c5e..fdb5ddc 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -23,9 +23,17 @@ .set ap_sipi_vector_in_rom, 0xff #endif -#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE +#define CACHE_AS_RAM_SIZE (CONFIG_DCACHE_RAM_SIZE + CONFIG_DCACHE_ROMSTAGE_SIZE) #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE +#if (CACHE_AS_RAM_BASE & (CACHE_AS_RAM_SIZE - 1)) +#error "CONFIG_DCACHE_RAM_BASE is not aligned!" +#endif + +#if ((CACHE_AS_RAM_SIZE & (CACHE_AS_RAM_SIZE - 1)) != 0) +#error "Cache-as-Ram size must be a power of 2!" +#endif + #if CONFIG(C_ENVIRONMENT_BOOTBLOCK) #if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0) #error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!" diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index 4ec46e0..5f9eb9c 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -15,6 +15,7 @@ select C_ENVIRONMENT_BOOTBLOCK select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE + select NO_XIP_EARLY_STAGES # mPGA604 are usually Intel Netburst CPUs which should have SSE2 # but the ramtest.c code on the Dell S1850 seems to choke on @@ -25,7 +26,7 @@ config DCACHE_RAM_BASE hex - default 0xfefc0000 + default 0xfef0000 config DCACHE_RAM_SIZE hex @@ -35,4 +36,12 @@ hex default 0x2000 +config DCACHE_ROMSTAGE_SIZE + hex + default 0xc000 + +config ROMSTAGE_ADRR + hex + default 0xfef4000 + endif # CPU_INTEL_SOCKET_MPGA604 -- To view, visit https://review.coreboot.org/c/coreboot/+/36564 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c35d09b87b545944a4465ff695953d1e8a811e4 Gerrit-Change-Number: 36564 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 17

Change in coreboot[master]: msrtool: Fix enum type declaration
by Peter Lemenkov (Code Review) 10 Jun '23

10 Jun '23

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39162 ) Change subject: msrtool: Fix enum type declaration ...................................................................... msrtool: Fix enum type declaration This patch fixes compilation and linking with GCC 10: * https://kojipkgs.fedoraproject.org//work/tasks/3541/41983541/build.log ``` gcc -o msrtool msrtool.o msrutils.o sys.o linux.o darwin.o freebsd.o geodegx2.o geodelx.o cs5536.o k8.o via_c7.o intel_pentium3_early.o intel_pentium3.o intel_pentium4_early.o intel_pentium4_later.o intel_pentium_d.o intel_core1.o intel_core2_early.o intel_core2_later.o intel_nehalem.o intel_atom.o -Wl,-z,relro -Wl,--as-needed -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -L/lib64 -lpci /usr/bin/ld: msrutils.o:/builddir/build/BUILD/coreboot-4.10/util/msrtool/msrtool.h:50: multiple definition of `PresentTypes'; msrtool.o:/builddir/build/BUILD/coreboot-4.10/util/msrtool/msrtool.h:50: first defined here /usr/bin/ld: msrutils.o:/builddir/build/BUILD/coreboot-4.10/util/msrtool/msrtool.h:40: multiple definition of `MsrTypes'; msrtool.o:/builddir/build/BUILD/coreboot-4.10/util/msrtool/msrtool.h:40: first defined here ``` Look at this expression: enum { ... } name; It declares a variable with type of anonymous enumeration. Before GCC 10 it wasn't an issue since compiler defines -fcommon. With GCC 10 this declaration is no longer permitted - see the following link for further details: * https://gcc.gnu.org/gcc-10/porting_to.html#common * https://wiki.gentoo.org/wiki/Gcc_10_porting_notes/fno_common Let's remove unnecessary variable declaration. Change-Id: Ie154375ad6e3c1845f7937dac0121f3b63b6dd63 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M util/msrtool/msrtool.h 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/39162/1 diff --git a/util/msrtool/msrtool.h b/util/msrtool/msrtool.h index 8cba4c7..192ebf2 100644 --- a/util/msrtool/msrtool.h +++ b/util/msrtool/msrtool.h @@ -32,14 +32,14 @@ #define HEXCHARS "0123456789abcdefABCDEF" -enum { +enum MsrTypes { MSRTYPE_RDONLY, MSRTYPE_RDWR, MSRTYPE_WRONLY, MSRTYPE_EOT -} MsrTypes; +}; -enum { +enum PresentTypes { PRESENT_RSVD, PRESENT_DEC, PRESENT_BIN, @@ -47,7 +47,7 @@ PRESENT_HEX, PRESENT_HEXDEC, PRESENT_STR, -} PresentTypes; +}; struct msr { uint32_t hi; -- To view, visit https://review.coreboot.org/c/coreboot/+/39162 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie154375ad6e3c1845f7937dac0121f3b63b6dd63 Gerrit-Change-Number: 39162 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: [RFC, scratch] Documentation/fsp: Start discussion around FSP-S issues
by Nico Huber (Code Review) 10 Jun '23

10 Jun '23

Hello Aaron Durbin, Patrick Rudolph, Arthur Heymans, Michael Niewöhner, Duncan Laurie, David Wu, Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/36328 to review the following change. Change subject: [RFC, scratch] Documentation/fsp: Start discussion around FSP-S issues ...................................................................... [RFC, scratch] Documentation/fsp: Start discussion around FSP-S issues To get some discussion started, list some heavy issues with FSP(-S). I've copy pasted some things together, and added a few words on top and bottom. Not sure yet, where this should lead. To convince Intel to contribute open-source code on their own, we might want to add a list of initialization steps, that should be open. Feel free to amend this commit in any way :) Change-Id: Ied0d8ad60fa487272a05fc73b16a7c343cc4d993 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- A Documentation/fsp/fsp-s_discussion.md 1 file changed, 165 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/36328/1 diff --git a/Documentation/fsp/fsp-s_discussion.md b/Documentation/fsp/fsp-s_discussion.md new file mode 100644 index 0000000..7ac649a --- /dev/null +++ b/Documentation/fsp/fsp-s_discussion.md @@ -0,0 +1,165 @@ +Introduction +============ + +*FSP* is an ABI that allows silicon vendors to provide pre-compiled +binaries of their silicon-initialization code for the integration +into firmware frameworks such as coreboot. Current, 2.x versions +of *FSP* describe three binaries with rough responsibilities: + +* `FSP-T`: Sets up a temporary RAM environment (usually some sort + of Cache as RAM, CAR) among other things. + +* `FSP-M`: Initializes the memory (DRAM) controller, among other + things. + +* `FSP-S`: Performs various silicon-initialization steps left. + +However, what operations these binaries perform exactly and what +operations are left to the firmware framework, is neither specified +nor documented. + +Historically, all these responsibilities were left to coreboot. +Later, pre-compiled reference code for the memory-controller +initialization was introduced, then for other silicon init, and +finally there are attempts to replace coreboot's CAR setup with +FSP-T. + +While the FSP-M integration saves coreboot developers time, because +of the complex nature of the memory-controller initialization, the +integration of FSP-S turns out to be harder than implementing the +necessary code natively in coreboot. We'll discuss why that is the +case and provide an incomplete list of issues with current FSP-S +binaries. + + +Bug Fixing +---------- + +Many companies rely on the pre-built FSP binaries. Yet, there is +no common procedure to get bugs fixed or even acknowledged. This +leads to an increase of workarounds in firmware frameworks, +especially for older hardware generations. + + +Lack of Documentation +--------------------- + +Many of the initialization steps performed by FSP-S are merely +translating mainboard-specific configuration into register settings. +This is reflected by a list of hundreds of configuration options of +FSP-S. While these steps are quite simple, the additional translation +from FSP options to register values heavily increases the integration +costs. Not only are the register settings usually much better documented +than their FSP counterparts, but FSP also uses different terms so that +the existing hardware documentation often can't assist developers when +dealing with FSP. + +FSP-S also performs locking of several registers so that they can't +be written anymore afterwards. It is not documented what locks are +set by FSP. This creates heavy security issues for multiple reasons: + +* One either has to assume that FSP doesn't perform any locking + and do it redundantly in the firmware framework, or expensively + test what is locked and keep doing so for every new FSP revision. + +* Some registers may be locked before they are configured in a + secure manner. This may result in workarounds in the firmware + framework to configure things early. Sometimes it's even + impossible to do so, because relevant information isn't + available yet. + +This shows that no matter the many options that are implemented in +FSP-S, there will always be things that must be controlled by the +firmware framework. Locking should either be a separate, last step +in FSP, or be left entirely to the firmware framework. And most of +all, the locking has to be documented. + + +Arbitrary Interface Changes +--------------------------- + +Within coreboot, we try to keep code-compatibility with older hardware +generations. The FSP ABI isn't stable, however. Even when the hardware +doesn't change between minor platform updates, the configuration +settings of FSP are sometimes adapted without backwards compatibility +in mind. This increases costs, just to translate configuration data +from one representation to another only to let FSP translate it again. +In such cases, directly configuring registers from coreboot, would +save two layers of indirection. + +Another problem is the disappearance of options in newer FSP releases. +See [SpiFlashCfgLockDown UPD vanished after KBL] +(https://github.com/IntelFsp/FSP/issues/25), for instance. Current +coreboot code seems to still rely on this option. It boots, though, +only security assumptions are broken. Which again shows, locking +shouldn't be part of FSP, or at least optional. + + +FSP Switches SAI +---------------- + +A problem that multiplies with the lack of documentation is that FSP-S +switches to `POSTBOOT_SAI` on newer platforms. While it probably tries +to achieve the opposite, this undermines firmware quality and security. + +* In some firmware frameworks FSP may run long before End-of-Post, this + means most of the framework runs with `POSTBOOT_SAI`. + +* In the EDS, implications of the SAI switch are _not_ documented. + Virtually for every register, it is unknown if it is still accessible + after the SAI switch. This seems to be a problem for developers both + inside and outside of Intel. + +* The SAI switch seems to force the firmware framework to do some things + in SMM. However, the use of SMM as a more privileged execution mode is + generally discouraged. This means FSP forces firmware development to + go backwards. + +Especially the lack of documentation leads to many bugs in firmware. +Even Intel developers working on coreboot don't seem to know the +implications of the SAI switch or lack the resources to re-evaluate +all code wrt. the SAI switch. + + +FSP Creates Legal Uncertainty +----------------------------- + +Many companies sell coreboot together with FSP as part of their products. +Especially, the function pointers to GPL code that were introduced with +FSP 2.1 seem unprecedented. However, they could be compared with runtime +linking which seems troubling. + + +Mitigations +----------- + +None of the listed issues would exist if FSP were open-source and the +initialization steps could be integrated into coreboot, like they were +before. An open-source approach would not only cut costs heavily but +might also decrease time-to-market if the whole coreboot community +could work together on new platforms. + +However, in the absence of such a firmware-development utopia, there +may be more realistic approaches. As mentioned earlier, not all of FSP +has a negative impact on development performance. FSP-M, for instance, +rarely causes trouble. And due to its complex nature, it is no surprise +if memory-controller initialization is kept secret. The configuration +done by FSP-S, on the other hand, overlaps with many of coreboot's +responsibilities. The few lines of code in FSP-S that help to get a +mainboard running, don't outweigh the damage it does. However, one +can't have the cherries without taking the whole menu, which takes +years to digest. + +One approach could be to split FSP-S further up and identify parts +that are necessarily closed source and parts that could as well be +reimplemented in coreboot. However, if parts that are left closed +source change the state of the execution environment (e.g. switch +SAI), finalize any settings or raise legal concerns, the ABI would +have to change to solve all aforementioned issues. + +Another approach could be to align older platforms with open-source +coreboot, step by step. Currently, everything from Skylake on relies +on FSP-S. However, it seems Intel has already abandoned development +for this platform (while the coreboot integration was never finished). +It would seem reasonable to release abandoned code to the public, or +at least clear existing documentation for older platforms from NDAs. -- To view, visit https://review.coreboot.org/c/coreboot/+/36328 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied0d8ad60fa487272a05fc73b16a7c343cc4d993 Gerrit-Change-Number: 36328 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Wu <david_wu(a)quantatw.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

15 60

Change in ...coreboot[master]: for review d945gclf/Kconig and devicetree.cb . these files are modif...
by junaid (Code Review) 10 Jun '23

10 Jun '23

junaid has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30798 Change subject: for review d945gclf/Kconig and devicetree.cb . these files are modified according to the superIO chip Winbond w83627DHG ...................................................................... for review d945gclf/Kconig and devicetree.cb . these files are modified according to the superIO chip Winbond w83627DHG Change-Id: I1449d9351bd1b76ecad16e6d81c501c1d4dd80f5 Signed-off-by: junaid <junaidimpex(a)gmail.com> --- M src/mainboard/intel/d945gclf/Kconfig M src/mainboard/intel/d945gclf/devicetree.cb 2 files changed, 37 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/30798/1 diff --git a/src/mainboard/intel/d945gclf/Kconfig b/src/mainboard/intel/d945gclf/Kconfig index 70fa848..906dd01 100644 --- a/src/mainboard/intel/d945gclf/Kconfig +++ b/src/mainboard/intel/d945gclf/Kconfig @@ -20,7 +20,8 @@ select NORTHBRIDGE_INTEL_I945 select NORTHBRIDGE_INTEL_SUBTYPE_I945GC select SOUTHBRIDGE_INTEL_I82801GX - select SUPERIO_SMSC_LPC47M15X +## changed as per Advantech SOM 4461 + select SUPERIO_WINBOND_W83627DHG select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select HAVE_PIRQ_TABLE diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb index 90c517f..864775a 100644 --- a/src/mainboard/intel/d945gclf/devicetree.cb +++ b/src/mainboard/intel/d945gclf/devicetree.cb @@ -65,44 +65,42 @@ device pci 1d.1 on end # USB UHCI device pci 1d.2 on end # USB UHCI device pci 1d.3 off end # USB UHCI - device pci 1d.7 on end # USB2 EHCI - device pci 1e.0 on end # PCI bridge - device pci 1e.2 off end # AC'97 Audio + device pci 1d.7 on end # USB2 EHCI + device pci 1e.0 on end # PCI bridge + device pci 1e.2 off end # AC'97 Audio device pci 1e.3 off end # AC'97 Modem device pci 1f.0 on # LPC bridge - chip superio/smsc/lpc47m15x - device pnp 2e.0 off # Floppy - end - device pnp 2e.3 off # Parport - end - device pnp 2e.4 on - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.5 on - io 0x60 = 0x2f8 - irq 0x70 = 3 - irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq - end - device pnp 2e.7 on # Keyboard+Mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - irq 0xf0 = 0x82 # HW accel A20. - end - device pnp 2e.8 on # GAME - # all default - end - device pnp 2e.a on # PME - end - device pnp 2e.b on # MPU - end - end - end + chip superio/winbond/w83627dhg + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # Parallel Port + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard,Mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + #device pnp 2e.6 off end # SPI + device pnp 2e.307 off end # GPIO6 + device pnp 2e.8 off end # WDTO, PLED + device pnp 2e.009 off end # GPIO2 + device pnp 2e.109 off end # GPIO3 + device pnp 2e.209 off end # GPIO4 + device pnp 2e.309 off end # GPIO5 + device pnp 2e.A off end # ACPI + device pnp 2e.B off end # HW Monitor + end # w83627dhg + end device pci 1f.1 off end # IDE - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus - end - end + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMBus + end + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/30798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1449d9351bd1b76ecad16e6d81c501c1d4dd80f5 Gerrit-Change-Number: 30798 Gerrit-PatchSet: 1 Gerrit-Owner: junaid <junaidimpex(a)gmail.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: configs/builder/config.ocp.sonorapass: Config for SonoraPass PO. src/...
by Ryback Hung (Code Review) 10 Jun '23

10 Jun '23

Ryback Hung has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40334 ) Change subject: configs/builder/config.ocp.sonorapass: Config for SonoraPass PO. src/mainboard/ocp/sonorapass/*.*: Preliminiary platform porting for SonoraPass PO. ...................................................................... configs/builder/config.ocp.sonorapass: Config for SonoraPass PO. src/mainboard/ocp/sonorapass/*.*: Preliminiary platform porting for SonoraPass PO. It can boot SonoraPass EVT board w/ ES1 CPX-SP and ES PCH. Due to IRQs issue, it has yet to boot into Linuxboot/u-root payload. Change-Id: I60452205d666fd19582780401ccd9d7773e68a5b --- A configs/builder/config.ocp.sonorapass A src/mainboard/ocp/sonorapass/Kconfig A src/mainboard/ocp/sonorapass/Kconfig.name A src/mainboard/ocp/sonorapass/Makefile.inc A src/mainboard/ocp/sonorapass/acpi/platform.asl A src/mainboard/ocp/sonorapass/board.fmd A src/mainboard/ocp/sonorapass/board_info.txt A src/mainboard/ocp/sonorapass/bootblock.c A src/mainboard/ocp/sonorapass/devicetree.cb A src/mainboard/ocp/sonorapass/dsdt.asl 10 files changed, 320 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/40334/1 diff --git a/configs/builder/config.ocp.sonorapass b/configs/builder/config.ocp.sonorapass new file mode 100644 index 0000000..c05dce2 --- /dev/null +++ b/configs/builder/config.ocp.sonorapass @@ -0,0 +1,21 @@ +# type this to get working .config: +# make defconfig KBUILD_DEFCONFIG=configs/builder/config.ocp.sonorapass + +CONFIG_VENDOR_OCP=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="site-local/cedarisland_crb/ucode-05-06-5a" +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_T_FILE="site-local/cedarisland_crb/Server_T.fd" +CONFIG_FSP_M_FILE="site-local/cedarisland_crb/Server_M.fd" +CONFIG_FSP_S_FILE="site-local/cedarisland_crb/Server_S.fd" +CONFIG_ME_BIN_PATH="site-local/sonorapass/me.bin" +CONFIG_IFD_BIN_PATH="site-local/sonorapass/descriptor.bin" +CONFIG_CONSOLE_SERIAL_57600=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +CONFIG_PAYLOAD_LINUX=y +CONFIG_PAYLOAD_FILE="site-local/linuxboot_uroot_ttys0" +CONFIG_LINUX_COMMAND_LINE="earlyprintk=uart8250,io,0x3f8,57600n1 console=uart8250,io,0x3f8,57600n1 loglevel=7" diff --git a/src/mainboard/ocp/sonorapass/Kconfig b/src/mainboard/ocp/sonorapass/Kconfig new file mode 100644 index 0000000..34adf5f --- /dev/null +++ b/src/mainboard/ocp/sonorapass/Kconfig @@ -0,0 +1,43 @@ +## +## This file is part of the coreboot project. +## +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_OCP_SONORAPASS + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_65536 + select MAINBOARD_USES_FSP2_0 + select IPMI_KCS + select SOC_INTEL_COOPERLAKE_SP + select SUPERIO_ASPEED_AST2400 + select HAVE_ACPI_TABLES + +config MAINBOARD_DIR + string + default "ocp/sonorapass" + +config MAINBOARD_PART_NUMBER + string + default "SonoraPass" + +config MAINBOARD_FAMILY + string + default "SonoraPass" + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" + +endif diff --git a/src/mainboard/ocp/sonorapass/Kconfig.name b/src/mainboard/ocp/sonorapass/Kconfig.name new file mode 100644 index 0000000..90e7f3d --- /dev/null +++ b/src/mainboard/ocp/sonorapass/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_OCP_SONORAPASS + bool "SonoraPass" diff --git a/src/mainboard/ocp/sonorapass/Makefile.inc b/src/mainboard/ocp/sonorapass/Makefile.inc new file mode 100644 index 0000000..8501868 --- /dev/null +++ b/src/mainboard/ocp/sonorapass/Makefile.inc @@ -0,0 +1 @@ +bootblock-y += bootblock.c diff --git a/src/mainboard/ocp/sonorapass/acpi/platform.asl b/src/mainboard/ocp/sonorapass/acpi/platform.asl new file mode 100644 index 0000000..75c1b92 --- /dev/null +++ b/src/mainboard/ocp/sonorapass/acpi/platform.asl @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +Name(\APC1, Zero) // IIO IOAPIC + +Name(\PICM, Zero) // IOAPIC/8259 + +Method(_PIC, 1) +{ + Store(Arg0, PICM) +} + +/* + * The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} diff --git a/src/mainboard/ocp/sonorapass/board.fmd b/src/mainboard/ocp/sonorapass/board.fmd new file mode 100644 index 0000000..e28bcf0 --- /dev/null +++ b/src/mainboard/ocp/sonorapass/board.fmd @@ -0,0 +1,10 @@ +FLASH@0xfc000000 64M { + SI_ALL@0x0 0x2fd8000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x2fc5000 + } + FMAP@0x03000000 0x800 + RW_MRC_CACHE@0x3000800 0x10000 + COREBOOT(CBFS)@0x3010800 +} diff --git a/src/mainboard/ocp/sonorapass/board_info.txt b/src/mainboard/ocp/sonorapass/board_info.txt new file mode 100644 index 0000000..bbf3ee9 --- /dev/null +++ b/src/mainboard/ocp/sonorapass/board_info.txt @@ -0,0 +1,5 @@ +Board name: SonoraPass +Category: server +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/ocp/sonorapass/bootblock.c b/src/mainboard/ocp/sonorapass/bootblock.c new file mode 100644 index 0000000..06f45c9 --- /dev/null +++ b/src/mainboard/ocp/sonorapass/bootblock.c @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <bootblock_common.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <device/pnp_ops.h> +#include <intelblocks/lpc_lib.h> +#include <intelblocks/pcr.h> +#include <soc/pci_devs.h> +#include <soc/pcr_ids.h> +#include <superio/aspeed/ast2400/ast2400.h> +#include <superio/aspeed/common/aspeed.h> + +/* these are defined in intelblocks/lpc_lib.h but we can't use them yet */ +#define PCR_DMI_LPCIOD 0x2770 +#define PCR_DMI_LPCIOE 0x2774 +#define ASPEED_CONFIG_INDEX 0x2E +#define ASPEED_CONFIG_DATA 0x2F + +void bootblock_mainboard_early_init(void) +{ + struct config_data port80[] = { + /* {Type, base, reg, and, or} */ + /* Set command source of GPIOH to LPC */ + {MEM, ASPEED_GPIO_BASE, 0x68, 0xFEFFFFFF, 0x01000000}, + {MEM, ASPEED_GPIO_BASE, 0x6C, 0xFEFFFFFF, 0x00000000}, + /* Unlock SCU Registers */ + {MEM, ASPEED_SCU_BASE, 0x00, 0x00000000, 0x1688A8A8}, + /* Program GPIOH multi-function to GPIO */ + {MEM, ASPEED_SCU_BASE, 0x90, 0xFFFFFF3F, 0x00000000}, + /* Program GPIOH as output */ + {MEM, ASPEED_GPIO_BASE, 0x24, 0x00FFFFFF, 0xFF000000}, + /* Set snooping address#0 as 80h */ + {MEM, ASPEED_LPC_BASE, 0x90, 0xFFFF0000, 0x00000080}, + /* Enable snooping address#0 */ + {MEM, ASPEED_LPC_BASE, 0x80, 0xFFFFFFFE, 0x00000001}, + /* Enable GPIO device */ + {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, ASPEED_ENTRY_KEY}, + {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, ASPEED_ENTRY_KEY}, + {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, LDN_SEL}, + {SIO, 0, ASPEED_CONFIG_DATA, 0x00, AST2400_GPIO}, + {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, ACT_REG}, + {SIO, 0, ASPEED_CONFIG_DATA, 0x00, PORT80_GPIO_EN | ACTIVATE_VALUE}, + /* Select GPIOH for port80 GPIO */ + {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, PORT80_GPIO_SEL}, + {SIO, 0, ASPEED_CONFIG_DATA, 0x00, GPIOH_SEL}, + /* Disable GPIO Device */ + {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, LDN_SEL}, + {SIO, 0, ASPEED_CONFIG_DATA, 0x00, AST2400_GPIO}, + {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, ACT_REG}, + {SIO, 0, ASPEED_CONFIG_DATA, 0xFE, DEACTIVATE_VALUE}, + {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, ASPEED_EXIT_KEY} + }; + struct config_data uart[] = { + /* {Type, base, reg, and, or} */ + /* Unlock SCU Registers */ + {MEM, ASPEED_SCU_BASE, 0x00, 0x00000000, 0x1688A8A8}, + /* SERIAL PORT1 */ + {MEM, ASPEED_SCU_BASE, 0x84, 0xFF00FFFF, 0x00C00000}, + {MEM, ASPEED_GPIO_BASE, 0x90, 0xFFFFFFCF, 0x00000000}, + /* SERIAL PORT2 */ + {MEM, ASPEED_SCU_BASE, 0x84, 0x00FFFFFF, 0xC0000000}, + {MEM, ASPEED_GPIO_BASE, 0x90, 0xFFFFFFCF, 0x00000000}, + }; + + /* Enable COM1 only */ + pcr_write32(PID_DMI, 0x2770, 0); + pcr_write32(PID_DMI, 0x2774, 1); + + /* Decode for SuperIO (0x2e) and COM1 (0x3f8) */ + pci_mmio_write_config32(PCH_DEV_LPC, 0x80, (1 << 28) | (1 << 16)); + + const pnp_devfn_t serial_dev = PNP_DEV(0x2e, AST2400_SUART1); + aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); + + /* Port 80h direct to GPIO for LED display */ + aspeed_early_config(ASPEED_CONFIG_INDEX, port80, ARRAY_SIZE(port80)); + + /* Init UART */ + aspeed_early_config(ASPEED_CONFIG_INDEX, uart, ARRAY_SIZE(uart)); +} diff --git a/src/mainboard/ocp/sonorapass/devicetree.cb b/src/mainboard/ocp/sonorapass/devicetree.cb new file mode 100644 index 0000000..fff834a --- /dev/null +++ b/src/mainboard/ocp/sonorapass/devicetree.cb @@ -0,0 +1,53 @@ +chip soc/intel/xeon_sp/cpx + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host bridge + device pci 04.0 on end + device pci 04.1 on end + device pci 04.2 on end + device pci 04.3 on end + device pci 04.4 on end + device pci 04.5 on end + device pci 04.6 on end + device pci 04.7 on end + device pci 05.0 on end + device pci 05.2 on end + device pci 05.4 on end + device pci 08.0 on end + device pci 08.1 on end + device pci 08.2 on end + device pci 11.0 on end + device pci 11.1 on end + device pci 11.5 on end + device pci 14.0 on end + device pci 16.0 on end + device pci 16.1 on end + device pci 16.4 on end + device pci 17.0 on end + device pci 1c.0 on end + device pci 1c.4 on end + device pci 1f.2 on end + device pci 1f.4 on end + device pci 1f.5 on end + + device pci 1f.0 on # LPC/eSPI Interface + chip superio/common + device pnp 2e.0 on + chip superio/aspeed/ast2400 + device pnp 2e.2 on # SUART1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # SUART2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + end + end + end + end + + end +end diff --git a/src/mainboard/ocp/sonorapass/dsdt.asl b/src/mainboard/ocp/sonorapass/dsdt.asl new file mode 100644 index 0000000..3dc45d5 --- /dev/null +++ b/src/mainboard/ocp/sonorapass/dsdt.asl @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <arch/acpi.h> +#include <soc/iomap.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include "acpi/platform.asl" + + Name(_S0, Package() { 0x00, 0x00, 0x00, 0x00 }) + Name(_S5, Package() { 0x07, 0x00, 0x00, 0x00 }) + + Scope (\_SB) + { + Device (PCI0) + { + #include <soc/intel/xeon_sp/cpx/acpi/southcluster.asl> + #include <soc/intel/common/block/acpi/acpi/lpc.asl> + + } + + + Device (UNC0) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_UID, 0x3F) + Method (_BBN, 0, NotSerialized) + { + Return (0xff) + } + + Method (_STA, 0, NotSerialized) + { + Return (0xf) + } + + Name (_CRS, ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x00FF, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0001, // Length + ,, ) + }) + + } + } + +} -- To view, visit https://review.coreboot.org/c/coreboot/+/40334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60452205d666fd19582780401ccd9d7773e68a5b Gerrit-Change-Number: 40334 Gerrit-PatchSet: 1 Gerrit-Owner: Ryback Hung <ryback.hung%quantatw.com(a)gtempaccount.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: Read spds only once if measured boot is enabled
by Bill XIE (Code Review) 10 Jun '23

10 Jun '23

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39969 ) Change subject: nb/intel/sandybridge: Read spds only once if measured boot is enabled ...................................................................... nb/intel/sandybridge: Read spds only once if measured boot is enabled Without considering s3 resume, spd may be used various times depending on various condition. If spd is stored in CBFS and read various times, PCR value may become inconsistent. As mentioned in CB:39906, in order to avoid this, we could read spd exactly once, and use the data read out various times, when measured boot is enabled. Change-Id: I02cad7e85d5e66fd9efb674e4dc9868233f6c233 Signed-off-by: Bill XIE <persmule(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit.c 1 file changed, 27 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/39969/1 diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index b096a11..f3c81a6 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -98,6 +98,17 @@ } } +static bool spd_is_available(const spd_raw_data spds[], size_t num_spd) +{ + /* An available spd should at least have an non-zero id */ + size_t i, j, sum = 0; + for (i = 0; i < num_spd; i++) { + for (j = 117; j < 128; j++) + sum += spds[i][j]; + } + return (sum > 0); +} + static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) { int dimms = 0, ch_dimms; @@ -222,6 +233,8 @@ struct region_device rdev; ramctr_timing *ctrl_cached = NULL; + if (CONFIG(TPM_MEASURED_BOOT)) + memset(spds, 0, sizeof(spds)); MCHBAR32(SAPMCTL) |= 1; /* Wait for ME to be ready */ @@ -271,8 +284,14 @@ /* Verify MRC cache for fast boot */ if (!s3resume && ctrl_cached) { /* Load SPD unique information data. */ - memset(spds, 0, sizeof(spds)); - mainboard_get_spd(spds, 1); + if (CONFIG(TPM_MEASURED_BOOT)) { + /* if CONFIG(TPM_MEASURED_BOOT), + we manage to get spds only ONCE */ + mainboard_get_spd(spds, 0); + } else { + memset(spds, 0, sizeof(spds)); + mainboard_get_spd(spds, 1); + } /* check SPD CRC16 to make sure the DIMMs haven't been replaced */ fast_boot = verify_crc16_spds_ddr3(spds, ctrl_cached); @@ -307,8 +326,12 @@ ctrl.cpu = cpuid; /* Get DDR3 SPD data */ - memset(spds, 0, sizeof(spds)); - mainboard_get_spd(spds, 0); + if (!CONFIG(TPM_MEASURED_BOOT) || !spd_is_available(spds, 4)) { + /* without CONFIG(TPM_MEASURED_BOOT), the previous read may + only contains id, so read it again */ + memset(spds, 0, sizeof(spds)); + mainboard_get_spd(spds, 0); + } dram_find_spds_ddr3(spds, &ctrl); err = try_init_dram_ddr3(&ctrl, fast_boot, s3resume, me_uma_size); -- To view, visit https://review.coreboot.org/c/coreboot/+/39969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02cad7e85d5e66fd9efb674e4dc9868233f6c233 Gerrit-Change-Number: 39969 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-MessageType: newchange

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