coreboot-gerrit April 2020

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Change in coreboot[master]: commonlib/elog: Add missing PCI Express PME sources
by Michał Żygowski (Code Review) 10 Jun '23

10 Jun '23

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40417 ) Change subject: commonlib/elog: Add missing PCI Express PME sources ...................................................................... commonlib/elog: Add missing PCI Express PME sources Intel Skylake SoC defines more than 12 PCI Express wake sources. However, these wake sources are not defined anywhere. Without these definitions the coreboot build for Skylake or Kaby Lake board fails when event log is enabled. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ie60a232104d8947d86de5add150f12ba7c03b0cc --- M src/commonlib/include/commonlib/elog.h 1 file changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/40417/1 diff --git a/src/commonlib/include/commonlib/elog.h b/src/commonlib/include/commonlib/elog.h index 3b84242..c9b0c3e 100644 --- a/src/commonlib/include/commonlib/elog.h +++ b/src/commonlib/include/commonlib/elog.h @@ -166,6 +166,18 @@ #define ELOG_WAKE_SOURCE_PME_XHCI_USB_2 0x1d #define ELOG_WAKE_SOURCE_PME_XHCI_USB_3 0x1e #define ELOG_WAKE_SOURCE_PME_WIFI 0x1f +#define ELOG_WAKE_SOURCE_PME_PCIE13 0x20 +#define ELOG_WAKE_SOURCE_PME_PCIE14 0x21 +#define ELOG_WAKE_SOURCE_PME_PCIE15 0x22 +#define ELOG_WAKE_SOURCE_PME_PCIE16 0x23 +#define ELOG_WAKE_SOURCE_PME_PCIE17 0x24 +#define ELOG_WAKE_SOURCE_PME_PCIE18 0x25 +#define ELOG_WAKE_SOURCE_PME_PCIE19 0x26 +#define ELOG_WAKE_SOURCE_PME_PCIE20 0x27 +#define ELOG_WAKE_SOURCE_PME_PCIE21 0x28 +#define ELOG_WAKE_SOURCE_PME_PCIE22 0x29 +#define ELOG_WAKE_SOURCE_PME_PCIE23 0x2a +#define ELOG_WAKE_SOURCE_PME_PCIE24 0x2b struct elog_event_data_wake { uint8_t source; @@ -383,6 +395,18 @@ { ELOG_WAKE_SOURCE_PME_PCIE10, "PCI Express 10 PME" }, { ELOG_WAKE_SOURCE_PME_PCIE11, "PCI Express 11 PME" }, { ELOG_WAKE_SOURCE_PME_PCIE12, "PCI Express 12 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE13, "PCI Express 13 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE14, "PCI Express 14 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE15, "PCI Express 15 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE16, "PCI Express 16 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE17, "PCI Express 17 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE18, "PCI Express 18 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE19, "PCI Express 19 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE20, "PCI Express 20 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE21, "PCI Express 21 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE22, "PCI Express 22 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE23, "PCI Express 23 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE24, "PCI Express 24 PME" }, { ELOG_WAKE_SOURCE_PME_SATA, "SATA PME" }, { ELOG_WAKE_SOURCE_PME_CSE, "CSE PME" }, { ELOG_WAKE_SOURCE_PME_CSE2, "CSE 2 PME" }, -- To view, visit https://review.coreboot.org/c/coreboot/+/40417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie60a232104d8947d86de5add150f12ba7c03b0cc Gerrit-Change-Number: 40417 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/cbmem: implement event log parser
by Michał Żygowski (Code Review) 10 Jun '23

10 Jun '23

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40344 ) Change subject: util/cbmem: implement event log parser ...................................................................... util/cbmem: implement event log parser Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ia24bc23e99f12ca4bd57505f83351a2907f81a33 --- M util/cbmem/cbmem.c 1 file changed, 213 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/40344/1 diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index f8da7da..d318acb 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -32,6 +32,7 @@ #include <assert.h> #include <regex.h> #include <commonlib/cbmem_id.h> +#include <commonlib/elog.h> #include <commonlib/timestamp_serialized.h> #include <commonlib/tcpa_log_serialized.h> #include <commonlib/coreboot_tables.h> @@ -1080,6 +1081,207 @@ unmap_memory(&coverage_mapping); } + +static int bcd_to_decimal(uint8_t x) +{ + return x - 6 * (x >> 4); +} + +static char *get_name_from_table(const struct elog_event_name *event_table, u8 event) +{ + size_t table_size; + + if (event_table == elog_event_to_name) + table_size = ARRAY_SIZE(elog_event_to_name); + else if (event_table == elog_ec_event_to_name) + table_size = ARRAY_SIZE(elog_ec_event_to_name); + else if (event_table == elog_wake_event_to_name) + table_size = ARRAY_SIZE(elog_wake_event_to_name); + else if (event_table == elog_ec_device_event_to_name) + table_size = ARRAY_SIZE(elog_ec_device_event_to_name); + else if (event_table == mrc_upd_slots) + table_size = ARRAY_SIZE(mrc_upd_slots); + else + return "Unknown"; + + for (size_t i = 0; i < table_size; i++) { + if (event_table[i].event_type == event) + return event_table[i].event_name; + } + return "Unknown event type"; +} + +static void print_raw(uint8_t *start, size_t end) +{ + size_t i, j; + for (i = 0; i < end; i += 16) { + for (j = 0; j < 16; j++) { + if (i + j >= end) + break; + printf("%02x ", start[i+j]); + } + printf("\n"); + } +} + +static void print_elog_date(struct event_header *ev_header) +{ + printf("[20%02d-%02d-%02d %02d:%02d:%02d] ", + bcd_to_decimal(ev_header->year), + bcd_to_decimal(ev_header->month), + bcd_to_decimal(ev_header->day), + bcd_to_decimal(ev_header->hour), + bcd_to_decimal(ev_header->minute), + bcd_to_decimal(ev_header->second)); +} + +struct cbmem_elog { + u32 magic; + u8 version; + u8 header_size; + u8 reserved[2]; +} __attribute__ ((__packed__)); + +static void dump_elog(void) +{ + uint64_t start; + size_t size, offset; + const void *elog; + uint8_t *elog_data; + size_t elog_size; + struct mapping elog_mapping; + struct cbmem_elog *cb_elog; + struct event_header *ev_header; + struct elog_event_data_wake *wake_ev; + struct elog_event_data_me_extended *me_ext_ev; + struct elog_event_mem_cache_update *mrc_event; + struct elog_event_extended_event *elog_ext; + + if (find_cbmem_entry(CBMEM_ID_ELOG, &start, &size)) { + fprintf(stderr, "ELOG area not found\n"); + return; + } + + elog = map_memory(&elog_mapping, start, size); + if (!elog) + die("Unable to map elog area.\n"); + + cb_elog = (struct cbmem_elog *)elog; + + printf("Dumping ELOG data...\n"); + printf("ELOG version %d\n", cb_elog->version); + + offset = cb_elog->header_size; + + while (*(uint8_t *)(elog + offset) != ELOG_TYPE_EOL) { + ev_header = (struct event_header *)(elog + offset); + print_elog_date(ev_header); + printf("%s", get_name_from_table(elog_event_to_name, ev_header->type)); + + elog_data = (uint8_t *) (elog + offset + sizeof(struct event_header)); + elog_size = ev_header->length - sizeof(struct event_header) - 1; + + if (ev_header->type < 0x80) { + offset += ev_header->length; + if (elog_size != 0) { + printf(". Data: "); + print_raw(elog_data, elog_size); + } else { + printf("\n"); + } + continue; + } + + switch (ev_header->type) { + case ELOG_TYPE_EC_EVENT: + printf(": %s\n", + get_name_from_table(elog_ec_event_to_name, *elog_data)); + break; + case ELOG_TYPE_ACPI_ENTER: + case ELOG_TYPE_ACPI_WAKE: + printf(": S%d\n", bcd_to_decimal(*elog_data)); + break; + case ELOG_TYPE_WAKE_SOURCE: + wake_ev = (struct elog_event_data_wake *) + (elog + offset + sizeof(struct event_header)); + printf(": %s instance %d\n", + get_name_from_table(elog_wake_event_to_name, wake_ev->source), + wake_ev->instance); + break; + case ELOG_TYPE_MEM_CACHE_UPDATE: + mrc_event = (struct elog_event_mem_cache_update *) + (elog + offset + sizeof(struct event_header)); + printf(": slot %s, status %s\n", + get_name_from_table(mrc_upd_slots, mrc_event->slot), + mrc_event->status ? "FAIL" : "SUCCESS"); + break; + case ELOG_TYPE_EC_DEVICE_EVENT: + printf(": %s\n", get_name_from_table(elog_ec_device_event_to_name, + *elog_data)); + break; + case ELOG_TYPE_EXTENDED_EVENT: + elog_ext = (struct elog_event_extended_event *) + (elog + offset + sizeof(struct event_header)); + if (elog_ext->event_type == ELOG_SLEEP_PENDING_PM1_WAKE) + printf(": Pending PM1 wake (%08d)\n", + elog_ext->event_complement); + else if (elog_ext->event_type == ELOG_SLEEP_PENDING_GPE0_WAKE) + printf(": Pending GPE0 wake (%08d)\n", + elog_ext->event_complement); + else + printf(": Unknown (%08d)\n", elog_ext->event_complement); + break; + case ELOG_TYPE_CROS_RECOVERY_MODE: + printf(": reason %02x\n", *elog_data); + break; + case ELOG_TYPE_INTRUDER_DETECTION: + if (*elog_data == ELOG_CASE_OPENED) + printf(": Case opened\n"); + else if (*elog_data == ELOG_CASE_CLOSED) + printf(": Case closed\n"); + else + printf(": Unknown (%02x)\n", *elog_data); + break; + case ELOG_TYPE_MANAGEMENT_ENGINE: + if (*elog_data < 6) + printf(": %s\n", me_bios_paths[*elog_data]); + else + printf("Unknown\n"); + break; + case ELOG_TYPE_MANAGEMENT_ENGINE_EXT: + me_ext_ev = (struct elog_event_data_me_extended *) + (elog + offset + sizeof(struct event_header)); + printf(":\n" + "\t\t\tCurrent working state: %02x\n" + "\t\t\tOperation state: %02x\n" + "\t\t\tOperation mode: %02x\n" + "\t\t\tError code: %02x\n" + "\t\t\tProgress code: %02x\n" + "\t\t\tCurrent PM event: %02x\n" + "\t\t\tCurrent state: %02x\n", + me_ext_ev->current_working_state, + me_ext_ev->operation_state, + me_ext_ev->operation_mode, + me_ext_ev->error_code, + me_ext_ev->progress_code, + me_ext_ev->current_pmevent, + me_ext_ev->current_state); + break; + default: + if (elog_size != 0) { + printf(": Unknown. Data: "); + print_raw(elog_data, elog_size); + } else + printf("\n"); + break; + } /* switch */ + + offset += ev_header->length; + } /* while */ + + unmap_memory(&elog_mapping); +} + static void print_version(void) { printf("cbmem v%s -- ", CBMEM_VERSION); @@ -1101,6 +1303,7 @@ " -c | --console: print cbmem console\n" " -1 | --oneboot: print cbmem console for last boot only\n" " -C | --coverage: dump coverage information\n" + " -e | --elog: dump event log\n" " -l | --list: print cbmem table of contents\n" " -x | --hexdump: print hexdump of cbmem area\n" " -r | --rawdump ID: print rawdump of specific ID (in hex) of cbtable\n" @@ -1234,6 +1437,7 @@ int print_defaults = 1; int print_console = 0; int print_coverage = 0; + int print_elog = 0; int print_list = 0; int print_hexdump = 0; int print_rawdump = 0; @@ -1248,6 +1452,7 @@ {"console", 0, 0, 'c'}, {"oneboot", 0, 0, '1'}, {"coverage", 0, 0, 'C'}, + {"elog", 0, 0, 'e'}, {"list", 0, 0, 'l'}, {"tcpa-log", 0, 0, 'L'}, {"timestamps", 0, 0, 't'}, @@ -1259,13 +1464,17 @@ {"help", 0, 0, 'h'}, {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "c1CltTLxVvh?r:", + while ((opt = getopt_long(argc, argv, "c1CeltTLxVvh?r:", long_options, &option_index)) != EOF) { switch (opt) { case 'c': print_console = 1; print_defaults = 0; break; + case 'e': + print_elog = 1; + print_defaults = 0; + break; case '1': print_console = 1; one_boot_only = 1; @@ -1401,6 +1610,9 @@ if (print_coverage) dump_coverage(); + if (print_elog) + dump_elog(); + if (print_list) dump_cbmem_toc(); -- To view, visit https://review.coreboot.org/c/coreboot/+/40344 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia24bc23e99f12ca4bd57505f83351a2907f81a33 Gerrit-Change-Number: 40344 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: ec/google/chromeec: Add support for USB Type-C alternate mode control
by John Zhao (Code Review) 10 Jun '23

10 Jun '23

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40424 ) Change subject: ec/google/chromeec: Add support for USB Type-C alternate mode control ...................................................................... ec/google/chromeec: Add support for USB Type-C alternate mode control PMC mux control can be used for swapping the USB data role and for setting connector to act in alternate modes. BUG=b:151646486 BRANCH=None TEST=Verify USB Type-C alternate mode (DP or TBT) along with PMC mux control. Change-Id: I8c872537d9c633f8eb4238fd9b023577c4570a5a Signed-off-by: John Zhao <john.zhao(a)intel.com> --- M src/ec/google/chromeec/acpi/cros_ec.asl 1 file changed, 113 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/40424/1 diff --git a/src/ec/google/chromeec/acpi/cros_ec.asl b/src/ec/google/chromeec/acpi/cros_ec.asl index 3e9b773..a8d859f 100644 --- a/src/ec/google/chromeec/acpi/cros_ec.asl +++ b/src/ec/google/chromeec/acpi/cros_ec.asl @@ -56,4 +56,117 @@ { Return (0xB) } + + Device (USBC) + { + Name (_HID, "GOOG0014") + Name (_DDN, "ChromeOS Embedded Controller USB Type-C Control") + + /* + * Each connector shall have its own ACPI device entry + * (node), under the actual interface device. + */ + Device (CON0) + { + Name (_ADR, 0) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package() { + Package () { "usb-role-switch", + \_SB.PCI0.PMC.MUX.CON0 }, + Package () { "mode-switch", + \_SB.PCI0.PMC.MUX.CON0 }, + Package () { "orientation-switch", + \_SB.PCI0.PMC.MUX.CON0 }, + Package () { "power-role", "dual" }, + Package () { "data-role", "dual" }, + } + }) + + /* + * Each supported alternate mode. Use _STA() to disable/enable + * them. + */ + + /* Thunderbolt 3 alternate mode */ + Device (TBT3) + { + Name (_ADR, 0) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package() { + Package () { "svid", 0x8087 }, + Package () { "vdo", 1 }, + } + }) + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + } + + /* Display Port alternate mode */ + Device (DP) + { + Name (_ADR, 1) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package() { + Package () { "svid", 0xff01 }, + Package () { "vdo", 0x1c46 }, + } + }) + } + } + + Device (CON1) + { + Name (_ADR, 1) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package() { + Package () { "usb-role-switch", + \_SB.PCI0.PMC.MUX.CON1 }, + Package () { "mode-switch", + \_SB.PCI0.PMC.MUX.CON1 }, + Package () { "orientation-switch", + \_SB.PCI0.PMC.MUX.CON1 }, + Package () { "power-role", "dual" }, + Package () { "data-role", "dual" }, + }, + }) + + Device (TBT3) + { + Name (_ADR, 0) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package() { + Package () {"svid", 0x8087}, + Package () {"vdo", 1}, + } + }) + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + } + + Device (DP) + { + Name (_ADR, 1) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package() { + Package () { "svid", 0xff01 }, + Package () { "vdo", 0x1c46 }, + } + }) + } + } + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/40424 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c872537d9c633f8eb4238fd9b023577c4570a5a Gerrit-Change-Number: 40424 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/common/smihandler.c: add mainboard intrusion detection handler
by Michał Żygowski (Code Review) 10 Jun '23

10 Jun '23

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40348 ) Change subject: sb/intel/common/smihandler.c: add mainboard intrusion detection handler ...................................................................... sb/intel/common/smihandler.c: add mainboard intrusion detection handler Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I87c30c9b8fbf7dbc0327155863cfe62c51bcbc1b --- M src/southbridge/intel/common/smihandler.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/40348/1 diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 7d4066d..b8ea9a2 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -424,6 +424,9 @@ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ /* Handle TCO timeout */ printk(BIOS_DEBUG, "TCO Timeout.\n"); + } else if (tco_sts & (1 << 16)) { /* INTRUDER */ + mainboard_smi_intruder(tco_sts); + printk(BIOS_DEBUG, "TCO Intruder.\n"); } else { dump_tco_status(tco_sts); } -- To view, visit https://review.coreboot.org/c/coreboot/+/40348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87c30c9b8fbf7dbc0327155863cfe62c51bcbc1b Gerrit-Change-Number: 40348 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/hatch: Toggle on EC_ENABLE_LID_SWITCH
by Edward O'Callaghan (Code Review) 10 Jun '23

10 Jun '23

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40517 ) Change subject: mb/google/hatch: Toggle on EC_ENABLE_LID_SWITCH ...................................................................... mb/google/hatch: Toggle on EC_ENABLE_LID_SWITCH Unfortunately EC_ENABLE_LID_SWITCH needs to be toggled on to enable the 'PNP0C0D' ASL device on otherwise the wake pin will not be noticed by the kernel. This patch works around that issue for Puff and Puff variants. BUG=b:152913653 BRANCH=none TEST=builds Change-Id: I2f40afb7aa62510312164d3a62d44f4b2b911700 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/mainboard/google/hatch/variants/duffy/include/variant/ec.h M src/mainboard/google/hatch/variants/kaisa/include/variant/ec.h M src/mainboard/google/hatch/variants/puff/include/variant/ec.h 3 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/40517/1 diff --git a/src/mainboard/google/hatch/variants/duffy/include/variant/ec.h b/src/mainboard/google/hatch/variants/duffy/include/variant/ec.h index 5e2043f..9f9b4a9 100644 --- a/src/mainboard/google/hatch/variants/duffy/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/duffy/include/variant/ec.h @@ -49,6 +49,8 @@ * Note that GPE_EC_WAKE is defined, confusingly, as GPE_LAN_WAK which is GPD2/LAN_WAKE# * on the PCH or as the line EC_PCH_WAKE_ODL on the schematic. */ +/* Enable LID switch such that the wake pin works for the EC */ +#define EC_ENABLE_LID_SWITCH #define EC_ENABLE_WAKE_PIN GPE_EC_WAKE #define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ diff --git a/src/mainboard/google/hatch/variants/kaisa/include/variant/ec.h b/src/mainboard/google/hatch/variants/kaisa/include/variant/ec.h index 5e2043f..9f9b4a9 100644 --- a/src/mainboard/google/hatch/variants/kaisa/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/kaisa/include/variant/ec.h @@ -49,6 +49,8 @@ * Note that GPE_EC_WAKE is defined, confusingly, as GPE_LAN_WAK which is GPD2/LAN_WAKE# * on the PCH or as the line EC_PCH_WAKE_ODL on the schematic. */ +/* Enable LID switch such that the wake pin works for the EC */ +#define EC_ENABLE_LID_SWITCH #define EC_ENABLE_WAKE_PIN GPE_EC_WAKE #define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ diff --git a/src/mainboard/google/hatch/variants/puff/include/variant/ec.h b/src/mainboard/google/hatch/variants/puff/include/variant/ec.h index 5e2043f..9f9b4a9 100644 --- a/src/mainboard/google/hatch/variants/puff/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/puff/include/variant/ec.h @@ -49,6 +49,8 @@ * Note that GPE_EC_WAKE is defined, confusingly, as GPE_LAN_WAK which is GPD2/LAN_WAKE# * on the PCH or as the line EC_PCH_WAKE_ODL on the schematic. */ +/* Enable LID switch such that the wake pin works for the EC */ +#define EC_ENABLE_LID_SWITCH #define EC_ENABLE_WAKE_PIN GPE_EC_WAKE #define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ -- To view, visit https://review.coreboot.org/c/coreboot/+/40517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f40afb7aa62510312164d3a62d44f4b2b911700 Gerrit-Change-Number: 40517 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/inteltool: print all Lewisburg GPIO registers
by Maxim Polyakov (Code Review) 10 Jun '23

10 Jun '23

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40014 ) Change subject: util/inteltool: print all Lewisburg GPIO registers ...................................................................... util/inteltool: print all Lewisburg GPIO registers These changes are in accordance with the documentation: [*] "Intel C620 Series Chipset Platform Controller Hub", datasheet. May 2019. Document Number: 336067-007US Change-Id: Ib7e4e3884f7b087c08325597650b2f2fd5a6a62f Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M util/inteltool/gpio_names/lewisburg.h 1 file changed, 220 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/40014/1 diff --git a/util/inteltool/gpio_names/lewisburg.h b/util/inteltool/gpio_names/lewisburg.h index 4d59177..d2aba7a 100644 --- a/util/inteltool/gpio_names/lewisburg.h +++ b/util/inteltool/gpio_names/lewisburg.h @@ -4,10 +4,190 @@ #include "gpio_groups.h" #include "sunrise.h" +static const struct gpiocom_register lewisburg_community0_abf_cfg_registers[] = { + {0x0C, "PADBAR"}, + {0x10, "MISCCFG"}, + {0x20, "PAD_OWN_GPP_A_0"}, + {0x24, "PAD_OWN_GPP_A_1"}, + {0x28, "PAD_OWN_GPP_A_2"}, + {0x2C, "PAD_OWN_GPP_B_0"}, + {0x30, "PAD_OWN_GPP_B_1"}, + {0x34, "PAD_OWN_GPP_B_2"}, + {0x38, "PAD_OWN_GPP_F_0"}, + {0x3C, "PAD_OWN_GPP_F_1"}, + {0x40, "PAD_OWN_GPP_F_2"}, + {0x60, "PADCFGLOCK_GPP_A"}, + {0x64, "PADCFGLOCKTX_GPP_A"}, + {0x68, "PADCFGLOCK_GPP_B"}, + {0x6C, "PADCFGLOCKTX_GPP_B"}, + {0x70, "PADCFGLOCK_GPP_F"}, + {0x74, "PADCFGLOCKTX_GPP_F"}, + {0x80, "HOSTSW_OWN_GPP_A"}, + {0x84, "HOSTSW_OWN_GPP_B"}, + {0x88, "HOSTSW_OWN_GPP_F"}, + {0x100, "GPI_IS_GPP_A"}, + {0x104, "GPI_IS_GPP_B"}, + {0x108, "GPI_IS_GPP_F"}, + {0x110, "GPI_IE_GPP_A"}, + {0x114, "GPI_IE_GPP_B"}, + {0x118, "GPI_IE_GPP_F"}, + {0x120, "GPI_GPE_STS_GPP_A"}, + {0x124, "GPI_GPE_STS_GPP_B"}, + {0x128, "GPI_GPE_STS_GPP_F"}, + {0x130, "GPI_GPE_EN_GPP_A"}, + {0x134, "GPI_GPE_EN_GPP_B"}, + {0x138, "GPI_GPE_EN_GPP_F"}, + {0x144, "GPI_SMI_STS_GPP_B"}, + {0x154, "GPI_SMI_EN_GPP_B"}, + {0x164, "GPI_NMI_STS_GPP_B"}, + {0x174, "GPI_NMI_EN_GPP_B"}, +}; + +static const struct gpiocom_register lewisburg_community1_cde_cfg_registers[] = { + {0x10, "PADBAR"}, + {0x13, "MISCCFG"}, + {0x23, "PAD_OWN_GPP_C_0"}, + {0x24, "PAD_OWN_GPP_C_1"}, + {0x28, "PAD_OWN_GPP_C_2"}, + {0x2C, "PAD_OWN_GPP_D_0"}, + {0x30, "PAD_OWN_GPP_D_1"}, + {0x34, "PAD_OWN_GPP_D_2"}, + {0x38, "PAD_OWN_GPP_E_0"}, + {0x3C, "PAD_OWN_GPP_E_1"}, + {0x60, "PADCFGLOCK_GPP_C_0"}, + {0x64, "PADCFGLOCKTX_GPP_C_0"}, + {0x68, "PADCFGLOCK_GPP_D_0"}, + {0x6C, "PADCFGLOCKTX_GPP_D_0"}, + {0x70, "PADCFGLOCK_GPP_E_0"}, + {0x74, "PADCFGLOCKTX_GPP_E_0"}, + {0x80, "HOSTSW_OWN_GPP_C_0"}, + {0x84, "HOSTSW_OWN_GPP_D_0"}, + {0x88, "HOSTSW_OWN_GPP_E_0"}, + {0x100, "GPI_IS_GPP_C_0"}, + {0x104, "GPI_IS_GPP_D_0"}, + {0x108, "GPI_IS_GPP_E_0"}, + {0x110, "GPI_IE_GPP_C_0"}, + {0x114, "GPI_IE_GPP_D_0"}, + {0x118, "GPI_IE_GPP_E_0"}, + {0x120, "GPI_GPE_STS_GPP_C_0"}, + {0x124, "GPI_GPE_STS_GPP_D_0"}, + {0x128, "GPI_GPE_STS_GPP_E_0"}, + {0x130, "GPI_GPE_EN_GPP_C_0"}, + {0x134, "GPI_GPE_EN_GPP_D_0"}, + {0x138, "GPI_GPE_EN_GPP_E_0"}, + {0x140, "GPI_SMI_STS_GPP_C_0"}, + {0x144, "GPI_SMI_STS_GPP_D_0"}, + {0x148, "GPI_SMI_STS_GPP_E_0"}, + {0x150, "GPI_SMI_EN_GPP_C_0"}, + {0x154, "GPI_SMI_EN_GPP_D_0"}, + {0x158, "GPI_SMI_EN_GPP_E_0"}, + {0x160, "GPI_NMI_STS_GPP_C_0"}, + {0x164, "GPI_NMI_STS_GPP_D_0"}, + {0x168, "GPI_NMI_STS_GPP_E_0"}, + {0x170, "GPI_NMI_EN_GPP_C_0"}, + {0x174, "GPI_NMI_EN_GPP_D_0"}, + {0x178, "GPI_NMI_EN_GPP_E_0"}, + {0x204, "PWMC"}, + {0x20C, "GP_SER_BLINK"}, + {0x210, "GP_SER_CMDSTS"}, + {0x214, "GP_SER_DATA"}, +}; + +static const struct gpiocom_register lewisburg_community2_gpd_cfg_registers[] = { + {0x0C, "PADBAR"}, + {0x10, "MISCCFG"}, + {0x20, "PAD_OWN_GPD_0"}, + {0x24, "PAD_OWN_GPD_1"}, + {0x60, "PADCFGLOCK_GPD_0"}, + {0x64, "PADCFGLOCKTX_GPD_0"}, + {0x80, "HOSTSW_OWN_GPD_0"}, + {0x100, "GPI_IS_GPD_0"}, + {0x110, "GPI_IE_GPD_0"}, + {0x120, "GPI_GPE_STS_GPD_0"}, + {0x130, "GPI_GPE_EN_GPD_0"}, +}; + +static const struct gpiocom_register lewisburg_community3_i_cfg_registers[] = { + {0xC0, "PADBAR"}, + {0x10, "MISCCFG"}, + {0x20, "PAD_OWN_GPP_I_0"}, + {0x24, "PAD_OWN_GPP_I_1"}, + {0x60, "PADCFGLOCK_GPP_I_0"}, + {0x64, "PADCFGLOCKTX_GPP_I_0"}, + {0x80, "HOSTSW_OWN_GPP_I_0"}, + {0x100, "GPI_IS_GPP_I_0"}, + {0x110, "GPI_IE_GPP_I_0"}, + {0x120, "GPI_GPE_STS_GPP_I_0"}, + {0x130, "GPI_GPE_EN_GPP_I_0"}, + {0x140, "GPI_SMI_STS_GPP_I_0"}, + {0x150, "GPI_SMI_EN_GPP_I_0"}, + {0x160, "GPI_NMI_STS_GPP_I_0"}, + {0x170, "GPI_NMI_EN_GPP_I_0"}, +}; + +static const struct gpiocom_register lewisburg_community4_jk_cfg_registers[] = { + {0x0C, "PADBAR"}, + {0x10, "MISCCFG"}, + {0x20, "PAD_OWN_GPP_J_0"}, + {0x24, "PAD_OWN_GPP_J_1"}, + {0x28, "PAD_OWN_GPP_J_2"}, + {0x2C, "PAD_OWN_GPP_K_0"}, + {0x30, "PAD_OWN_GPP_K_1"}, + {0x60, "PADCFGLOCK_GPP_J"}, + {0x64, "PADCFGLOCKTX_GPP_J"}, + {0x68, "PADCFGLOCK_GPP_K"}, + {0x6C, "PADCFGLOCKTX_GPP_K"}, + {0x80, "HOSTSW_OWN_GPP_J"}, + {0x84, "HOSTSW_OWN_GPP_K"}, + {0x100, "GPI_IS_GPP_J"}, + {0x104, "GPI_IS_GPP_K"}, + {0x110, "GPI_IE_GPP_J"}, + {0x114, "GPI_IE_GPP_K"}, + {0x120, "GPI_GPE_STS_GPP_J"}, + {0x124, "GPI_GPE_STS_GPP_K"}, + {0x130, "GPI_GPE_EN_GPP_J"}, + {0x134, "GPI_GPE_EN_GPP_K"}, +}; + +static const struct gpiocom_register lewisburg_community5_jk_cfg_registers[] = { + {0x0C, "PADBAR"}, + {0x10, "MISCCFG"}, + {0x20, "PAD_OWN_GPP_G_0"}, + {0x24, "PAD_OWN_GPP_G_1"}, + {0x28, "PAD_OWN_GPP_G_2"}, + {0x2C, "PAD_OWN_GPP_H_0"}, + {0x30, "PAD_OWN_GPP_H_1"}, + {0x34, "PAD_OWN_GPP_H_2"}, + {0x38, "PAD_OWN_GPP_L_0"}, + {0x3C, "PAD_OWN_GPP_L_1"}, + {0x40, "PAD_OWN_GPP_L_2"}, + {0x60, "PADCFGLOCK_GPP_G"}, + {0x64, "PADCFGLOCKTX_GPP_G"}, + {0x68, "PADCFGLOCK_GPP_H"}, + {0x6C, "PADCFGLOCKTX_GPP_H"}, + {0x70, "PADCFGLOCK_GPP_L"}, + {0x74, "PADCFGLOCKTX_GPP_L"}, + {0x80, "HOSTSW_OWN_GPP_G"}, + {0x84, "HOSTSW_OWN_GPP_H"}, + {0x88, "HOSTSW_OWN_GPP_L"}, + {0x100, "GPI_IS_GPP_G"}, + {0x104, "GPI_IS_GPP_H"}, + {0x108, "GPI_IS_GPP_L"}, + {0x110, "GPI_IE_GPP_G"}, + {0x114, "GPI_IE_GPP_H"}, + {0x118, "GPI_IE_GPP_L"}, + {0x120, "GPI_GPE_STS_GPP_G"}, + {0x124, "GPI_GPE_STS_GPP_H"}, + {0x128, "GPI_GPE_STS_GPP_L"}, + {0x130, "GPI_GPE_EN_GPP_G"}, + {0x134, "GPI_GPE_EN_GPP_H"}, + {0x138, "GPI_GPE_EN_GPP_L"}, +}; + static const char *const lewisburg_group_a_names[] = { - "GPP_A0", "RCIN#", "n/a", "ESPI_ALERT1#", - "GPP_A1", "LAD0", "n/a", "ESPI_IO0", - "GPP_A2", "LAD1", "n/a", "ESPI_IO1", + "GPP_,A0", "RCIN#", "n/a", "ESPI_ALERT1#", + "GPP_,A1", "LAD0", "n/a", "ESPI_IO0", + "GPP_,A2", "LAD1", "n/a", "ESPI_IO1", "GPP_A3", "LAD2", "n/a", "ESPI_IO2", "GPP_A4", "LAD3", "n/a", "ESPI_IO3", "GPP_A5", "LFRAME#", "n/a", "ESPI_CS0#", @@ -384,10 +564,12 @@ }; static const struct gpio_community lewisburg_community0_abf = { - .name = "------- GPIO Community 0 -------", - .pcr_port_id = 0xaf, - .group_count = ARRAY_SIZE(lewisburg_community0_abf_groups), - .groups = lewisburg_community0_abf_groups, + .name = "------- GPIO Community 0 -------", + .pcr_port_id = 0xaf, + .groups = lewisburg_community0_abf_groups, + .group_count = ARRAY_SIZE(lewisburg_community0_abf_groups), + .cfg_registers = lewisburg_community0_abf_cfg_registers, + .cfg_registers_count = ARRAY_SIZE(lewisburg_community0_abf_cfg_registers), }; static const struct gpio_group *const lewisburg_community1_cde_groups[] = { @@ -397,10 +579,12 @@ }; static const struct gpio_community lewisburg_community1_cde = { - .name = "------- GPIO Community 1 -------", - .pcr_port_id = 0xae, - .group_count = ARRAY_SIZE(lewisburg_community1_cde_groups), - .groups = lewisburg_community1_cde_groups, + .name = "------- GPIO Community 1 -------", + .pcr_port_id = 0xae, + .groups = lewisburg_community1_cde_groups, + .group_count = ARRAY_SIZE(lewisburg_community1_cde_groups), + .cfg_registers = lewisburg_community1_cde_cfg_registers, + .cfg_registers_count = ARRAY_SIZE(lewisburg_community1_cde_cfg_registers), }; static const struct gpio_group *const lewisburg_community2_gpd_groups[] = { @@ -408,10 +592,12 @@ }; static const struct gpio_community lewisburg_community2_gpd = { - .name = "------- GPIO Community 2 -------", - .pcr_port_id = 0xad, - .group_count = ARRAY_SIZE(lewisburg_community2_gpd_groups), - .groups = lewisburg_community2_gpd_groups, + .name = "------- GPIO Community 2 -------", + .pcr_port_id = 0xad, + .groups = lewisburg_community2_gpd_groups, + .group_count = ARRAY_SIZE(lewisburg_community2_gpd_groups), + .cfg_registers = lewisburg_community2_gpd_cfg_registers, + .cfg_registers_count = ARRAY_SIZE(lewisburg_community2_gpd_cfg_registers), }; static const struct gpio_group *const lewisburg_community3_i_groups[] = { @@ -419,10 +605,12 @@ }; static const struct gpio_community lewisburg_community3_i = { - .name = "------- GPIO Community 3 -------", - .pcr_port_id = 0xac, - .group_count = ARRAY_SIZE(lewisburg_community3_i_groups), - .groups = lewisburg_community3_i_groups, + .name = "------- GPIO Community 3 -------", + .pcr_port_id = 0xac, + .groups = lewisburg_community3_i_groups, + .group_count = ARRAY_SIZE(lewisburg_community3_i_groups), + .cfg_registers = lewisburg_community3_i_cfg_registers, + .cfg_registers_count = ARRAY_SIZE(lewisburg_community3_i_cfg_registers), }; static const struct gpio_group *const lewisburg_community4_jk_groups[] = { @@ -431,10 +619,12 @@ }; static const struct gpio_community lewisburg_community4_jk = { - .name = "------- GPIO Community 4 -------", - .pcr_port_id = 0xab, - .group_count = ARRAY_SIZE(lewisburg_community4_jk_groups), - .groups = lewisburg_community4_jk_groups, + .name = "------- GPIO Community 4 -------", + .pcr_port_id = 0xab, + .groups = lewisburg_community4_jk_groups, + .group_count = ARRAY_SIZE(lewisburg_community4_jk_groups), + .cfg_registers = lewisburg_community4_jk_cfg_registers, + .cfg_registers_count = ARRAY_SIZE(lewisburg_community4_jk_cfg_registers), }; static const struct gpio_group *const lewisburg_community5_ghl_groups[] = { @@ -444,10 +634,13 @@ }; static const struct gpio_community lewisburg_community5_ghl = { - .name = "------- GPIO Community 5 -------", - .pcr_port_id = 0x11, - .group_count = ARRAY_SIZE(lewisburg_community5_ghl_groups), - .groups = lewisburg_community5_ghl_groups, + .name = "------- GPIO Community 5 -------", + .pcr_port_id = 0x11, + .groups = lewisburg_community5_ghl_groups, + .group_count = ARRAY_SIZE(lewisburg_community5_ghl_groups), + .cfg_registers = lewisburg_community4_jk_cfg_registers, + .cfg_registers_count = ARRAY_SIZE(lewisburg_community4_jk_cfg_registers), + }; static const struct gpio_community *const lewisburg_communities[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/40014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7e4e3884f7b087c08325597650b2f2fd5a6a62f Gerrit-Change-Number: 40014 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: mb/google/deltaur: Update ISH firmware name
by Anil Kumar K (Code Review) 10 Jun '23

10 Jun '23

Anil Kumar K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40537 ) Change subject: mb/google/deltaur: Update ISH firmware name ...................................................................... mb/google/deltaur: Update ISH firmware name Bug=b:153847811 Branch=master Test=make build successfull Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> Change-Id: Ic701f224452731e43207836882d649580b76db3a --- M src/mainboard/google/deltaur/variants/baseboard/devicetree.cb 1 file changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/40537/1 diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index e0b3d50..831c1c4 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -175,7 +175,13 @@ device pci 11.2 off end # UART5 device pci 11.3 off end # UART6 - device pci 12.0 on end # ISH + device pci 12.0 on + chip drivers/intel/ish + register "firmware_name" = ""deltaur_ish.bin"" + device generic 0 on end + end + end # ISH + device pci 12.6 off end # GSPI #2 device pci 13.0 off end # GSPI #3 device pci 13.1 off end # GSPI #4 -- To view, visit https://review.coreboot.org/c/coreboot/+/40537 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic701f224452731e43207836882d649580b76db3a Gerrit-Change-Number: 40537 Gerrit-PatchSet: 1 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: Documentation/soc/intel: Add documentation for MCU update
by Varshit B Pandya (Code Review) 10 Jun '23

10 Jun '23

Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34657 ) Change subject: Documentation/soc/intel: Add documentation for MCU update ...................................................................... Documentation/soc/intel: Add documentation for MCU update Change-Id: I3deb24550c1f1cd4c7b8082af75115ca174c295a Signed-off-by: Pandya, Varshit B <varshit.b.pandya(a)intel.com> --- A Documentation/soc/intel/ucode_update/Flash_Layout.PNG A Documentation/soc/intel/ucode_update/microcode_update_model.md 2 files changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/34657/1 diff --git a/Documentation/soc/intel/ucode_update/Flash_Layout.PNG b/Documentation/soc/intel/ucode_update/Flash_Layout.PNG new file mode 100644 index 0000000..ac18977 --- /dev/null +++ b/Documentation/soc/intel/ucode_update/Flash_Layout.PNG Binary files differ diff --git a/Documentation/soc/intel/ucode_update/microcode_update_model.md b/Documentation/soc/intel/ucode_update/microcode_update_model.md new file mode 100644 index 0000000..e2d7f35 --- /dev/null +++ b/Documentation/soc/intel/ucode_update/microcode_update_model.md @@ -0,0 +1,43 @@ +# Microcode update mechanism for devices in field + +## Introduction + +Processor microcode (MCU) is akin to processor firmware. Processors may need updates to their microcode to operate correctly. These updates fix bugs/errata that can cause anything from incorrect processing, to code and data corruption, and system lockups. + +##Problem Statement + +As per chrome design, any field updatable FW has to be first verified by vboot (chrome root of trust - CROT) before it is allowed to run on the system. CROT executes on the CPU, hence FW such as MCU loaded before the CPU reset cannot be verified before it actually gets loaded. As a result today Chromebooks are not able to apply MCU in the field. This proposal tries to address the issue + +Prior to CPU reset, the CPU HW locates the FIT table from the storage, walks over the FIT table and picks-up the MCU that matches the CPU Family, Model, Stepping and PLATFORM ID with the highest revision ID. CPU verifies that MCU is signed by Intel and once verification is successful, it attempts to load the MCU. + +However FIT does not contain any fall back mechanism. If one MCU loading fails for whatever reason, it drops the further loading process and moves on to CPU reset. While it is fairly a remote chance, in case of any failure to load MCU which cause hang like situations before CPU reset, a platform based mechanism can be put in place to enter recovery mode. As detailed below, if we are using BUC register based top swap implementation, then an RTC reset may be required to clear top swap bit. + +## Design Proposal + +The proposal relies on the following Intel SoC features: + +1. Top swap, which enables the BIOS to have 2 bootblocks and bot from either using a RTC backed Top swap control bit in BUC register. +2. Firmware Interface Table (FIT) based MCU loading. + +The idea is to have 2 bootblocks, each having its own FIT table. The FIT in one of them will be configured to point to an MCU in RO firmware, and the FIT in other one will point to a fixed flash region (aka MCU staging area), which will contain an MCU from RW firmware. + +Top-swap feature of Intel CPUs, will be used to switch between 2 bootblocks, based on the bootmode i.e., recovery or normal/developer mode. + +Coreboot will keep the MCU staging area updated with the MCU from the currently selected RW firmware. + +## Implementation Details + +1. Create 2 BBs (bb_ro_ucode and bb_staged_ucode) each containing their own FIT tables. Both bootblocks will be in the RO section. + a. bb_ro_ucode contains a FIT which has pointer to MCU (microcode_blob.bin) which resides in RO section. This is will be used in the recovery scenario. + b. bb_staged_ucode is identical to bb_ro_ucode but contains a FIT which has pointer to a MCU that will reside in a staging area. +2. Create a MCU staging area + a. Reserve a region in the FMAP which is equal to or greater than the MCU size specified in the BWG for that SoC. This is a RW region just lke the RW_MRC_CACHE. + b. MCU from RW-A/RW-B will be copied to this region during boot. + c. A Flash Protected Range (FPR) should be configured to write protect this MCU Staging area. + d. bb_staged_ucode FIT points to the MCU in this staging area. +3. The resulting flash layout is shown below, +**Flash Layout** +![Flash Layout][flash_layout] +[flash_layout]: Flash_Layout.PNG + +4. The proposed design uses the PCR register based control for top-swap -- To view, visit https://review.coreboot.org/c/coreboot/+/34657 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3deb24550c1f1cd4c7b8082af75115ca174c295a Gerrit-Change-Number: 34657 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-MessageType: newchange

6 15

Change in coreboot[master]: emulation/qemu-i440fx: Add \_SB.PCI0.MBRS
by Paul Menzel (Code Review) 10 Jun '23

10 Jun '23

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38304 ) Change subject: emulation/qemu-i440fx: Add \_SB.PCI0.MBRS ...................................................................... emulation/qemu-i440fx: Add \_SB.PCI0.MBRS Linux 5.4.8 shows the ACPI error below. [ 0.732324] ACPI BIOS Error (bug): Could not resolve symbol [\_SB.PCI0.MBRS], AE_NOT_FOUND (20190816/dswload2-159) [ 0.732784] ACPI Error: AE_NOT_FOUND, During name lookup/catalog (20190816/psobject-220) So, add that symbol. Copied from (removed) `src/mainboard/hp/dl145_g1/dsdt.asl`. Change-Id: I0243f6a469f5addbf2f09f3aed52d1a067b22cc9 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/emulation/qemu-i440fx/dsdt.asl 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/38304/1 diff --git a/src/mainboard/emulation/qemu-i440fx/dsdt.asl b/src/mainboard/emulation/qemu-i440fx/dsdt.asl index 9bef7d9..95b4b42 100644 --- a/src/mainboard/emulation/qemu-i440fx/dsdt.asl +++ b/src/mainboard/emulation/qemu-i440fx/dsdt.asl @@ -33,6 +33,13 @@ Scope(\_SB) { Device(PCI0) { + /* Dummy device to hold auto generated reserved resources */ + Device(MBRS) { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x01) + External(_CRS) /* Resource Template in SSDT */ + } + Name(_HID, EisaId("PNP0A03")) Name(_UID, 1) } -- To view, visit https://review.coreboot.org/c/coreboot/+/38304 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0243f6a469f5addbf2f09f3aed52d1a067b22cc9 Gerrit-Change-Number: 38304 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: [UNTESTED] intel/stm: Introduce stm_update_smm_info()
by Nico Huber (Code Review) 10 Jun '23

10 Jun '23

Hello Kyösti Mälkki, Aaron Durbin, Arthur Heymans, cedarhouse1(a)comcast.net, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38768 to review the following change. Change subject: [UNTESTED] intel/stm: Introduce stm_update_smm_info() ...................................................................... [UNTESTED] intel/stm: Introduce stm_update_smm_info() Add a helper that will be called from `mp_init.c`. This allows to keep SMRAM allocations local to STM code. Call it after validation of the original numbers. Change-Id: I2c29a4adfc78f21126122caefffa27a4d6d8c5df Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/cpu/x86/mp_init.c M src/security/intel/stm/SmmStm.h M src/security/intel/stm/StmPlatformSmm.c 3 files changed, 26 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/38768/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 9bc4aab..5b34d4b 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -1042,26 +1042,6 @@ &state->smm_save_state_size); /* - * Make sure there is enough room for the SMM descriptor - */ - if (CONFIG(STM)) { - state->smm_save_state_size += - sizeof(TXT_PROCESSOR_SMM_DESCRIPTOR); - - /* Currently, the CPU SMM save state size is based on a simplistic - * algorithm. (align on 4K) - * note: In the future, this will need to handle newer x86 processors - * that require alignment of the save state on 32K boundaries. - * The alignment is done here because coreboot has a hard coded - * value of 0x400 for this value. - * Also, this alignment only works on CPUs less than 5 threads - */ - if (CONFIG(STM)) - state->smm_save_state_size = - ALIGN_UP(state->smm_save_state_size, 0x1000); - } - - /* * Default to smm_initiate_relocation() if trigger callback isn't * provided. */ @@ -1093,8 +1073,11 @@ mp_state.ops.relocation_handler != NULL) smm_enable(); - if (is_smm_enabled()) + if (is_smm_enabled()) { printk(BIOS_INFO, "Will perform SMM setup.\n"); + stm_update_smm_info(&mp_state.perm_smbase, &mp_state.perm_smsize, + &mp_state.smm_save_state_size); + } mp_params.num_cpus = mp_state.cpu_count; /* Gather microcode information. */ diff --git a/src/security/intel/stm/SmmStm.h b/src/security/intel/stm/SmmStm.h index 1690255..f6ab0bf 100644 --- a/src/security/intel/stm/SmmStm.h +++ b/src/security/intel/stm/SmmStm.h @@ -27,6 +27,13 @@ */ int load_stm_image(uintptr_t mseg); +#if CONFIG(STM) +void stm_update_smm_info( + uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size); +#else +static inline void stm_update_smm_info(uintptr_t *, size_t *, size_t *) {} +#endif + void stm_setup( uintptr_t mseg, int cpu, uintptr_t smbase, uintptr_t smbase_base, uint32_t offset32); diff --git a/src/security/intel/stm/StmPlatformSmm.c b/src/security/intel/stm/StmPlatformSmm.c index 5be6ee7..c389afa 100644 --- a/src/security/intel/stm/StmPlatformSmm.c +++ b/src/security/intel/stm/StmPlatformSmm.c @@ -154,6 +154,21 @@ static int stm_load_status = 0; +void stm_update_smm_info( + uintptr_t *const perm_smbase, size_t *const perm_smsize, + size_t *const smm_save_state_size) +{ + *smm_save_state_size += sizeof(TXT_PROCESSOR_SMM_DESCRIPTOR); + + /* + * Currently, the CPU SMM save state size is based on a simplistic + * algorithm. (align on 4K) + * note: In the future, this will need to handle newer x86 processors + * that require alignment of the save state on 32K boundaries. + */ + *smm_save_state_size = ALIGN_UP(*smm_save_state_size, 0x1000); +} + void stm_setup(uintptr_t mseg, int cpu, uintptr_t smbase, uintptr_t base_smbase, uint32_t offset32) { -- To view, visit https://review.coreboot.org/c/coreboot/+/38768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c29a4adfc78f21126122caefffa27a4d6d8c5df Gerrit-Change-Number: 38768 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: cedarhouse1(a)comcast.net Gerrit-MessageType: newchange

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coreboot-gerrit April 2020