coreboot-gerrit December 2020

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Change in coreboot[master]: [TEST only]: mb/google/dedede/var/drawcia: Use TABLEMODE bit to load ...
by Chen Wisley (Code Review) 07 Aug '23

07 Aug '23

Chen Wisley has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45190 ) Change subject: [TEST only]: mb/google/dedede/var/drawcia: Use TABLEMODE bit to load LV or TFC module ...................................................................... [TEST only]: mb/google/dedede/var/drawcia: Use TABLEMODE bit to load LV or TFC module BUG=none TEST=emerge-dedede coreboot, change tabletmode bit in CBI and dump ssdt table, Change-Id: I35dcc7bb82ceb014fd40b794ccf190b226061281 --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 3 files changed, 16 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/45190/1 diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 2bb255f..c9c2803 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -11,6 +11,8 @@ select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI select EC_GOOGLE_CHROMEEC_SKUID + select FW_CONFIG + select FW_CONFIG_SOURCE_CHROMEEC_CBI select GOOGLE_SMBIOS_MAINBOARD_VERSION select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 363307b..01fcad0 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -1,3 +1,10 @@ +fw_config + field TABLETMODE 10 + option TABLETMODE_DISABLED 0 + option TABLETMODE_ENABLED 1 + end +end + chip soc/intel/jasperlake device cpu_cluster 0 on device lapic 0 on end diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index 0506cd4..2c78b21 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -242,7 +242,13 @@ register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" - device i2c 36 on end + device i2c 36 on + probe TABLETMODE TABLETMODE_DISABLED + end + device i2c 10 on + probe TABLETMODE TABLETMODE_ENABLED + end + end chip drivers/intel/mipi_camera register "acpi_hid" = "ACPI_DT_NAMESPACE_HID" -- To view, visit https://review.coreboot.org/c/coreboot/+/45190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35dcc7bb82ceb014fd40b794ccf190b226061281 Gerrit-Change-Number: 45190 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-MessageType: newchange

4 15

Change in coreboot[master]: mb/google/dedede/variants/drawcia: Reduce TCC offset from 20 to 5
by Sumeet R Pawnikar (Code Review) 07 Aug '23

07 Aug '23

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45267 ) Change subject: mb/google/dedede/variants/drawcia: Reduce TCC offset from 20 to 5 ...................................................................... mb/google/dedede/variants/drawcia: Reduce TCC offset from 20 to 5 Reduce TCC offset value from 20 to 5 for Thermal Control Circuit(TCC) activation. Change-Id: I9222a922a55d27bc175f219c5bbb59b246abec9f Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/45267/1 diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index 395dee3..adde5bc 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -62,7 +62,7 @@ .tdp_pl2_override = 15, }" - register "tcc_offset" = "20" # TCC of 85C + register "tcc_offset" = "5" # TCC of 100C device domain 0 on device pci 04.0 on -- To view, visit https://review.coreboot.org/c/coreboot/+/45267 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9222a922a55d27bc175f219c5bbb59b246abec9f Gerrit-Change-Number: 45267 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: nb/intel/x4x: Relocate read to TPM base address
by Angel Pons (Code Review) 07 Aug '23

07 Aug '23

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45390 ) Change subject: nb/intel/x4x: Relocate read to TPM base address ...................................................................... nb/intel/x4x: Relocate read to TPM base address Other northbridges do it at the start of raminit. Also, since the TPM access register is 8 bits wide, use 8-bit ops instead of 32-bit ops. This register works the same for all TXT-enabled northbridges: If the TPM access register is valid, and the establishment bit (bit 0) is set, then a DRTM has not been established on the platform (or the TPM is not present), and the memory will be unlocked. If bit 0 is clear, then the memory may remain locked depending on whether it could contain secrets. Change-Id: Ic36a2810a861758ce733fe80c4e555439e2ffb7b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/x4x/bootblock.c M src/northbridge/intel/x4x/raminit.c 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/45390/1 diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c index baa4ae3..e83a2b8 100644 --- a/src/northbridge/intel/x4x/bootblock.c +++ b/src/northbridge/intel/x4x/bootblock.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <arch/bootblock.h> -#include <arch/mmio.h> #include <device/pci_ops.h> #include "x4x.h" @@ -9,9 +8,6 @@ void bootblock_early_northbridge_init(void) { - /* Disable LaGrande Technology (LT) */ - read32((void *)TPM_BASE_ADDRESS); - const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | 16 | 1; pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO, reg32); } diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index a62771d..6536fbf 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <arch/mmio.h> #include <device/pci_ops.h> #include <device/smbus_host.h> #include <cbmem.h> @@ -616,6 +617,9 @@ timestamp_add_now(TS_BEFORE_INITRAM); printk(BIOS_DEBUG, "Setting up RAM controller.\n"); + /* Disable LaGrande Technology (LT) */ + read8((void *)TPM_BASE_ADDRESS); + pci_write_config8(HOST_BRIDGE, 0xdf, 0xff); memset(&s, 0, sizeof(struct sysinfo)); -- To view, visit https://review.coreboot.org/c/coreboot/+/45390 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic36a2810a861758ce733fe80c4e555439e2ffb7b Gerrit-Change-Number: 45390 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: cpu/x86: Move SMI GSMI calls entry to a common place
by Arthur Heymans (Code Review) 07 Aug '23

07 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45474 ) Change subject: cpu/x86: Move SMI GSMI calls entry to a common place ...................................................................... cpu/x86: Move SMI GSMI calls entry to a common place Now that SMM save states are handled in a common place so can the GSMI calls entry. Change-Id: I93639d8d0fde2e874eb9b963c449be1b754ca63d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/elog/gsmi.c M src/include/elog.h M src/soc/amd/picasso/smihandler.c M src/soc/amd/stoneyridge/smihandler.c M src/soc/intel/baytrail/smihandler.c M src/soc/intel/braswell/smihandler.c M src/soc/intel/broadwell/smihandler.c M src/soc/intel/common/block/smm/smihandler.c M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/lynxpoint/smihandler.c 10 files changed, 37 insertions(+), 194 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/45474/1 diff --git a/src/drivers/elog/gsmi.c b/src/drivers/elog/gsmi.c index ebdde19..128f4a7 100644 --- a/src/drivers/elog/gsmi.c +++ b/src/drivers/elog/gsmi.c @@ -2,6 +2,7 @@ #include <console/console.h> #include <elog.h> +#include <cpu/x86/save_state.h> #define GSMI_RET_SUCCESS 0x00 #define GSMI_RET_INVALID_PARAMETER 0x82 @@ -43,7 +44,7 @@ } /* Param is usually EBX, ret in EAX */ -u32 gsmi_exec(u8 command, u32 *param) +static u32 gsmi_exec(u8 command, u32 *param) { struct gsmi_set_eventlog_param *sel; struct gsmi_set_eventlog_type1 *type1; @@ -121,3 +122,28 @@ return ret; } + +void apmc_smi_gsmi(void) +{ + u8 sub_command; + u16 ax; + u32 ret, param; + const int apmc_node = get_apmc_node(APM_CNT_ELOG_GSMI); + + if (apmc_node < 0) + return; + + /* Command and return value in EAX */ + if (get_save_state_reg(RAX, apmc_node, &ax, sizeof(ax))) + return; + + sub_command = (ax >> 8); + + /* Parameter buffer in EBX */ + if (get_save_state_reg(RBX, apmc_node, &param, sizeof(param))) + return; + + ret = gsmi_exec(sub_command, &param); + set_save_state_reg(RAX, apmc_node, &ret, sizeof(ret)); +} + diff --git a/src/include/elog.h b/src/include/elog.h index 6c2c531..89195c5 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -248,7 +248,8 @@ static inline int elog_gsmi_add_event_word(u8 event_type, u16 data) { return 0; } #endif -extern u32 gsmi_exec(u8 command, u32 *param); +void apmc_smi_gsmi(void); +//extern u32 gsmi_exec(u8 command, u32 *param); #if CONFIG(ELOG_BOOT_COUNT) u32 boot_count_read(void); diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c index 7e762a9..89df86f 100644 --- a/src/soc/amd/picasso/smihandler.c +++ b/src/soc/amd/picasso/smihandler.c @@ -57,25 +57,6 @@ return NULL; } -static void southbridge_smi_gsmi(void) -{ - u8 sub_command; - amd64_smm_state_save_area_t *io_smi; - u32 reg_ebx; - - io_smi = find_save_state(APM_CNT_ELOG_GSMI); - if (!io_smi) - return; - /* Command and return value in EAX */ - sub_command = (io_smi->rax >> 8) & 0xff; - - /* Parameter buffer in EBX */ - reg_ebx = io_smi->rbx; - - /* drivers/elog/gsmi.c */ - io_smi->rax = gsmi_exec(sub_command, &reg_ebx); -} - static void southbridge_smi_store(void) { u8 sub_command; @@ -108,7 +89,7 @@ break; case APM_CNT_ELOG_GSMI: if (CONFIG(ELOG_GSMI)) - southbridge_smi_gsmi(); + apmc_smi_gsmi(); break; case APM_CNT_SMMSTORE: if (CONFIG(SMMSTORE)) diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index be55458..d55c545 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -55,25 +55,6 @@ return NULL; } -static void southbridge_smi_gsmi(void) -{ - u8 sub_command; - amd64_smm_state_save_area_t *io_smi; - u32 reg_ebx; - - io_smi = find_save_state(APM_CNT_ELOG_GSMI); - if (!io_smi) - return; - /* Command and return value in EAX */ - sub_command = (io_smi->rax >> 8) & 0xff; - - /* Parameter buffer in EBX */ - reg_ebx = io_smi->rbx; - - /* drivers/elog/gsmi.c */ - io_smi->rax = gsmi_exec(sub_command, &reg_ebx); -} - static void southbridge_smi_store(void) { u8 sub_command; @@ -106,7 +87,7 @@ break; case APM_CNT_ELOG_GSMI: if (CONFIG(ELOG_GSMI)) - southbridge_smi_gsmi(); + apmc_smi_gsmi(); break; case APM_CNT_SMMSTORE: if (CONFIG(SMMSTORE)) diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index 6f3f07e..bfe933f 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -186,26 +186,6 @@ return NULL; } -static void southbridge_smi_gsmi(void) -{ - u32 *ret, *param; - uint8_t sub_command; - em64t100_smm_state_save_area_t *io_smi = smi_apmc_find_state_save(APM_CNT_ELOG_GSMI); - - if (!io_smi) - return; - - /* Command and return value in EAX */ - ret = (u32 *)&io_smi->rax; - sub_command = (uint8_t)(*ret >> 8); - - /* Parameter buffer in EBX */ - param = (u32 *)&io_smi->rbx; - - /* drivers/elog/gsmi.c */ - *ret = gsmi_exec(sub_command, param); -} - /* * soc_legacy: A payload (Depthcharge) has indicated that the * legacy payload (SeaBIOS) is being loaded. Switch devices that are @@ -327,7 +307,7 @@ break; case APM_CNT_ELOG_GSMI: if (CONFIG(ELOG_GSMI)) - southbridge_smi_gsmi(); + apmc_smi_gsmi(); break; case APM_CNT_LEGACY: soc_legacy(); diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c index a2c26c11..f6ac703 100644 --- a/src/soc/intel/braswell/smihandler.c +++ b/src/soc/intel/braswell/smihandler.c @@ -220,26 +220,6 @@ return NULL; } -static void southbridge_smi_gsmi(void) -{ - u32 *ret, *param; - uint8_t sub_command; - em64t100_smm_state_save_area_t *io_smi = smi_apmc_find_state_save(APM_CNT_ELOG_GSMI); - - if (!io_smi) - return; - - /* Command and return value in EAX */ - ret = (u32 *)&io_smi->rax; - sub_command = (uint8_t)(*ret >> 8); - - /* Parameter buffer in EBX */ - param = (u32 *)&io_smi->rbx; - - /* drivers/elog/gsmi.c */ - *ret = gsmi_exec(sub_command, param); -} - static void southbridge_smi_store(void) { u8 sub_command, ret; @@ -307,7 +287,7 @@ break; case APM_CNT_ELOG_GSMI: if (CONFIG(ELOG_GSMI)) - southbridge_smi_gsmi(); + apmc_smi_gsmi(); break; case APM_CNT_SMMSTORE: if (CONFIG(SMMSTORE)) diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index 86be400..ea5bf8a 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -267,27 +267,6 @@ return NULL; } -static void southbridge_smi_gsmi(void) -{ - u32 *ret, *param; - u8 sub_command; - em64t101_smm_state_save_area_t *io_smi = - smi_apmc_find_state_save(APM_CNT_ELOG_GSMI); - - if (!io_smi) - return; - - /* Command and return value in EAX */ - ret = (u32 *)&io_smi->rax; - sub_command = (u8)(*ret >> 8); - - /* Parameter buffer in EBX */ - param = (u32 *)&io_smi->rbx; - - /* drivers/elog/gsmi.c */ - *ret = gsmi_exec(sub_command, param); -} - static void southbridge_smi_store(void) { u8 sub_command, ret; @@ -347,7 +326,7 @@ break; case APM_CNT_ELOG_GSMI: if (CONFIG(ELOG_GSMI)) - southbridge_smi_gsmi(); + apmc_smi_gsmi(); break; case APM_CNT_SMMSTORE: if (CONFIG(SMMSTORE)) diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 7bd17c3..77eaad9 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -266,49 +266,6 @@ } } -static void southbridge_smi_gsmi( - const struct smm_save_state_ops *save_state_ops) -{ - u8 sub_command, ret; - void *io_smi = NULL; - uint32_t reg_ebx; - - io_smi = find_save_state(save_state_ops, APM_CNT_ELOG_GSMI); - if (!io_smi) - return; - /* Command and return value in EAX */ - sub_command = (save_state_ops->get_reg(io_smi, RAX) >> 8) - & 0xff; - - /* Parameter buffer in EBX */ - reg_ebx = save_state_ops->get_reg(io_smi, RBX); - - /* drivers/elog/gsmi.c */ - ret = gsmi_exec(sub_command, &reg_ebx); - save_state_ops->set_reg(io_smi, RAX, ret); -} - -static void southbridge_smi_store( - const struct smm_save_state_ops *save_state_ops) -{ - u8 sub_command, ret; - void *io_smi; - uint32_t reg_ebx; - - io_smi = find_save_state(save_state_ops, APM_CNT_SMMSTORE); - if (!io_smi) - return; - /* Command and return value in EAX */ - sub_command = (save_state_ops->get_reg(io_smi, RAX) >> 8) & 0xff; - - /* Parameter buffer in EBX */ - reg_ebx = save_state_ops->get_reg(io_smi, RBX); - - /* drivers/smmstore/smi.c */ - ret = smmstore_exec(sub_command, (void *)reg_ebx); - save_state_ops->set_reg(io_smi, RAX, ret); -} - static void finalize(void) { static int finalize_done; @@ -379,7 +336,7 @@ break; case APM_CNT_ELOG_GSMI: if (CONFIG(ELOG_GSMI)) - southbridge_smi_gsmi(save_state_ops); + apmc_smi_gsmi(); break; case APM_CNT_SMMSTORE: if (CONFIG(SMMSTORE)) diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 49e306f..3ce4ba8 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -230,27 +230,6 @@ return NULL; } -static void southbridge_smi_gsmi(void) -{ - u32 *ret, *param; - u8 sub_command; - em64t101_smm_state_save_area_t *io_smi = - smi_apmc_find_state_save(APM_CNT_ELOG_GSMI); - - if (!io_smi) - return; - - /* Command and return value in EAX */ - ret = (u32*)&io_smi->rax; - sub_command = (u8)(*ret >> 8); - - /* Parameter buffer in EBX */ - param = (u32*)&io_smi->rbx; - - /* drivers/elog/gsmi.c */ - *ret = gsmi_exec(sub_command, param); -} - static void southbridge_smi_store(void) { u8 sub_command, ret; @@ -322,7 +301,7 @@ break; case APM_CNT_ELOG_GSMI: if (CONFIG(ELOG_GSMI)) - southbridge_smi_gsmi(); + apmc_smi_gsmi(); break; case APM_CNT_SMMSTORE: if (CONFIG(SMMSTORE)) diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index e4ebffd..9464904 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -218,27 +218,6 @@ return NULL; } -static void southbridge_smi_gsmi(void) -{ - u32 *ret, *param; - u8 sub_command; - em64t101_smm_state_save_area_t *io_smi = - smi_apmc_find_state_save(APM_CNT_ELOG_GSMI); - - if (!io_smi) - return; - - /* Command and return value in EAX */ - ret = (u32*)&io_smi->rax; - sub_command = (u8)(*ret >> 8); - - /* Parameter buffer in EBX */ - param = (u32*)&io_smi->rbx; - - /* drivers/elog/gsmi.c */ - *ret = gsmi_exec(sub_command, param); -} - static void southbridge_smi_store(void) { u8 sub_command, ret; @@ -323,7 +302,7 @@ break; case APM_CNT_ELOG_GSMI: if (CONFIG(ELOG_GSMI)) - southbridge_smi_gsmi(); + apmc_smi_gsmi(); break; case APM_CNT_SMMSTORE: if (CONFIG(SMMSTORE)) -- To view, visit https://review.coreboot.org/c/coreboot/+/45474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93639d8d0fde2e874eb9b963c449be1b754ca63d Gerrit-Change-Number: 45474 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 12

Change in coreboot[master]: cpu/x86/smm: Move smmstore entry to a common place
by Arthur Heymans (Code Review) 07 Aug '23

07 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45475 ) Change subject: cpu/x86/smm: Move smmstore entry to a common place ...................................................................... cpu/x86/smm: Move smmstore entry to a common place Now that SMM save states are handled in a common place so can the SMMSTORE calls entry. Change-Id: Ieb8d01a2d33e9214c3df7f909dcfab49a05fffff Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/smmstore/smi.c M src/include/smmstore.h M src/soc/amd/picasso/smihandler.c M src/soc/amd/stoneyridge/smihandler.c M src/soc/intel/baytrail/smihandler.c M src/soc/intel/braswell/smihandler.c M src/soc/intel/broadwell/smihandler.c M src/soc/intel/common/block/smm/smihandler.c M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/lynxpoint/smihandler.c 10 files changed, 35 insertions(+), 146 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/45475/1 diff --git a/src/drivers/smmstore/smi.c b/src/drivers/smmstore/smi.c index b21423e..ba1d9e8 100644 --- a/src/drivers/smmstore/smi.c +++ b/src/drivers/smmstore/smi.c @@ -6,6 +6,7 @@ #include <smmstore.h> #include <stddef.h> #include <stdint.h> +#include <cpu/x86/save_state.h> /* * Check that the given range is legal. @@ -24,7 +25,7 @@ } /* Param is usually EBX, ret in EAX */ -uint32_t smmstore_exec(uint8_t command, void *param) +static uint32_t smmstore_exec(uint8_t command, void *param) { uint32_t ret = SMMSTORE_RET_FAILURE; @@ -76,3 +77,27 @@ return ret; } + +void apmc_smmtore_handler(void) +{ + u8 sub_command; + u16 ax; + u32 ret, param; + const int apmc_node = get_apmc_node(APM_CNT_SMMSTORE); + + if (apmc_node < 0) + return; + + /* Command and return value in EAX */ + if (get_save_state_reg(RAX, apmc_node, &ax, sizeof(ax))) + return; + + sub_command = (ax >> 8); + + /* Parameter buffer in EBX */ + if (get_save_state_reg(RBX, apmc_node, &param, sizeof(param))) + return; + + ret = smmstore_exec(sub_command, &param); + set_save_state_reg(RAX, apmc_node, &ret, sizeof(ret)); +} diff --git a/src/include/smmstore.h b/src/include/smmstore.h index ff0b720..3c50690 100644 --- a/src/include/smmstore.h +++ b/src/include/smmstore.h @@ -27,7 +27,7 @@ }; /* SMM responder */ -uint32_t smmstore_exec(uint8_t command, void *param); +void apmc_smmtore_handler(void); /* implementation */ int smmstore_read_region(void *buf, ssize_t *bufsize); diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c index 89df86f..e6be072 100644 --- a/src/soc/amd/picasso/smihandler.c +++ b/src/soc/amd/picasso/smihandler.c @@ -57,25 +57,6 @@ return NULL; } -static void southbridge_smi_store(void) -{ - u8 sub_command; - amd64_smm_state_save_area_t *io_smi; - u32 reg_ebx; - - io_smi = find_save_state(APM_CNT_SMMSTORE); - if (!io_smi) - return; - /* Command and return value in EAX */ - sub_command = (io_smi->rax >> 8) & 0xff; - - /* Parameter buffer in EBX */ - reg_ebx = io_smi->rbx; - - /* drivers/smmstore/smi.c */ - io_smi->rax = smmstore_exec(sub_command, (void *)reg_ebx); -} - static void sb_apmc_smi_handler(void) { const uint8_t cmd = inb(pm_acpi_smi_cmd_port()); @@ -93,7 +74,7 @@ break; case APM_CNT_SMMSTORE: if (CONFIG(SMMSTORE)) - southbridge_smi_store(); + apmc_smmtore_handler(); break; case APM_CNT_SMMINFO: psp_notify_smm(); diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index d55c545..2163c80 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -55,25 +55,6 @@ return NULL; } -static void southbridge_smi_store(void) -{ - u8 sub_command; - amd64_smm_state_save_area_t *io_smi; - u32 reg_ebx; - - io_smi = find_save_state(APM_CNT_SMMSTORE); - if (!io_smi) - return; - /* Command and return value in EAX */ - sub_command = (io_smi->rax >> 8) & 0xff; - - /* Parameter buffer in EBX */ - reg_ebx = io_smi->rbx; - - /* drivers/smmstore/smi.c */ - io_smi->rax = smmstore_exec(sub_command, (void *)reg_ebx); -} - static void sb_apmc_smi_handler(void) { const uint8_t cmd = inb(pm_acpi_smi_cmd_port()); @@ -91,7 +72,7 @@ break; case APM_CNT_SMMSTORE: if (CONFIG(SMMSTORE)) - southbridge_smi_store(); + apmc_smmtore_handler(); break; } diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index bfe933f..9348ae0 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -240,25 +240,6 @@ LPSS_ACPI_MODE_DISABLE(SPI); } -static void southbridge_smi_store(void) -{ - u8 sub_command, ret; - em64t100_smm_state_save_area_t *io_smi = smi_apmc_find_state_save(APM_CNT_SMMSTORE); - uint32_t reg_ebx; - - if (!io_smi) - return; - /* Command and return value in EAX */ - sub_command = (io_smi->rax >> 8) & 0xff; - - /* Parameter buffer in EBX */ - reg_ebx = io_smi->rbx; - - /* drivers/smmstore/smi.c */ - ret = smmstore_exec(sub_command, (void *)reg_ebx); - io_smi->rax = ret; -} - static void southbridge_smi_apmc(void) { uint8_t reg8; @@ -314,7 +295,7 @@ break; case APM_CNT_SMMSTORE: if (CONFIG(SMMSTORE)) - southbridge_smi_store(); + apmc_smmtore_handler(); break; } diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c index f6ac703..6f8cd62 100644 --- a/src/soc/intel/braswell/smihandler.c +++ b/src/soc/intel/braswell/smihandler.c @@ -220,25 +220,6 @@ return NULL; } -static void southbridge_smi_store(void) -{ - u8 sub_command, ret; - em64t100_smm_state_save_area_t *io_smi = smi_apmc_find_state_save(APM_CNT_SMMSTORE); - uint32_t reg_ebx; - - if (!io_smi) - return; - /* Command and return value in EAX */ - sub_command = (io_smi->rax >> 8) & 0xff; - - /* Parameter buffer in EBX */ - reg_ebx = io_smi->rbx; - - /* drivers/smmstore/smi.c */ - ret = smmstore_exec(sub_command, (void *)reg_ebx); - io_smi->rax = ret; -} - static void southbridge_smi_apmc(void) { uint8_t reg8; @@ -291,7 +272,7 @@ break; case APM_CNT_SMMSTORE: if (CONFIG(SMMSTORE)) - southbridge_smi_store(); + apmc_smmtore_handler(); break; } diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index ea5bf8a..a223bf5 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -267,26 +267,6 @@ return NULL; } -static void southbridge_smi_store(void) -{ - u8 sub_command, ret; - em64t101_smm_state_save_area_t *io_smi = - smi_apmc_find_state_save(APM_CNT_SMMSTORE); - uint32_t reg_ebx; - - if (!io_smi) - return; - /* Command and return value in EAX */ - sub_command = (io_smi->rax >> 8) & 0xff; - - /* Parameter buffer in EBX */ - reg_ebx = io_smi->rbx; - - /* drivers/smmstore/smi.c */ - ret = smmstore_exec(sub_command, (void *)reg_ebx); - io_smi->rax = ret; -} - static void southbridge_smi_apmc(void) { u8 reg8; @@ -330,7 +310,7 @@ break; case APM_CNT_SMMSTORE: if (CONFIG(SMMSTORE)) - southbridge_smi_store(); + apmc_smmtore_handler(); break; } diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 77eaad9..b629ef2 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -340,7 +340,7 @@ break; case APM_CNT_SMMSTORE: if (CONFIG(SMMSTORE)) - southbridge_smi_store(save_state_ops); + apmc_smmtore_handler(); break; case APM_CNT_FINALIZE: finalize(); diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 3ce4ba8..ff61c6f 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -230,26 +230,6 @@ return NULL; } -static void southbridge_smi_store(void) -{ - u8 sub_command, ret; - em64t101_smm_state_save_area_t *io_smi = - smi_apmc_find_state_save(APM_CNT_SMMSTORE); - uintptr_t reg_rbx; - - if (!io_smi) - return; - /* Command and return value in EAX */ - sub_command = (io_smi->rax >> 8) & 0xff; - - /* Parameter buffer in EBX */ - reg_rbx = (uintptr_t)io_smi->rbx; - - /* drivers/smmstore/smi.c */ - ret = smmstore_exec(sub_command, (void *)reg_rbx); - io_smi->rax = ret; -} - static int mainboard_finalized = 0; static void southbridge_smi_apmc(void) @@ -305,7 +285,7 @@ break; case APM_CNT_SMMSTORE: if (CONFIG(SMMSTORE)) - southbridge_smi_store(); + apmc_smmtore_handler(); break; } diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 9464904..a033d68 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -218,26 +218,6 @@ return NULL; } -static void southbridge_smi_store(void) -{ - u8 sub_command, ret; - em64t101_smm_state_save_area_t *io_smi = - smi_apmc_find_state_save(APM_CNT_SMMSTORE); - uint32_t reg_ebx; - - if (!io_smi) - return; - /* Command and return value in EAX */ - sub_command = (io_smi->rax >> 8) & 0xff; - - /* Parameter buffer in EBX */ - reg_ebx = io_smi->rbx; - - /* drivers/smmstore/smi.c */ - ret = smmstore_exec(sub_command, (void *)reg_ebx); - io_smi->rax = ret; -} - static void southbridge_smi_apmc(void) { u8 reg8; @@ -306,7 +286,7 @@ break; case APM_CNT_SMMSTORE: if (CONFIG(SMMSTORE)) - southbridge_smi_store(); + apmc_smmtore_handler(); break; } -- To view, visit https://review.coreboot.org/c/coreboot/+/45475 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb8d01a2d33e9214c3df7f909dcfab49a05fffff Gerrit-Change-Number: 45475 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 15

Change in coreboot[master]: util/cbfstool: Add genarated files to .gitignore.
by Masanori Ogino (Code Review) 07 Aug '23

07 Aug '23

Masanori Ogino has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45524 ) Change subject: util/cbfstool: Add genarated files to .gitignore. ...................................................................... util/cbfstool: Add genarated files to .gitignore. TEST=Run `make -C util/cbfstool` and confirm that there is no remaining untracked files. Signed-off-by: Masanori Ogino <mogino(a)acm.org> Change-Id: I5e03ab10f7c627ee7cd1cd5ec8e871cda4986b46 --- M .gitignore 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/45524/1 diff --git a/.gitignore b/.gitignore index 190d3717..dfb8bb3 100644 --- a/.gitignore +++ b/.gitignore @@ -93,6 +93,9 @@ util/cbfstool/cbfs-compression-tool util/cbfstool/cbfstool util/cbfstool/fmaptool +util/cbfstool/fmd_parser.h +util/cbfstool/fmd_scanner.h +util/cbfstool/ifittool util/cbfstool/ifwitool util/cbfstool/rmodtool util/cbmem/.dependencies -- To view, visit https://review.coreboot.org/c/coreboot/+/45524 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e03ab10f7c627ee7cd1cd5ec8e871cda4986b46 Gerrit-Change-Number: 45524 Gerrit-PatchSet: 1 Gerrit-Owner: Masanori Ogino <mogino(a)acm.org> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: [RFC] Introduce vpd_get_option()
by Nico Huber (Code Review) 07 Aug '23

07 Aug '23

Hello Martin Roth, Marc Jones, Johnny Lin, Angel Pons, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45774 to review the following change. Change subject: [RFC] Introduce vpd_get_option() ...................................................................... [RFC] Introduce vpd_get_option() Allows to read options from VPD regions in flash. This is currently very limited as type information is missing both in the get_option() interface and the backend. Hence, every option to be queried needs to be added manually to vpd_get_option(). Storing options in VPD should only be an interim solution, VPD doesn't seem to be meant to be used like that. The lack of typing also makes this a bit ugly. But this way, we can keep that local. Change-Id: I825388f767d1d87f44923eff5ae6680105fa801e Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/Kconfig M src/drivers/vpd/vpd.c M src/drivers/vpd/vpd.h M src/include/option.h 4 files changed, 58 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/45774/1 diff --git a/src/Kconfig b/src/Kconfig index 40310bb..40e275b 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -135,6 +135,46 @@ every boot. Use this if you want the NVRAM configuration to never be modified from its default values. +config USE_VPD_OPTIONS + bool "Use VPD for configuration values" + depends on VPD + help + Enable this option if coreboot shall read options from the VPD + regions in flash. + This is currently very limited as type information is missing + both in the get_option() interface and the backend. Hence, every + option to be queried needs to be added manually to vpd_get_option(). + +if USE_VPD_OPTIONS + +choice + prompt "VPD region to query" + default VPD_OPTION_REGION_RW_THEN_RO + +config VPD_OPTION_REGION_RO + bool "RO" + +config VPD_OPTION_REGION_RW + bool "RW" + +config VPD_OPTION_REGION_RO_THEN_RW + bool "RO, then RW" + +config VPD_OPTION_REGION_RW_THEN_RO + bool "RW, then RO" + +endchoice + +# Keep in sync with `drivers/vpd/vpd.h`. +config VPD_OPTION_REGION + int + default 3 if VPD_OPTION_REGION_RW_THEN_RO + default 2 if VPD_OPTION_REGION_RO_THEN_RW + default 1 if VPD_OPTION_REGION_RW + default 0 + +endif # USE_VPD_OPTIONS + config USE_MAINBOARD_OPTIONS bool help diff --git a/src/drivers/vpd/vpd.c b/src/drivers/vpd/vpd.c index d3ff370..727a616 100644 --- a/src/drivers/vpd/vpd.c +++ b/src/drivers/vpd/vpd.c @@ -5,6 +5,7 @@ #include <cbmem.h> #include <ctype.h> #include <fmap.h> +#include <option.h> #include <program_loading.h> #include <string.h> #include <timestamp.h> @@ -297,4 +298,17 @@ return true; } +enum cb_err vpd_get_option(void *const dest, const char *const name) +{ + if (strcmp(name, "debug_level") == 0) { + int i; + if (vpd_get_int("coreboot_log_level", CONFIG_VPD_OPTION_REGION, &i)) { + *(char *)dest = (char)i; + return CB_SUCCESS; + } + } + + return CB_CMOS_OPTION_NOT_FOUND; +} + ROMSTAGE_CBMEM_INIT_HOOK(cbmem_add_cros_vpd) diff --git a/src/drivers/vpd/vpd.h b/src/drivers/vpd/vpd.h index 817867a..5c2a80f 100644 --- a/src/drivers/vpd/vpd.h +++ b/src/drivers/vpd/vpd.h @@ -7,6 +7,7 @@ #define GOOGLE_VPD_2_0_OFFSET 0x600 +/* Keep in sync with Kconfig VPD_OPTION_REGION. */ enum vpd_region { VPD_RO, VPD_RW, diff --git a/src/include/option.h b/src/include/option.h index 86c8ff1..2822bcb 100644 --- a/src/include/option.h +++ b/src/include/option.h @@ -11,6 +11,7 @@ enum cb_err cmos_get_option(void *dest, const char *name); enum cb_err mainboard_get_option(void *dest, const char *name); +enum cb_err vpd_get_option(void *dest, const char *name); static inline enum cb_err set_option(const char *name, void *val) { @@ -26,6 +27,8 @@ if (CONFIG(USE_OPTION_TABLE)) ret = cmos_get_option(dest, name); + if (CONFIG(USE_VPD_OPTIONS) && ret != CB_SUCCESS) + ret = vpd_get_option(dest, name); if (CONFIG(USE_MAINBOARD_OPTIONS) && ret != CB_SUCCESS) ret = mainboard_get_option(dest, name); -- To view, visit https://review.coreboot.org/c/coreboot/+/45774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I825388f767d1d87f44923eff5ae6680105fa801e Gerrit-Change-Number: 45774 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Marc Jones <marc.jones(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: nb/intel/ironlake: Account for TSEG alignment
by Angel Pons (Code Review) 07 Aug '23

07 Aug '23

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45920 ) Change subject: nb/intel/ironlake: Account for TSEG alignment ...................................................................... nb/intel/ironlake: Account for TSEG alignment The TSEGMB register has 1 MiB granularity, but do not rely on reserved bits being zero. Raminit aligns TSEG to a 8 MiB boundary, anyway. Change-Id: Iedb63f7c7a29172da187030e33197fc6e4ee23f8 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/memmap.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/45920/1 diff --git a/src/northbridge/intel/ironlake/memmap.c b/src/northbridge/intel/ironlake/memmap.c index 78fbae8..221ae92 100644 --- a/src/northbridge/intel/ironlake/memmap.c +++ b/src/northbridge/intel/ironlake/memmap.c @@ -14,7 +14,7 @@ static uintptr_t northbridge_get_tseg_base(void) { /* Base of TSEG is top of usable DRAM */ - return pci_read_config32(PCI_DEV(0, 0, 0), TSEG); + return ALIGN_DOWN(pci_read_config32(PCI_DEV(0, 0, 0), TSEG), 1 * MiB); } static size_t northbridge_get_tseg_size(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/45920 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iedb63f7c7a29172da187030e33197fc6e4ee23f8 Gerrit-Change-Number: 45920 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: [TESTONLY] .checkpatch.conf: Check SPDX license headers
by Angel Pons (Code Review) 07 Aug '23

07 Aug '23

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46320 ) Change subject: [TESTONLY] .checkpatch.conf: Check SPDX license headers ...................................................................... [TESTONLY] .checkpatch.conf: Check SPDX license headers Change-Id: Ie6d4e019dde23c8d8c3211fff1c19967b0ce7c8a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M .checkpatch.conf 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/46320/1 diff --git a/.checkpatch.conf b/.checkpatch.conf index c294e7b..ac2e530 100644 --- a/.checkpatch.conf +++ b/.checkpatch.conf @@ -17,7 +17,6 @@ --ignore CONFIG_DESCRIPTION --ignore MISSING_SPACE --ignore CORRUPTED_PATCH ---ignore SPDX_LICENSE_TAG --ignore UNDOCUMENTED_DT_STRING --ignore PRINTK_WITHOUT_KERN_LEVEL -- To view, visit https://review.coreboot.org/c/coreboot/+/46320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6d4e019dde23c8d8c3211fff1c19967b0ce7c8a Gerrit-Change-Number: 46320 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/google/dedede: Enable PCI device 14.2
by Meera Ravindranath (Code Review) 07 Aug '23

07 Aug '23

Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46550 ) Change subject: mb/google/dedede: Enable PCI device 14.2 ...................................................................... mb/google/dedede: Enable PCI device 14.2 Enable PCI device 14.2 to align with kernel Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Change-Id: I3eb32218041263f0abef8b9dd4c52efb17289fd7 --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/46550/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index b7aa11d..7236547 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -304,7 +304,7 @@ end end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) - device pci 14.2 off end # PMC SRAM + device pci 14.2 on end # PMC SRAM chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" device pci 14.3 on end # CNVi wifi -- To view, visit https://review.coreboot.org/c/coreboot/+/46550 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3eb32218041263f0abef8b9dd4c52efb17289fd7 Gerrit-Change-Number: 46550 Gerrit-PatchSet: 1 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-MessageType: newchange

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