coreboot-gerrit December 2020

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Change in coreboot[master]: cpu/intel/common: Report the CPU max speed in SMBIOS
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43903 ) Change subject: cpu/intel/common: Report the CPU max speed in SMBIOS ...................................................................... cpu/intel/common: Report the CPU max speed in SMBIOS Use the TSC frequency to provide the maximum processor speed in SMBIOS tables type 4. The TSC frequency is the "Maximum Non-Turbo Ratio" or "Scaleable Bus Speed" on older platforms, times the FSB. Change-Id: I8030187d2c9714c7f6c9451fd2318b3c6608e431 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/intel/common/fsb.c 1 file changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/43903/1 diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c index 7772171..df2e51c 100644 --- a/src/cpu/intel/common/fsb.c +++ b/src/cpu/intel/common/fsb.c @@ -7,6 +7,7 @@ #include <console/console.h> #include <commonlib/helpers.h> #include <delay.h> +#include <smbios.h> static u32 timer_fsb; static u32 timer_tsc; @@ -137,3 +138,17 @@ printk(BIOS_ERR, "FSB not supported or not found\n"); return -1; } + +#if CONFIG(GENERATE_SMBIOS_TABLES) +unsigned int smbios_cpu_get_max_speed_mhz(void) +{ + int ret, fsb, ratio; + + /* Return the Maximum Non-Turbo Ratio (R/O) */ + ret = get_fsb_tsc(&fsb, &ratio); + if (ret == 0) + return fsb * ratio; + + return 0; +} +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/43903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8030187d2c9714c7f6c9451fd2318b3c6608e431 Gerrit-Change-Number: 43903 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: mb/clevo/kbl-u: Enable Gaussian Mixture Model PCI device
by Paul Menzel (Code Review) 07 Aug '23

07 Aug '23

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43936 ) Change subject: mb/clevo/kbl-u: Enable Gaussian Mixture Model PCI device ...................................................................... mb/clevo/kbl-u: Enable Gaussian Mixture Model PCI device Currently, the PCI device is not shown in GNU/Linux. But, the vendor firmware enables it, so let’s do the same. TEST=GMM PCI device is present: 00:08.0 System peripheral [0880]: Intel Corporation Xeon E3-1200 v5/v6 / E3-1500 v5 / 6th/7th/8th Gen Core Processor Gaussian Mixture Model [8086:1911] Change-Id: I94d69015c86d05849d6f3cda6ac45bfabf912658 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb M src/mainboard/clevo/kbl-u/variants/n240bu/devicetree.cb 2 files changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/43936/1 diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb index a92670f..caa3973 100644 --- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb @@ -113,6 +113,8 @@ end device pci 02.0 on end # Integrated Graphics Device + device pci 08.0 on end # Gaussian Mixture Model + device pci 14.0 on # USB xHCI register "SsicPortEnable" = "0" diff --git a/src/mainboard/clevo/kbl-u/variants/n240bu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n240bu/devicetree.cb index 23840cc..bb588ed 100644 --- a/src/mainboard/clevo/kbl-u/variants/n240bu/devicetree.cb +++ b/src/mainboard/clevo/kbl-u/variants/n240bu/devicetree.cb @@ -215,7 +215,7 @@ subsystemid 0x1558 0x2410 inherit end device pci 02.0 on end # Integrated Graphics Device - device pci 08.0 off end # Gaussian Mixture Model + device pci 08.0 on end # Gaussian Mixture Model device pci 14.0 on end # USB xHCI device pci 14.2 on end # Thermal Subsystem device pci 16.0 off end # Management Engine Interface 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/43936 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94d69015c86d05849d6f3cda6ac45bfabf912658 Gerrit-Change-Number: 43936 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: mb/google/kahlee: Set EFS SPI platform configuration
by Matt Papageorge (Code Review) 07 Aug '23

07 Aug '23

Matt Papageorge has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44002 ) Change subject: mb/google/kahlee: Set EFS SPI platform configuration ...................................................................... mb/google/kahlee: Set EFS SPI platform configuration Set platform defaults for SPI settings in Kconfig for EFS for Kahlee based platforms. BUG=b:158755102 TEST=Build test. I have no device for a boot test. Change-Id: I9b979d79ad2dc920e8baf288ddfab04f04f42789 Signed-off-by: Matt Papageorge <matthewpapa07(a)gmail.com> --- M src/mainboard/google/kahlee/Kconfig M src/soc/amd/stoneyridge/Makefile.inc 2 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/44002/1 diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index a9ba0f5..9ce3760 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -127,4 +127,14 @@ config USE_PSPSECUREOS def_bool n +config EFS_SPI_READ_MODE + int + default 4 + default 0 if EM100 + +config EFS_SPI_SPEED + int + default 0 + default 3 if EM100 + endif # BOARD_GOOGLE_BASEBOARD_KAHLEE diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 0d7b5d1..ecb1414 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -193,6 +193,8 @@ SUBPROG_FN_SMU_FW=1 OPT_SMUFWM_FN_FILE=$(call add_opt_prefix, $(SMUFWM_FN_FILE), --subprogram $(SUBPROG_FN_SMU_FW) --smufirmware) OPT_SMUFIRMWARE2_FN_FILE=$(call add_opt_prefix, $(SMUFIRMWARE2_FN_FILE), --subprogram $(SUBPROG_FN_SMU_FW) --smufirmware2) +OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode) +OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) ifeq ($(FIRMWARE_TYPE),ST) OPT_COMBOCAPABLE=--combo-capable @@ -247,6 +249,9 @@ $(OPT_SMUFIRMWARE2_FN_FILE) \ $(OPT_SMUSCS_FILE) \ $(OPT_COMBOCAPABLE)\ + $(OPT_EFS_SPI_READ_MODE) \ + $(OPT_EFS_SPI_SPEED) \ + --soc-name "Stoneyridge" \ --flashsize $(CONFIG_ROM_SIZE) \ --location $(shell printf "0x%x" $(STONEYRIDGE_FWM_POSITION)) \ --output $@ -- To view, visit https://review.coreboot.org/c/coreboot/+/44002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b979d79ad2dc920e8baf288ddfab04f04f42789 Gerrit-Change-Number: 44002 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: [WIP] soc/intel/baytrail: Add libgfxinit support
by Angel Pons (Code Review) 07 Aug '23

07 Aug '23

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44072 ) Change subject: [WIP] soc/intel/baytrail: Add libgfxinit support ...................................................................... [WIP] soc/intel/baytrail: Add libgfxinit support Tested on Asrock Q1900M, lights up. Change-Id: I7c8beea3fc94bd2da94a0caa77dcc1c749c778aa Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/drivers/intel/gma/Kconfig M src/soc/intel/baytrail/gfx.c M src/soc/intel/baytrail/romstage/gfx.c 3 files changed, 13 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/44072/1 diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index c515888..811f59b 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -80,7 +80,7 @@ def_bool y depends on NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X \ || NORTHBRIDGE_INTEL_IRONLAKE || NORTHBRIDGE_INTEL_SANDYBRIDGE \ - || NORTHBRIDGE_INTEL_HASWELL \ + || NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BAYTRAIL \ || SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || SOC_INTEL_APOLLOLAKE \ || SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE \ || SOC_INTEL_WHISKEYLAKE @@ -109,6 +109,7 @@ config GFX_GMA_GENERATION string default "Broxton" if SOC_INTEL_APOLLOLAKE + default "Valleyview" if SOC_INTEL_BAYTRAIL default "Skylake" if SOC_INTEL_SKYLAKE || SOC_INTEL_KABYLAKE || \ SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE default "Haswell" if NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c index 0ee3cef..9062585 100644 --- a/src/soc/intel/baytrail/gfx.c +++ b/src/soc/intel/baytrail/gfx.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <bootmode.h> #include <device/mmio.h> #include <device/pci_ops.h> #include <console/console.h> @@ -7,6 +8,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <drivers/intel/gma/opregion.h> +#include <drivers/intel/gma/libgfxinit.h> #include <reg_script.h> #include <soc/gfx.h> #include <soc/iosf.h> @@ -362,8 +364,14 @@ gfx_panel_setup(dev); - /* Run VBIOS */ - pci_dev_init(dev); + if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { + int lightup_ok; + gma_gfxinit(&lightup_ok); + gfx_set_init_done(lightup_ok); + } else { + /* Run VBIOS */ + pci_dev_init(dev); + } /* Post VBIOS Init */ gfx_post_vbios_init(dev); diff --git a/src/soc/intel/baytrail/romstage/gfx.c b/src/soc/intel/baytrail/romstage/gfx.c index eb0b5e7..c8fac9d 100644 --- a/src/soc/intel/baytrail/romstage/gfx.c +++ b/src/soc/intel/baytrail/romstage/gfx.c @@ -21,7 +21,7 @@ ggc &= ~(GGC_GTT_SIZE_MASK | GGC_GSM_SIZE_MASK); /* 32MB GSM is not supported with <C0 stepping. */ - ggc |= GGC_GTT_SIZE_2MB | GGC_GSM_SIZE_64MB; + ggc |= GGC_GTT_SIZE_2MB | GGC_GSM_SIZE_128MB; /* Enable VGA decoding as well. */ ggc &= ~(GGC_VGA_DISABLE); -- To view, visit https://review.coreboot.org/c/coreboot/+/44072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c8beea3fc94bd2da94a0caa77dcc1c749c778aa Gerrit-Change-Number: 44072 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: soc/intel/cnl: GNA
by Felix Singer (Code Review) 07 Aug '23

07 Aug '23

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44739 ) Change subject: soc/intel/cnl: GNA ...................................................................... soc/intel/cnl: GNA Change-Id: I921e29bfc77c8096519b52fec8bb6b2193006f99 Signed-off-by: Felix Singer <felix.singer(a)secunet.com> --- M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/cannonlake/include/soc/pci_devs.h 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/44739/1 diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 51ed2a8..95da672 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -643,6 +643,9 @@ params->PeiGraphicsPeimInit = 1; else params->PeiGraphicsPeimInit = 0; + + dev = pcidev_path_on_root(SA_DEVFN_GNA); + params->GnaEnable = is_dev_enabled(dev); } /* Mainboard GPIO Configuration */ diff --git a/src/soc/intel/cannonlake/include/soc/pci_devs.h b/src/soc/intel/cannonlake/include/soc/pci_devs.h index c9c51ca..fd43bbd 100644 --- a/src/soc/intel/cannonlake/include/soc/pci_devs.h +++ b/src/soc/intel/cannonlake/include/soc/pci_devs.h @@ -34,6 +34,10 @@ #define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0) #define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0) +#define SA_DEV_SLOT_GNA 0x08 +#define SA_DEVFN_GNA PCI_DEVFN(SA_DEV_SLOT_GNA, 0) +#define SA_DEV_GNA PCI_DEV(0, SA_DEV_SLOT_GNA, 0) + /* PCH Devices */ #define PCH_DEV_SLOT_THERMAL 0x12 #define PCH_DEVFN_THERMAL _PCH_DEVFN(THERMAL, 0) -- To view, visit https://review.coreboot.org/c/coreboot/+/44739 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I921e29bfc77c8096519b52fec8bb6b2193006f99 Gerrit-Change-Number: 44739 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cnl: PEG devices
by Felix Singer (Code Review) 07 Aug '23

07 Aug '23

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44741 ) Change subject: soc/intel/cnl: PEG devices ...................................................................... soc/intel/cnl: PEG devices Change-Id: Ie2dd90edf10f1cefed26fe577508a9c8af3eb532 Signed-off-by: Felix Singer <felix.singer(a)secunet.com> --- M src/soc/intel/cannonlake/include/soc/pci_devs.h M src/soc/intel/cannonlake/romstage/fsp_params.c 2 files changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/44741/1 diff --git a/src/soc/intel/cannonlake/include/soc/pci_devs.h b/src/soc/intel/cannonlake/include/soc/pci_devs.h index b0430e4..35f0e59 100644 --- a/src/soc/intel/cannonlake/include/soc/pci_devs.h +++ b/src/soc/intel/cannonlake/include/soc/pci_devs.h @@ -22,6 +22,16 @@ #define SA_DEV_ROOT PCI_DEV(0, SA_DEV_SLOT_ROOT, 0) #endif +#define SA_DEV_SLOT_PEG 0x01 +#define SA_DEVFN_PEG0 PCI_DEVFN(SA_DEV_SLOT_PEG, 0) +#define SA_DEVFN_PEG1 PCI_DEVFN(SA_DEV_SLOT_PEG, 1) +#define SA_DEVFN_PEG2 PCI_DEVFN(SA_DEV_SLOT_PEG, 2) +#define SA_DEVFN_PEG3 PCI_DEVFN(SA_DEV_SLOT_PEG, 3) +#define SA_DEV_PEG0 PCI_DEV(0, SA_DEV_SLOT_PEG, 0) +#define SA_DEV_PEG1 PCI_DEV(0, SA_DEV_SLOT_PEG, 1) +#define SA_DEV_PEG2 PCI_DEV(0, SA_DEV_SLOT_PEG, 2) +#define SA_DEV_PEG3 PCI_DEV(0, SA_DEV_SLOT_PEG, 3) + #define SA_DEV_SLOT_IGD 0x02 #define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0) #define SA_DEV_IGD PCI_DEV(0, SA_DEV_SLOT_IGD, 0) diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index ac42e00..4b2ad50 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -131,6 +131,20 @@ if (config->DisableHeciRetry) tconfig->DisableHeciRetry = config->DisableHeciRetry; #endif + +#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) + dev = pcidev_path_on_root(SA_DEVFN_PEG0); + m_cfg->Peg0Enable = is_dev_enabled(dev); + + dev = pcidev_path_on_root(SA_DEVFN_PEG1); + m_cfg->Peg1Enable = is_dev_enabled(dev); + + dev = pcidev_path_on_root(SA_DEVFN_PEG2); + m_cfg->Peg2Enable = is_dev_enabled(dev); + + dev = pcidev_path_on_root(SA_DEVFN_PEG3); + m_cfg->Peg3Enable = is_dev_enabled(dev); +#endif } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -- To view, visit https://review.coreboot.org/c/coreboot/+/44741 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie2dd90edf10f1cefed26fe577508a9c8af3eb532 Gerrit-Change-Number: 44741 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: Adds compressed RW blob to RW_A and RW_B
by Sridhar Siricilla (Code Review) 07 Aug '23

07 Aug '23

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44822 ) Change subject: soc/intel/common: Adds compressed RW blob to RW_A and RW_B ...................................................................... soc/intel/common: Adds compressed RW blob to RW_A and RW_B Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Ic4a8797946284359656d3b092fc55812a3de2d37 --- M src/soc/intel/common/block/cse/Makefile.inc 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/44822/1 diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc index 11cc3c2..7ea6fdc 100644 --- a/src/soc/intel/common/block/cse/Makefile.inc +++ b/src/soc/intel/common/block/cse/Makefile.inc @@ -11,4 +11,13 @@ $(CSE_LITE_ME_RW)-file := $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_FILE)) $(CSE_LITE_ME_RW)-name := $(CSE_LITE_ME_RW) $(CSE_LITE_ME_RW)-type := raw +$(CSE_LITE_ME_RW)-compression := lzma + + +CSE_LITE_ME_RW_VER = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_VER_CBFS_NAME)) +regions-for-file-$(CSE_LITE_ME_RW_VER) = FW_MAIN_A,FW_MAIN_B +cbfs-files-y += $(CSE_LITE_ME_RW_VER) +$(CSE_LITE_ME_RW_VER)-file := $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_VER_FILE)) +$(CSE_LITE_ME_RW_VER)-name := $(CSE_LITE_ME_RW_VER) +$(CSE_LITE_ME_RW_VER)-type := raw endif -- To view, visit https://review.coreboot.org/c/coreboot/+/44822 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4a8797946284359656d3b092fc55812a3de2d37 Gerrit-Change-Number: 44822 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [TESTME] mb/bostentech/gbyt4: Add libgfxinit support
by Angel Pons (Code Review) 07 Aug '23

07 Aug '23

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44938 ) Change subject: [TESTME] mb/bostentech/gbyt4: Add libgfxinit support ...................................................................... [TESTME] mb/bostentech/gbyt4: Add libgfxinit support Change-Id: Id729f730f93f5c26b603a5b7a94f671f7fd9bfb7 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/bostentech/gbyt4/Kconfig M src/mainboard/bostentech/gbyt4/Makefile.inc A src/mainboard/bostentech/gbyt4/gma-mainboard.ads 3 files changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/44938/1 diff --git a/src/mainboard/bostentech/gbyt4/Kconfig b/src/mainboard/bostentech/gbyt4/Kconfig index a267840..d5e8bda 100644 --- a/src/mainboard/bostentech/gbyt4/Kconfig +++ b/src/mainboard/bostentech/gbyt4/Kconfig @@ -7,6 +7,7 @@ select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME + select MAINBOARD_HAS_LIBGFXINIT select SUPERIO_ITE_IT8728F config MAINBOARD_DIR diff --git a/src/mainboard/bostentech/gbyt4/Makefile.inc b/src/mainboard/bostentech/gbyt4/Makefile.inc index 11a2a4a..a4fecae 100644 --- a/src/mainboard/bostentech/gbyt4/Makefile.inc +++ b/src/mainboard/bostentech/gbyt4/Makefile.inc @@ -3,3 +3,5 @@ ramstage-y += irqroute.c gpio.c bootblock-y += early_init.c romstage-y += early_init.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/bostentech/gbyt4/gma-mainboard.ads b/src/mainboard/bostentech/gbyt4/gma-mainboard.ads new file mode 100644 index 0000000..c6422a5 --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/gma-mainboard.ads @@ -0,0 +1,15 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (Analog, + others => Disabled); + +end GMA.Mainboard; -- To view, visit https://review.coreboot.org/c/coreboot/+/44938 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id729f730f93f5c26b603a5b7a94f671f7fd9bfb7 Gerrit-Change-Number: 44938 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [DO NOT COMMIT]: TGLRVP Disabling TBT DMA1 for UP4
by Jason V Le (Code Review) 07 Aug '23

07 Aug '23

Hello Bernardo Perez Priego, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45015 to review the following change. Change subject: [DO NOT COMMIT]: TGLRVP Disabling TBT DMA1 for UP4 ...................................................................... [DO NOT COMMIT]: TGLRVP Disabling TBT DMA1 for UP4 Change-Id: Icc61ae8a63bb84ccae74af79b10d1f11644219c3 --- M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/45015/1 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index ccc4df8..928ae36 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -160,7 +160,7 @@ device pci 0d.0 on end # USB xHCI 0x9A13 device pci 0d.1 on end # USB xDCI (OTG) 0x9A15 device pci 0d.2 on end # TBT DMA0 0x9A1B - device pci 0d.3 on end # TBT DMA1 0x9A1D + device pci 0d.3 off end # TBT DMA1 0x9A1D device pci 0e.0 off end # VMD 0x9A0B # From PCH EDS(576591) -- To view, visit https://review.coreboot.org/c/coreboot/+/45015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc61ae8a63bb84ccae74af79b10d1f11644219c3 Gerrit-Change-Number: 45015 Gerrit-PatchSet: 1 Gerrit-Owner: Jason V Le <jason.v.le(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/arch/x86: Fix register accesses for x86_64 debugging
by Martin Schmidt (Code Review) 07 Aug '23

07 Aug '23

Martin Schmidt has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45032 ) Change subject: src/arch/x86: Fix register accesses for x86_64 debugging ...................................................................... src/arch/x86: Fix register accesses for x86_64 debugging Code that interacts with GDB was accessing the eip and eflags filed in the eregs struct. Because those registers are rip and rflags in x86_64, compilation would fail with x86_64 + debugging enabled. Fix compilation by accessing the fields with a macro which expends to the corresponding x86_64 or x86 registers. Signed-off-by: Martin Schmidt <martin.schmidt(a)epita.fr> Change-Id: I07183fe84d083e79ccfda19df82e87c374aed84a --- M src/arch/x86/exception.c M src/arch/x86/include/arch/registers.h 2 files changed, 12 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/45032/1 diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c index f10c7bf..07e2314 100644 --- a/src/arch/x86/exception.c +++ b/src/arch/x86/exception.c @@ -380,9 +380,9 @@ #if CONFIG(GDB_STUB) int signo; memcpy(gdb_stub_registers, info, 8*sizeof(uint32_t)); - gdb_stub_registers[PC] = info->eip; + gdb_stub_registers[PC] = info->X86_ARCH_IP_REGISTER; gdb_stub_registers[CS] = info->cs; - gdb_stub_registers[PS] = info->eflags; + gdb_stub_registers[PS] = info->X86_ARCH_FLAGS_REGISTER; signo = GDB_UNKNOWN; if (info->vector < ARRAY_SIZE(exception_to_signal)) signo = exception_to_signal[info->vector]; @@ -416,9 +416,9 @@ copy_from_hex(&gdb_stub_registers, in_buffer + 1, sizeof(gdb_stub_registers)); memcpy(info, gdb_stub_registers, 8*sizeof(uint32_t)); - info->eip = gdb_stub_registers[PC]; + info->X86_ARCH_IP_REGISTER = gdb_stub_registers[PC]; info->cs = gdb_stub_registers[CS]; - info->eflags = gdb_stub_registers[PS]; + info->X86_ARCH_FLAGS_REGISTER = gdb_stub_registers[PS]; memcpy(out_buffer, "OK", 3); break; case 'm': @@ -452,13 +452,13 @@ */ ptr = &in_buffer[1]; if (parse_ulong(&ptr, &addr)) - info->eip = addr; + info->X86_ARCH_IP_REGISTER = addr; /* Clear the trace bit */ - info->eflags &= ~(1 << 8); + info->X86_ARCH_FLAGS_REGISTER &= ~(1 << 8); /* Set the trace bit if we are single stepping */ if (in_buffer[0] == 's') - info->eflags |= (1 << 8); + info->X86_ARCH_FLAGS_REGISTER |= (1 << 8); return; case 'D': memcpy(out_buffer, "OK", 3); diff --git a/src/arch/x86/include/arch/registers.h b/src/arch/x86/include/arch/registers.h index 5f8f9be..ec3b71a 100644 --- a/src/arch/x86/include/arch/registers.h +++ b/src/arch/x86/include/arch/registers.h @@ -67,6 +67,8 @@ QUAD_DOWNTO16(sp); uint64_t ss; }; +#define X86_ARCH_IP_REGISTER rip +#define X86_ARCH_FLAGS_REGISTER rflags #else struct eregs { LONG_DOWNTO8(a); @@ -83,7 +85,10 @@ uint32_t cs; uint32_t eflags; }; +#define X86_ARCH_IP_REGISTER eip +#define X86_ARCH_FLAGS_REGISTER eflags #endif + #endif // !ASSEMBLER #if CONFIG(COMPILER_LLVM_CLANG) -- To view, visit https://review.coreboot.org/c/coreboot/+/45032 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07183fe84d083e79ccfda19df82e87c374aed84a Gerrit-Change-Number: 45032 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Schmidt Gerrit-MessageType: newchange

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